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From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [Qemu-devel] [PULL 05/27] irq: Add a new irq device that allows the ORing of lines
Date: Tue,  4 Oct 2016 13:42:33 +0100	[thread overview]
Message-ID: <1475584975-25099-6-git-send-email-peter.maydell@linaro.org> (raw)
In-Reply-To: <1475584975-25099-1-git-send-email-peter.maydell@linaro.org>

From: Alistair Francis <alistair23@gmail.com>

Signed-off-by: Alistair Francis <alistair@alistair23.me>
Message-id: 52e5d361e3b5a0ea8554aca73ee65ae2b586112e.1474742262.git.alistair@alistair23.me
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/core/Makefile.objs |   1 +
 hw/core/or-irq.c      | 107 ++++++++++++++++++++++++++++++++++++++++++++++++++
 include/hw/or-irq.h   |  44 +++++++++++++++++++++
 3 files changed, 152 insertions(+)
 create mode 100644 hw/core/or-irq.c
 create mode 100644 include/hw/or-irq.h

diff --git a/hw/core/Makefile.objs b/hw/core/Makefile.objs
index cfd4840..b47241b 100644
--- a/hw/core/Makefile.objs
+++ b/hw/core/Makefile.objs
@@ -16,4 +16,5 @@ common-obj-$(CONFIG_SOFTMMU) += null-machine.o
 common-obj-$(CONFIG_SOFTMMU) += loader.o
 common-obj-$(CONFIG_SOFTMMU) += qdev-properties-system.o
 common-obj-$(CONFIG_SOFTMMU) += register.o
+common-obj-$(CONFIG_SOFTMMU) += or-irq.o
 common-obj-$(CONFIG_PLATFORM_BUS) += platform-bus.o
diff --git a/hw/core/or-irq.c b/hw/core/or-irq.c
new file mode 100644
index 0000000..1ac090d
--- /dev/null
+++ b/hw/core/or-irq.c
@@ -0,0 +1,107 @@
+/*
+ * QEMU IRQ/GPIO common code.
+ *
+ * Copyright (c) 2016 Alistair Francis <alistair@alistair23.me>.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include "qemu/osdep.h"
+#include "hw/or-irq.h"
+
+static void or_irq_handler(void *opaque, int n, int level)
+{
+    qemu_or_irq *s = OR_IRQ(opaque);
+    int or_level = 0;
+    int i;
+
+    s->levels[n] = level;
+
+    for (i = 0; i < s->num_lines; i++) {
+        or_level |= s->levels[i];
+    }
+
+    qemu_set_irq(s->out_irq, or_level);
+}
+
+static void or_irq_reset(DeviceState *dev)
+{
+    qemu_or_irq *s = OR_IRQ(dev);
+    int i;
+
+    for (i = 0; i < MAX_OR_LINES; i++) {
+        s->levels[i] = false;
+    }
+}
+
+static void or_irq_realize(DeviceState *dev, Error **errp)
+{
+    qemu_or_irq *s = OR_IRQ(dev);
+
+    assert(s->num_lines < MAX_OR_LINES);
+
+    qdev_init_gpio_in(dev, or_irq_handler, s->num_lines);
+}
+
+static void or_irq_init(Object *obj)
+{
+    qemu_or_irq *s = OR_IRQ(obj);
+
+    qdev_init_gpio_out(DEVICE(obj), &s->out_irq, 1);
+}
+
+static const VMStateDescription vmstate_or_irq = {
+    .name = TYPE_OR_IRQ,
+    .version_id = 1,
+    .minimum_version_id = 1,
+    .fields = (VMStateField[]) {
+        VMSTATE_BOOL_ARRAY(levels, qemu_or_irq, MAX_OR_LINES),
+        VMSTATE_END_OF_LIST(),
+    }
+};
+
+static Property or_irq_properties[] = {
+    DEFINE_PROP_UINT16("num-lines", qemu_or_irq, num_lines, 1),
+    DEFINE_PROP_END_OF_LIST(),
+};
+
+static void or_irq_class_init(ObjectClass *klass, void *data)
+{
+    DeviceClass *dc = DEVICE_CLASS(klass);
+
+    dc->reset = or_irq_reset;
+    dc->props = or_irq_properties;
+    dc->realize = or_irq_realize;
+    dc->vmsd = &vmstate_or_irq;
+}
+
+static const TypeInfo or_irq_type_info = {
+   .name = TYPE_OR_IRQ,
+   .parent = TYPE_DEVICE,
+   .instance_size = sizeof(qemu_or_irq),
+   .instance_init = or_irq_init,
+   .class_init = or_irq_class_init,
+};
+
+static void or_irq_register_types(void)
+{
+    type_register_static(&or_irq_type_info);
+}
+
+type_init(or_irq_register_types)
diff --git a/include/hw/or-irq.h b/include/hw/or-irq.h
new file mode 100644
index 0000000..d400a81
--- /dev/null
+++ b/include/hw/or-irq.h
@@ -0,0 +1,44 @@
+/*
+ * QEMU IRQ/GPIO common code.
+ *
+ * Copyright (c) 2016 Alistair Francis <alistair@alistair23.me>.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include "hw/irq.h"
+#include "hw/sysbus.h"
+#include "qom/object.h"
+
+#define TYPE_OR_IRQ "or-irq"
+
+#define MAX_OR_LINES      16
+
+typedef struct OrIRQState qemu_or_irq;
+
+#define OR_IRQ(obj) OBJECT_CHECK(qemu_or_irq, (obj), TYPE_OR_IRQ)
+
+struct OrIRQState {
+    DeviceState parent_obj;
+
+    qemu_irq out_irq;
+    qemu_irq *in_irqs;
+    bool levels[MAX_OR_LINES];
+    uint16_t num_lines;
+};
-- 
2.7.4

  parent reply	other threads:[~2016-10-04 12:43 UTC|newest]

Thread overview: 32+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2016-10-04 12:42 [Qemu-devel] [PULL 00/27] target-arm queue Peter Maydell
2016-10-04 12:42 ` [Qemu-devel] [PULL 01/27] STM32F205: Remove the individual device variables Peter Maydell
2016-10-04 12:42 ` [Qemu-devel] [PULL 02/27] STM32F2xx: Display PWM duty cycle from timer Peter Maydell
2016-10-04 12:42 ` [Qemu-devel] [PULL 03/27] STM32F2xx: Add the ADC device Peter Maydell
2016-10-04 12:42 ` [Qemu-devel] [PULL 04/27] STM32F2xx: Add the SPI device Peter Maydell
2016-10-04 12:42 ` Peter Maydell [this message]
2016-10-04 12:42 ` [Qemu-devel] [PULL 06/27] STM32F205: Connect the ADC devices Peter Maydell
2016-10-04 12:42 ` [Qemu-devel] [PULL 07/27] STM32F205: Connect the SPI devices Peter Maydell
2016-10-04 12:42 ` [Qemu-devel] [PULL 08/27] MAINTAINERS: Add Alistair to the maintainers list Peter Maydell
2016-10-04 12:42 ` [Qemu-devel] [PULL 09/27] mainstone: Fix incorrect key mapping for Enter key Peter Maydell
2016-10-04 12:42 ` [Qemu-devel] [PULL 10/27] mainstone: Add mapping for dot, slash and backspace Peter Maydell
2016-10-04 12:42 ` [Qemu-devel] [PULL 11/27] hw/arm: Fix Integrator/CM initialization Peter Maydell
2016-10-04 12:42 ` [Qemu-devel] [PULL 12/27] vmstateify tsc2005 Peter Maydell
2016-10-04 12:42 ` [Qemu-devel] [PULL 13/27] vmstateify tsc210x Peter Maydell
2016-10-04 12:42 ` [Qemu-devel] [PULL 14/27] hw/arm/virt: add 2.8 machine type Peter Maydell
2016-10-04 12:42 ` [Qemu-devel] [PULL 15/27] hw/intc/arm_gic(v3)_kvm: Initialize gsi routing Peter Maydell
2016-10-04 12:42 ` [Qemu-devel] [PULL 16/27] hw/intc/arm_gicv3_its: Implement ITS base class Peter Maydell
2016-10-04 12:42 ` [Qemu-devel] [PULL 17/27] target-arm: move gicv3_class_name from machine to kvm_arm.h Peter Maydell
2016-10-04 12:42 ` [Qemu-devel] [PULL 18/27] kvm-all: Pass requester ID to MSI routing functions Peter Maydell
2016-10-04 12:42 ` [Qemu-devel] [PULL 19/27] hw/intc/arm_gicv3_its: Implement support for in-kernel ITS emulation Peter Maydell
2016-10-04 12:42 ` [Qemu-devel] [PULL 20/27] arm/virt: Add ITS to the virt board Peter Maydell
2016-10-04 12:42 ` [Qemu-devel] [PULL 21/27] ACPI: Add GIC Interrupt Translation Service Structure definition Peter Maydell
2016-10-04 12:42 ` [Qemu-devel] [PULL 22/27] ARM: Virt: ACPI: Add GIC ITS description in ACPI MADT table Peter Maydell
2016-10-04 12:42 ` [Qemu-devel] [PULL 23/27] generic-loader: Add a generic loader Peter Maydell
2016-10-04 12:42 ` [Qemu-devel] [PULL 24/27] docs: Add a generic loader explanation document Peter Maydell
2016-10-04 12:42 ` [Qemu-devel] [PULL 25/27] cadence_gem: Fix priority queue out of bounds access Peter Maydell
2016-10-04 12:42 ` [Qemu-devel] [PULL 26/27] target-arm: A64: Fix decoding of iss_sf in disas_ld_lit Peter Maydell
2016-10-04 12:42 ` [Qemu-devel] [PULL 27/27] target-arm: Correctly handle 'sub pc, pc, 1' for ARMv6 Peter Maydell
2016-10-14  6:44   ` Alex Bennée
2016-10-14 17:35     ` Peter Maydell
2016-10-04 13:19 ` [Qemu-devel] [PULL 00/27] target-arm queue no-reply
2016-10-04 13:24 ` Peter Maydell

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