Re: [PATCH 9/9] drm/i915: Address broxton phy registers based on phy and channel number

[Imre Deak <imre.deak@intel.com>]

On ke, 2016-10-05 at 15:09 +0300, Ander Conselvan de Oliveira wrote:
> The port registers related to the phys in broxton map to different
> channels and specific phys. Make that mapping explicit.
> 
> Signed-off-by: Ander Conselvan de Oliveira 
> ---
>  drivers/gpu/drm/i915/i915_drv.h       |   2 +
>  drivers/gpu/drm/i915/i915_reg.h       | 211 +++++++++++++---------------------
>  drivers/gpu/drm/i915/intel_dpio_phy.c | 131 +++++++++++++++------
>  drivers/gpu/drm/i915/intel_dpll_mgr.c |  84 ++++++++------
>  4 files changed, 222 insertions(+), 206 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 77f1374..c3fa29a 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -3735,6 +3735,8 @@ u32 vlv_flisdsi_read(struct drm_i915_private *dev_priv, u32 reg);
>  void vlv_flisdsi_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
>  
>  /* intel_dpio_phy.c */
> +void bxt_port_to_phy_channel(enum port port,
> +			     u32 *phy, enum dpio_channel *ch);
>  void bxt_ddi_phy_set_signal_level(struct drm_i915_private *dev_priv,
>  				  enum port port, u32 margin, u32 scale,
>  				  u32 enable, u32 deemphasis);
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index d3802c6..416cbb1 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -1187,6 +1187,9 @@ enum skl_disp_power_wells {
>  #define   DPIO_UPAR_SHIFT		30
>  
>  /* BXT PHY registers */
> +#define BXT_PHY1_BASE			0x162000
> +#define BXT_PHY0_BASE			0x6C000
> +
>  #define _BXT_PHY(phy, a, b)		_MMIO_PIPE((phy), (a), (b))
>  
>  #define BXT_P_CR_GT_DISP_PWRON		_MMIO(0x138090)
> @@ -1216,31 +1219,26 @@ enum skl_disp_power_wells {
>  #define   PORT_PLL_REF_SEL		(1 << 27)
>  #define BXT_PORT_PLL_ENABLE(port)	_MMIO_PORT(port, _PORT_PLL_A, _PORT_PLL_B)
>  
> -#define _PORT_PLL_EBB_0_A		0x162034
> -#define _PORT_PLL_EBB_0_B		0x6C034
> -#define _PORT_PLL_EBB_0_C		0x6C340
> +#define _PORT_PLL_EBB_0_CH0		0x34
> +#define _PORT_PLL_EBB_0_CH1		0x340
>  #define   PORT_PLL_P1_SHIFT		13
>  #define   PORT_PLL_P1_MASK		(0x07 << PORT_PLL_P1_SHIFT)
>  #define   PORT_PLL_P1(x)		((x)  << PORT_PLL_P1_SHIFT)
>  #define   PORT_PLL_P2_SHIFT		8
>  #define   PORT_PLL_P2_MASK		(0x1f << PORT_PLL_P2_SHIFT)
>  #define   PORT_PLL_P2(x)		((x)  << PORT_PLL_P2_SHIFT)
> -#define BXT_PORT_PLL_EBB_0(port)	_MMIO_PORT3(port, _PORT_PLL_EBB_0_A, \
> -						_PORT_PLL_EBB_0_B,	\
> -						_PORT_PLL_EBB_0_C)
> +#define BXT_PORT_PLL_EBB_0(base, ch)	\
> +	_MMIO((base) + _PIPE((ch), _PORT_PLL_EBB_0_CH0, _PORT_PLL_EBB_0_CH1))

Passing the phy and calculating the base here would be more natural.
Also we should try to preserve bspec reg names and addresses to make
lookup easier. You could do that by using _PORT_PLL_EBB_0_B
and _PORT_PLL_EBB_0_C here and adjusting the base by -BXT_PHY0_BASE.
I'd also leave _PORT_PLL_EBB_0_A around for reference.

>  
> -#define _PORT_PLL_EBB_4_A		0x162038
> -#define _PORT_PLL_EBB_4_B		0x6C038
> -#define _PORT_PLL_EBB_4_C		0x6C344
> +#define _PORT_PLL_EBB_4_CH0		0x38
> +#define _PORT_PLL_EBB_4_CH1		0x344
>  #define   PORT_PLL_10BIT_CLK_ENABLE	(1 << 13)
>  #define   PORT_PLL_RECALIBRATE		(1 << 14)
> -#define BXT_PORT_PLL_EBB_4(port)	_MMIO_PORT3(port, _PORT_PLL_EBB_4_A, \
> -						_PORT_PLL_EBB_4_B,	\
> -						_PORT_PLL_EBB_4_C)
> +#define BXT_PORT_PLL_EBB_4(base, ch)	\
> +	_MMIO((base) + _PIPE((ch), _PORT_PLL_EBB_4_CH0, _PORT_PLL_EBB_4_CH1))
>  
> -#define _PORT_PLL_0_A			0x162100
> -#define _PORT_PLL_0_B			0x6C100
> -#define _PORT_PLL_0_C			0x6C380
> +#define _PORT_PLL_0_CH0			0x100
> +#define _PORT_PLL_0_CH1			0x380
>  /* PORT_PLL_0_A */
>  #define   PORT_PLL_M2_MASK		0xFF
>  /* PORT_PLL_1_A */
> @@ -1267,65 +1265,43 @@ enum skl_disp_power_wells {
>  #define  PORT_PLL_DCO_AMP_DEFAULT	15
>  #define  PORT_PLL_DCO_AMP_MASK		0x3c00
>  #define  PORT_PLL_DCO_AMP(x)		((x)<<10)
> -#define _PORT_PLL_BASE(port)		_PORT3(port, _PORT_PLL_0_A,	\
> -						_PORT_PLL_0_B,		\
> -						_PORT_PLL_0_C)
> -#define BXT_PORT_PLL(port, idx)		_MMIO(_PORT_PLL_BASE(port) + (idx) * 4)
> +#define _PORT_PLL_BASE(base, ch)	\
> +	((base) + _PIPE((ch), _PORT_PLL_0_CH0, _PORT_PLL_0_CH1))
> +#define BXT_PORT_PLL(base, ch, idx)	\
> +	_MMIO(_PORT_PLL_BASE(base, ch) + (idx) * 4)
>  
>  /* BXT PHY common lane registers */
> -#define _PORT_CL1CM_DW0_A		0x162000
> -#define _PORT_CL1CM_DW0_BC		0x6C000
> +#define BXT_PORT_CL1CM_DW0(base)	_MMIO((base) + 0x0)
>  #define   PHY_POWER_GOOD		(1 << 16)
>  #define   PHY_RESERVED			(1 << 7)
> -#define BXT_PORT_CL1CM_DW0(phy)		_BXT_PHY((phy), _PORT_CL1CM_DW0_BC, \
> -							_PORT_CL1CM_DW0_A)
>  
> -#define _PORT_CL1CM_DW9_A		0x162024
> -#define _PORT_CL1CM_DW9_BC		0x6C024
> +#define BXT_PORT_CL1CM_DW9(base)	_MMIO((base) + 0x24)
>  #define   IREF0RC_OFFSET_SHIFT		8
>  #define   IREF0RC_OFFSET_MASK		(0xFF << IREF0RC_OFFSET_SHIFT)
> -#define BXT_PORT_CL1CM_DW9(phy)		_BXT_PHY((phy), _PORT_CL1CM_DW9_BC, \
> -							_PORT_CL1CM_DW9_A)
>  
> -#define _PORT_CL1CM_DW10_A		0x162028
> -#define _PORT_CL1CM_DW10_BC		0x6C028
> +#define BXT_PORT_CL1CM_DW10(base)	_MMIO((base) + 0x28)
>  #define   IREF1RC_OFFSET_SHIFT		8
>  #define   IREF1RC_OFFSET_MASK		(0xFF << IREF1RC_OFFSET_SHIFT)
> -#define BXT_PORT_CL1CM_DW10(phy)	_BXT_PHY((phy), _PORT_CL1CM_DW10_BC, \
> -							_PORT_CL1CM_DW10_A)
>  
> -#define _PORT_CL1CM_DW28_A		0x162070
> -#define _PORT_CL1CM_DW28_BC		0x6C070
> +#define BXT_PORT_CL1CM_DW28(base)	_MMIO((base) + 0x70)
>  #define   OCL1_POWER_DOWN_EN		(1 << 23)
>  #define   DW28_OLDO_DYN_PWR_DOWN_EN	(1 << 22)
>  #define   SUS_CLK_CONFIG		0x3
> -#define BXT_PORT_CL1CM_DW28(phy)	_BXT_PHY((phy), _PORT_CL1CM_DW28_BC, \
> -							_PORT_CL1CM_DW28_A)
>  
> -#define _PORT_CL1CM_DW30_A		0x162078
> -#define _PORT_CL1CM_DW30_BC		0x6C078
> +#define BXT_PORT_CL1CM_DW30(base)	_MMIO((base) + 0x78)
>  #define   OCL2_LDOFUSE_PWR_DIS		(1 << 6)
> -#define BXT_PORT_CL1CM_DW30(phy)	_BXT_PHY((phy), _PORT_CL1CM_DW30_BC, \
> -							_PORT_CL1CM_DW30_A)
>  
>  /* The spec defines this only for BXT PHY0, but lets assume that this
>   * would exist for PHY1 too if it had a second channel.
>   */
> -#define _PORT_CL2CM_DW6_A		0x162358
> -#define _PORT_CL2CM_DW6_BC		0x6C358
> -#define BXT_PORT_CL2CM_DW6(phy)		_BXT_PHY((phy), _PORT_CL2CM_DW6_BC, \
> -							_PORT_CL2CM_DW6_A)
> +#define BXT_PORT_CL2CM_DW6(base)	_MMIO((base) + 0x358)
>  #define   DW6_OLDO_DYN_PWR_DOWN_EN	(1 << 28)
>  
>  /* BXT PHY Ref registers */
> -#define _PORT_REF_DW3_A			0x16218C
> -#define _PORT_REF_DW3_BC		0x6C18C
> +#define BXT_PORT_REF_DW3(base)		_MMIO((base) + 0x18c)
>  #define   GRC_DONE			(1 << 22)
> -#define BXT_PORT_REF_DW3(phy)		_BXT_PHY((phy), _PORT_REF_DW3_BC, \
> -							_PORT_REF_DW3_A)
>  
> -#define _PORT_REF_DW6_A			0x162198
> -#define _PORT_REF_DW6_BC		0x6C198
> +#define BXT_PORT_REF_DW6(base)		_MMIO((base) + 0x198)
>  #define   GRC_CODE_SHIFT		24
>  #define   GRC_CODE_MASK			(0xFF << GRC_CODE_SHIFT)
>  #define   GRC_CODE_FAST_SHIFT		16
> @@ -1333,113 +1309,88 @@ enum skl_disp_power_wells {
>  #define   GRC_CODE_SLOW_SHIFT		8
>  #define   GRC_CODE_SLOW_MASK		(0xFF << GRC_CODE_SLOW_SHIFT)
>  #define   GRC_CODE_NOM_MASK		0xFF
> -#define BXT_PORT_REF_DW6(phy)		_BXT_PHY((phy), _PORT_REF_DW6_BC,	\
> -						      _PORT_REF_DW6_A)
>  
> -#define _PORT_REF_DW8_A			0x1621A0
> -#define _PORT_REF_DW8_BC		0x6C1A0
> +#define BXT_PORT_REF_DW8(base)		_MMIO((base) + 0x1a0)
>  #define   GRC_DIS			(1 << 15)
>  #define   GRC_RDY_OVRD			(1 << 1)
> -#define BXT_PORT_REF_DW8(phy)		_BXT_PHY((phy), _PORT_REF_DW8_BC,	\
> -						      _PORT_REF_DW8_A)
>  
>  /* BXT PHY PCS registers */
> -#define _PORT_PCS_DW10_LN01_A		0x162428
> -#define _PORT_PCS_DW10_LN01_B		0x6C428
> -#define _PORT_PCS_DW10_LN01_C		0x6C828
> -#define _PORT_PCS_DW10_GRP_A		0x162C28
> -#define _PORT_PCS_DW10_GRP_B		0x6CC28
> -#define _PORT_PCS_DW10_GRP_C		0x6CE28
> -#define BXT_PORT_PCS_DW10_LN01(port)	_MMIO_PORT3(port, _PORT_PCS_DW10_LN01_A, \
> -						     _PORT_PCS_DW10_LN01_B, \
> -						     _PORT_PCS_DW10_LN01_C)
> -#define BXT_PORT_PCS_DW10_GRP(port)	_MMIO_PORT3(port, _PORT_PCS_DW10_GRP_A,  \
> -						     _PORT_PCS_DW10_GRP_B,  \
> -						     _PORT_PCS_DW10_GRP_C)
> +#define _PORT_PCS_DW10_LN01_CH0		0x428
> +#define _PORT_PCS_DW10_LN01_CH1		0x828
> +#define _PORT_PCS_DW10_GRP_CH0		0xC28
> +#define _PORT_PCS_DW10_GRP_CH1		0xE28
>  #define   TX2_SWING_CALC_INIT		(1 << 31)
>  #define   TX1_SWING_CALC_INIT		(1 << 30)
> -
> -#define _PORT_PCS_DW12_LN01_A		0x162430
> -#define _PORT_PCS_DW12_LN01_B		0x6C430
> -#define _PORT_PCS_DW12_LN01_C		0x6C830
> -#define _PORT_PCS_DW12_LN23_A		0x162630
> -#define _PORT_PCS_DW12_LN23_B		0x6C630
> -#define _PORT_PCS_DW12_LN23_C		0x6CA30
> -#define _PORT_PCS_DW12_GRP_A		0x162c30
> -#define _PORT_PCS_DW12_GRP_B		0x6CC30
> -#define _PORT_PCS_DW12_GRP_C		0x6CE30
> +#define BXT_PORT_PCS_DW10_LN01(base, ch)	\
> +	_MMIO((base) + _PIPE(ch, _PORT_PCS_DW10_LN01_CH0,		\
> +			     _PORT_PCS_DW10_LN01_CH1))
> +#define BXT_PORT_PCS_DW10_GRP(base, ch)	\
> +	_MMIO((base) + _PIPE(ch, _PORT_PCS_DW10_GRP_CH0,		\
> +			     _PORT_PCS_DW10_GRP_CH1))
> +
> +#define _PORT_PCS_DW12_LN01_CH0		0x430
> +#define _PORT_PCS_DW12_LN01_CH1		0x830
> +#define _PORT_PCS_DW12_LN23_CH0		0x630
> +#define _PORT_PCS_DW12_LN23_CH1		0xA30
> +#define _PORT_PCS_DW12_GRP_CH0		0xC30
> +#define _PORT_PCS_DW12_GRP_CH1		0xE30
>  #define   LANESTAGGER_STRAP_OVRD	(1 << 6)
>  #define   LANE_STAGGER_MASK		0x1F
> -#define BXT_PORT_PCS_DW12_LN01(port)	_MMIO_PORT3(port, _PORT_PCS_DW12_LN01_A, \
> -						     _PORT_PCS_DW12_LN01_B, \
> -						     _PORT_PCS_DW12_LN01_C)
> -#define BXT_PORT_PCS_DW12_LN23(port)	_MMIO_PORT3(port, _PORT_PCS_DW12_LN23_A, \
> -						     _PORT_PCS_DW12_LN23_B, \
> -						     _PORT_PCS_DW12_LN23_C)
> -#define BXT_PORT_PCS_DW12_GRP(port)	_MMIO_PORT3(port, _PORT_PCS_DW12_GRP_A, \
> -						     _PORT_PCS_DW12_GRP_B, \
> -						     _PORT_PCS_DW12_GRP_C)
> +#define BXT_PORT_PCS_DW12_LN01(base, ch)	\
> +	_MMIO((base) + _PIPE(ch, _PORT_PCS_DW12_LN01_CH0, _PORT_PCS_DW12_LN01_CH1))
> +#define BXT_PORT_PCS_DW12_LN23(base, ch)	\
> +	_MMIO((base) + _PIPE(ch, _PORT_PCS_DW12_LN23_CH0, _PORT_PCS_DW12_LN23_CH1))
> +#define BXT_PORT_PCS_DW12_GRP(base, ch)	\
> +	_MMIO((base) + _PIPE(ch, _PORT_PCS_DW12_GRP_CH0, _PORT_PCS_DW12_GRP_CH1))
>  
>  /* BXT PHY TX registers */
>  #define _BXT_LANE_OFFSET(lane)           (((lane) >> 1) * 0x200 +	\
>  					  ((lane) & 1) * 0x80)
>  
> -#define _PORT_TX_DW2_LN0_A		0x162508
> -#define _PORT_TX_DW2_LN0_B		0x6C508
> -#define _PORT_TX_DW2_LN0_C		0x6C908
> -#define _PORT_TX_DW2_GRP_A		0x162D08
> -#define _PORT_TX_DW2_GRP_B		0x6CD08
> -#define _PORT_TX_DW2_GRP_C		0x6CF08
> -#define BXT_PORT_TX_DW2_GRP(port)	_MMIO_PORT3(port, _PORT_TX_DW2_GRP_A,  \
> -						     _PORT_TX_DW2_GRP_B,  \
> -						     _PORT_TX_DW2_GRP_C)
> -#define BXT_PORT_TX_DW2_LN0(port)	_MMIO_PORT3(port, _PORT_TX_DW2_LN0_A,  \
> -						     _PORT_TX_DW2_LN0_B,  \
> -						     _PORT_TX_DW2_LN0_C)
> +#define _PORT_TX_DW2_LN0_CH0		0x508
> +#define _PORT_TX_DW2_LN0_CH1		0x908
> +#define _PORT_TX_DW2_GRP_CH0		0xD08
> +#define _PORT_TX_DW2_GRP_CH1		0xF08
>  #define   MARGIN_000_SHIFT		16
>  #define   MARGIN_000			(0xFF << MARGIN_000_SHIFT)
>  #define   UNIQ_TRANS_SCALE_SHIFT	8
>  #define   UNIQ_TRANS_SCALE		(0xFF << UNIQ_TRANS_SCALE_SHIFT)
> -
> -#define _PORT_TX_DW3_LN0_A		0x16250C
> -#define _PORT_TX_DW3_LN0_B		0x6C50C
> -#define _PORT_TX_DW3_LN0_C		0x6C90C
> -#define _PORT_TX_DW3_GRP_A		0x162D0C
> -#define _PORT_TX_DW3_GRP_B		0x6CD0C
> -#define _PORT_TX_DW3_GRP_C		0x6CF0C
> -#define BXT_PORT_TX_DW3_GRP(port)	_MMIO_PORT3(port, _PORT_TX_DW3_GRP_A,  \
> -						     _PORT_TX_DW3_GRP_B,  \
> -						     _PORT_TX_DW3_GRP_C)
> -#define BXT_PORT_TX_DW3_LN0(port)	_MMIO_PORT3(port, _PORT_TX_DW3_LN0_A,  \
> -						     _PORT_TX_DW3_LN0_B,  \
> -						     _PORT_TX_DW3_LN0_C)
> +#define BXT_PORT_TX_DW2_GRP(base, ch)	\
> +	_MMIO((base) + _PIPE((ch), _PORT_TX_DW2_GRP_CH0, _PORT_TX_DW2_GRP_CH1))
> +#define BXT_PORT_TX_DW2_LN0(base, ch)	\
> +	_MMIO((base) + _PIPE((ch), _PORT_TX_DW2_LN0_CH0, _PORT_TX_DW2_LN0_CH1))
> +
> +#define _PORT_TX_DW3_LN0_CH0		0x50C
> +#define _PORT_TX_DW3_LN0_CH1		0x90C
> +#define _PORT_TX_DW3_GRP_CH0		0xD0C
> +#define _PORT_TX_DW3_GRP_CH1		0xF0C
>  #define   SCALE_DCOMP_METHOD		(1 << 26)
>  #define   UNIQUE_TRANGE_EN_METHOD	(1 << 27)
> +#define BXT_PORT_TX_DW3_GRP(base, ch)	\
> +	_MMIO((base) + _PIPE((ch), _PORT_TX_DW3_GRP_CH0, _PORT_TX_DW3_GRP_CH1))
> +#define BXT_PORT_TX_DW3_LN0(base, ch)	\
> +	_MMIO((base) + _PIPE((ch), _PORT_TX_DW3_LN0_CH0, _PORT_TX_DW3_LN0_CH1))
> +
>  
> -#define _PORT_TX_DW4_LN0_A		0x162510
> -#define _PORT_TX_DW4_LN0_B		0x6C510
> -#define _PORT_TX_DW4_LN0_C		0x6C910
> -#define _PORT_TX_DW4_GRP_A		0x162D10
> -#define _PORT_TX_DW4_GRP_B		0x6CD10
> -#define _PORT_TX_DW4_GRP_C		0x6CF10
> -#define BXT_PORT_TX_DW4_LN0(port)	_MMIO_PORT3(port, _PORT_TX_DW4_LN0_A,  \
> -						     _PORT_TX_DW4_LN0_B,  \
> -						     _PORT_TX_DW4_LN0_C)
> -#define BXT_PORT_TX_DW4_GRP(port)	_MMIO_PORT3(port, _PORT_TX_DW4_GRP_A,  \
> -						     _PORT_TX_DW4_GRP_B,  \
> -						     _PORT_TX_DW4_GRP_C)
> +#define _PORT_TX_DW4_LN0_CH0		0x510
> +#define _PORT_TX_DW4_LN0_CH1		0x910
> +#define _PORT_TX_DW4_GRP_CH0		0xD10
> +#define _PORT_TX_DW4_GRP_CH1		0xF10
>  #define   DEEMPH_SHIFT			24
>  #define   DE_EMPHASIS			(0xFF << DEEMPH_SHIFT)
> +#define BXT_PORT_TX_DW4_GRP(base, ch)	\
> +	_MMIO((base) + _PIPE((ch), _PORT_TX_DW4_GRP_CH0, _PORT_TX_DW4_GRP_CH1))
> +#define BXT_PORT_TX_DW4_LN0(base, ch)	\
> +	_MMIO((base) + _PIPE((ch), _PORT_TX_DW4_LN0_CH0, _PORT_TX_DW4_LN0_CH1))
>  
> -#define _PORT_TX_DW14_LN0_A		0x162538
> -#define _PORT_TX_DW14_LN0_B		0x6C538
> -#define _PORT_TX_DW14_LN0_C		0x6C938
> +#define _PORT_TX_DW14_LN0_CH0		0x538
> +#define _PORT_TX_DW14_LN0_CH1		0x938
>  #define   LATENCY_OPTIM_SHIFT		30
>  #define   LATENCY_OPTIM			(1 << LATENCY_OPTIM_SHIFT)
> -#define BXT_PORT_TX_DW14_LN(port, lane)	_MMIO(_PORT3((port), _PORT_TX_DW14_LN0_A,   \
> -							_PORT_TX_DW14_LN0_B,   \
> -							_PORT_TX_DW14_LN0_C) + \
> -					 _BXT_LANE_OFFSET(lane))
> +#define BXT_PORT_TX_DW14_LN(base, ch, lane)	\
> +	_MMIO((base) + _PIPE((ch), _PORT_TX_DW14_LN0_CH0,	\
> +				   _PORT_TX_DW14_LN0_CH1) + 	\
> +	      _BXT_LANE_OFFSET(lane))
>  
>  /* UAIMI scratch pad register 1 */
>  #define UAIMI_SPR1			_MMIO(0x4F074)
> diff --git a/drivers/gpu/drm/i915/intel_dpio_phy.c b/drivers/gpu/drm/i915/intel_dpio_phy.c
> index e8a75fd..07ef154 100644
> --- a/drivers/gpu/drm/i915/intel_dpio_phy.c
> +++ b/drivers/gpu/drm/i915/intel_dpio_phy.c
> @@ -124,6 +124,11 @@ struct bxt_ddi_phy_info {
>  	bool dual_channel;
>  
>  	/**
> +	 * @mmio_base: base addess for accessing this PHY through mmio.
> +	 */
> +	u32 mmio_base;
> +
> +	/**
>  	 * @rcomp_phy: If -1, indicates this phy has its own rcomp resistor.
>  	 * Otherwise the GRC value will be copied from the phy indicated by
>  	 * this field.
> @@ -143,6 +148,7 @@ struct bxt_ddi_phy_info {
>  
>  static const struct bxt_ddi_phy_info bxt_ddi_phy_info[] = {
>  	[DPIO_PHY0] = {
> +		.mmio_base = BXT_PHY0_BASE,
>  		.dual_channel = true,
>  		.rcomp_phy = DPIO_PHY1,
>  
> @@ -152,6 +158,7 @@ static const struct bxt_ddi_phy_info bxt_ddi_phy_info[] = {
>  		}
>  	},
>  	[DPIO_PHY1] = {
> +		.mmio_base = BXT_PHY1_BASE,
>  		.dual_channel = false,
>  		.rcomp_phy = -1,
>  
> @@ -167,26 +174,58 @@ static u32 bxt_phy_port_mask(const struct bxt_ddi_phy_info *phy_info)
>  		BIT(phy_info->channel[DPIO_CH0].port);
>  }
>  
> +void bxt_port_to_phy_channel(enum port port,
> +			     u32 *mmio_base, enum dpio_channel *ch)
> +{
> +	const struct bxt_ddi_phy_info *phy_info;
> +	int i;
> +
> +	for (i = 0; i < ARRAY_SIZE(bxt_ddi_phy_info); i++) {
> +		phy_info = &bxt_ddi_phy_info[i];
> +
> +		if (port == phy_info->channel[DPIO_CH0].port) {
> +			*mmio_base = phy_info->mmio_base;
> +			*ch = DPIO_CH0;
> +			return;
> +		}
> +
> +		if (phy_info->dual_channel &&
> +		    port == phy_info->channel[DPIO_CH1].port) {
> +			*mmio_base = phy_info->mmio_base;
> +			*ch = DPIO_CH1;
> +			return;
> +		}
> +	}
> +
> +	WARN(1, "PHY not found for PORT %c", port_name(port));
> +	*mmio_base = BXT_PHY0_BASE;
> +	*ch = DPIO_CH0;
> +}
> +
>  void bxt_ddi_phy_set_signal_level(struct drm_i915_private *dev_priv,
>  				  enum port port, u32 margin, u32 scale,
>  				  u32 enable, u32 deemphasis)
>  {
>  	u32 val;
> +	u32 phy;
> +	enum dpio_channel ch;
> +
> +	bxt_port_to_phy_channel(port, &phy, &ch);
>  
>  	/*
>  	 * While we write to the group register to program all lanes at once we
>  	 * can read only lane registers and we pick lanes 0/1 for that.
>  	 */
> -	val = I915_READ(BXT_PORT_PCS_DW10_LN01(port));
> +	val = I915_READ(BXT_PORT_PCS_DW10_LN01(phy, ch));
>  	val &= ~(TX2_SWING_CALC_INIT | TX1_SWING_CALC_INIT);
> -	I915_WRITE(BXT_PORT_PCS_DW10_GRP(port), val);
> +	I915_WRITE(BXT_PORT_PCS_DW10_GRP(phy, ch), val);
>  
> -	val = I915_READ(BXT_PORT_TX_DW2_LN0(port));
> +	val = I915_READ(BXT_PORT_TX_DW2_LN0(phy, ch));
>  	val &= ~(MARGIN_000 | UNIQ_TRANS_SCALE);
>  	val |= margin << MARGIN_000_SHIFT | scale << UNIQ_TRANS_SCALE_SHIFT;
> -	I915_WRITE(BXT_PORT_TX_DW2_GRP(port), val);
> +	I915_WRITE(BXT_PORT_TX_DW2_GRP(phy, ch), val);
>  
> -	val = I915_READ(BXT_PORT_TX_DW3_LN0(port));
> +	val = I915_READ(BXT_PORT_TX_DW3_LN0(phy, ch));
>  	val &= ~SCALE_DCOMP_METHOD;
>  	if (enable)
>  		val |= SCALE_DCOMP_METHOD;
> @@ -194,16 +233,16 @@ void bxt_ddi_phy_set_signal_level(struct drm_i915_private *dev_priv,
>  	if ((val & UNIQUE_TRANGE_EN_METHOD) && !(val & SCALE_DCOMP_METHOD))
>  		DRM_ERROR("Disabled scaling while ouniqetrangenmethod was set");
>  
> -	I915_WRITE(BXT_PORT_TX_DW3_GRP(port), val);
> +	I915_WRITE(BXT_PORT_TX_DW3_GRP(phy, ch), val);
>  
> -	val = I915_READ(BXT_PORT_TX_DW4_LN0(port));
> +	val = I915_READ(BXT_PORT_TX_DW4_LN0(phy, ch));
>  	val &= ~DE_EMPHASIS;
>  	val |= deemphasis << DEEMPH_SHIFT;
> -	I915_WRITE(BXT_PORT_TX_DW4_GRP(port), val);
> +	I915_WRITE(BXT_PORT_TX_DW4_GRP(phy, ch), val);
>  
> -	val = I915_READ(BXT_PORT_PCS_DW10_LN01(port));
> +	val = I915_READ(BXT_PORT_PCS_DW10_LN01(phy, ch));
>  	val |= TX2_SWING_CALC_INIT | TX1_SWING_CALC_INIT;
> -	I915_WRITE(BXT_PORT_PCS_DW10_GRP(port), val);
> +	I915_WRITE(BXT_PORT_PCS_DW10_GRP(phy, ch), val);
>  }
>  
>  bool bxt_ddi_phy_is_enabled(struct drm_i915_private *dev_priv,
> @@ -215,7 +254,7 @@ bool bxt_ddi_phy_is_enabled(struct drm_i915_private *dev_priv,
>  	if (!(I915_READ(BXT_P_CR_GT_DISP_PWRON) & GT_DISPLAY_POWER_ON(phy)))
>  		return false;
>  
> -	if ((I915_READ(BXT_PORT_CL1CM_DW0(phy)) &
> +	if ((I915_READ(BXT_PORT_CL1CM_DW0(phy_info->mmio_base)) &
>  	     (PHY_POWER_GOOD | PHY_RESERVED)) != PHY_POWER_GOOD) {
>  		DRM_DEBUG_DRIVER("DDI PHY %d powered, but power hasn't settled\n",
>  				 phy);
> @@ -224,7 +263,7 @@ bool bxt_ddi_phy_is_enabled(struct drm_i915_private *dev_priv,
>  	}
>  
>  	if (phy_info->rcomp_phy == -1 &&
> -	    !(I915_READ(BXT_PORT_REF_DW3(phy)) & GRC_DONE)) {
> +	    !(I915_READ(BXT_PORT_REF_DW3(phy_info->mmio_base)) & GRC_DONE)) {
>  		DRM_DEBUG_DRIVER("DDI PHY %d powered, but GRC isn't done\n",
>  				 phy);
>  
> @@ -256,7 +295,11 @@ bool bxt_ddi_phy_is_enabled(struct drm_i915_private *dev_priv,
>  
>  static u32 bxt_get_grc(struct drm_i915_private *dev_priv, enum dpio_phy phy)
>  {
> -	u32 val = I915_READ(BXT_PORT_REF_DW6(phy));
> +	const struct bxt_ddi_phy_info *phy_info;
> +	u32 val;
> +
> +	phy_info = &bxt_ddi_phy_info[phy];
> +	val = I915_READ(BXT_PORT_REF_DW6(phy_info->mmio_base));
>  
>  	return (val & GRC_CODE_MASK) >> GRC_CODE_SHIFT;
>  }
> @@ -264,8 +307,12 @@ static u32 bxt_get_grc(struct drm_i915_private *dev_priv, enum dpio_phy phy)
>  static void bxt_phy_wait_grc_done(struct drm_i915_private *dev_priv,
>  				  enum dpio_phy phy)
>  {
> +	const struct bxt_ddi_phy_info *phy_info;
> +
> +	phy_info = &bxt_ddi_phy_info[phy];
> +
>  	if (intel_wait_for_register(dev_priv,
> -				    BXT_PORT_REF_DW3(phy),
> +				    BXT_PORT_REF_DW3(phy_info->mmio_base),
>  				    GRC_DONE, GRC_DONE,
>  				    10))
>  		DRM_ERROR("timeout waiting for PHY%d GRC\n", phy);
> @@ -305,35 +352,35 @@ static void _bxt_ddi_phy_init(struct drm_i915_private *dev_priv,
>  	 * HW team confirmed that the time to reach phypowergood status is
>  	 * anywhere between 50 us and 100us.
>  	 */
> -	if (wait_for_us(((I915_READ(BXT_PORT_CL1CM_DW0(phy)) &
> +	if (wait_for_us(((I915_READ(BXT_PORT_CL1CM_DW0(phy_info->mmio_base)) &
>  		(PHY_RESERVED | PHY_POWER_GOOD)) == PHY_POWER_GOOD), 100)) {
>  		DRM_ERROR("timeout during PHY%d power on\n", phy);
>  	}
>  
>  	/* Program PLL Rcomp code offset */
> -	val = I915_READ(BXT_PORT_CL1CM_DW9(phy));
> +	val = I915_READ(BXT_PORT_CL1CM_DW9(phy_info->mmio_base));
>  	val &= ~IREF0RC_OFFSET_MASK;
>  	val |= 0xE4 << IREF0RC_OFFSET_SHIFT;
> -	I915_WRITE(BXT_PORT_CL1CM_DW9(phy), val);
> +	I915_WRITE(BXT_PORT_CL1CM_DW9(phy_info->mmio_base), val);
>  
> -	val = I915_READ(BXT_PORT_CL1CM_DW10(phy));
> +	val = I915_READ(BXT_PORT_CL1CM_DW10(phy_info->mmio_base));
>  	val &= ~IREF1RC_OFFSET_MASK;
>  	val |= 0xE4 << IREF1RC_OFFSET_SHIFT;
> -	I915_WRITE(BXT_PORT_CL1CM_DW10(phy), val);
> +	I915_WRITE(BXT_PORT_CL1CM_DW10(phy_info->mmio_base), val);
>  
>  	/* Program power gating */
> -	val = I915_READ(BXT_PORT_CL1CM_DW28(phy));
> +	val = I915_READ(BXT_PORT_CL1CM_DW28(phy_info->mmio_base));
>  	val |= OCL1_POWER_DOWN_EN | DW28_OLDO_DYN_PWR_DOWN_EN |
>  		SUS_CLK_CONFIG;
> -	I915_WRITE(BXT_PORT_CL1CM_DW28(phy), val);
> +	I915_WRITE(BXT_PORT_CL1CM_DW28(phy_info->mmio_base), val);
>  
>  	if (phy_info->dual_channel) {
> -		val = I915_READ(BXT_PORT_CL2CM_DW6(phy));
> +		val = I915_READ(BXT_PORT_CL2CM_DW6(phy_info->mmio_base));
>  		val |= DW6_OLDO_DYN_PWR_DOWN_EN;
> -		I915_WRITE(BXT_PORT_CL2CM_DW6(phy), val);
> +		I915_WRITE(BXT_PORT_CL2CM_DW6(phy_info->mmio_base), val);
>  	}
>  
> -	val = I915_READ(BXT_PORT_CL1CM_DW30(phy));
> +	val = I915_READ(BXT_PORT_CL1CM_DW30(phy_info->mmio_base));
>  	val &= ~OCL2_LDOFUSE_PWR_DIS;
>  	/*
>  	 * On PHY1 disable power on the second channel, since no port is
> @@ -347,7 +394,7 @@ static void _bxt_ddi_phy_init(struct drm_i915_private *dev_priv,
>  	 */
>  	if (!phy_info->dual_channel)
>  		val |= OCL2_LDOFUSE_PWR_DIS;
> -	I915_WRITE(BXT_PORT_CL1CM_DW30(phy), val);
> +	I915_WRITE(BXT_PORT_CL1CM_DW30(phy_info->mmio_base), val);
>  
>  	if (phy_info->rcomp_phy != -1) {
>  		uint32_t grc_code;
> @@ -361,11 +408,11 @@ static void _bxt_ddi_phy_init(struct drm_i915_private *dev_priv,
>  		grc_code = val << GRC_CODE_FAST_SHIFT |
>  			   val << GRC_CODE_SLOW_SHIFT |
>  			   val;
> -		I915_WRITE(BXT_PORT_REF_DW6(phy), grc_code);
> +		I915_WRITE(BXT_PORT_REF_DW6(phy_info->mmio_base), grc_code);
>  
> -		val = I915_READ(BXT_PORT_REF_DW8(phy));
> +		val = I915_READ(BXT_PORT_REF_DW8(phy_info->mmio_base));
>  		val |= GRC_DIS | GRC_RDY_OVRD;
> -		I915_WRITE(BXT_PORT_REF_DW8(phy), val);
> +		I915_WRITE(BXT_PORT_REF_DW8(phy_info->mmio_base), val);
>  	}
>  
>  	val = I915_READ(BXT_PHY_CTL_FAMILY(phy));
> @@ -461,20 +508,20 @@ bool bxt_ddi_phy_verify_state(struct drm_i915_private *dev_priv,
>  	ok = true;
>  
>  	/* PLL Rcomp code offset */
> -	ok &= _CHK(BXT_PORT_CL1CM_DW9(phy),
> +	ok &= _CHK(BXT_PORT_CL1CM_DW9(phy_info->mmio_base),
>  		    IREF0RC_OFFSET_MASK, 0xe4 << IREF0RC_OFFSET_SHIFT,
>  		    "BXT_PORT_CL1CM_DW9(%d)", phy);
> -	ok &= _CHK(BXT_PORT_CL1CM_DW10(phy),
> +	ok &= _CHK(BXT_PORT_CL1CM_DW10(phy_info->mmio_base),
>  		    IREF1RC_OFFSET_MASK, 0xe4 << IREF1RC_OFFSET_SHIFT,
>  		    "BXT_PORT_CL1CM_DW10(%d)", phy);
>  
>  	/* Power gating */
>  	mask = OCL1_POWER_DOWN_EN | DW28_OLDO_DYN_PWR_DOWN_EN | SUS_CLK_CONFIG;
> -	ok &= _CHK(BXT_PORT_CL1CM_DW28(phy), mask, mask,
> +	ok &= _CHK(BXT_PORT_CL1CM_DW28(phy_info->mmio_base), mask, mask,
>  		    "BXT_PORT_CL1CM_DW28(%d)", phy);
>  
>  	if (phy_info->dual_channel)
> -		ok &= _CHK(BXT_PORT_CL2CM_DW6(phy),
> +		ok &= _CHK(BXT_PORT_CL2CM_DW6(phy_info->mmio_base),
>  			   DW6_OLDO_DYN_PWR_DOWN_EN, DW6_OLDO_DYN_PWR_DOWN_EN,
>  			   "BXT_PORT_CL2CM_DW6(%d)", phy);
>  
> @@ -491,11 +538,11 @@ bool bxt_ddi_phy_verify_state(struct drm_i915_private *dev_priv,
>  			   grc_code;
>  		mask = GRC_CODE_FAST_MASK | GRC_CODE_SLOW_MASK |
>  		       GRC_CODE_NOM_MASK;
> -		ok &= _CHK(BXT_PORT_REF_DW6(phy), mask, grc_code,
> -			    "BXT_PORT_REF_DW6(%d)", phy);
> +		ok &= _CHK(BXT_PORT_REF_DW6(phy_info->mmio_base), mask,
> +			   grc_code, "BXT_PORT_REF_DW6(%d)", phy);
>  
>  		mask = GRC_DIS | GRC_RDY_OVRD;
> -		ok &= _CHK(BXT_PORT_REF_DW8(phy), mask, mask,
> +		ok &= _CHK(BXT_PORT_REF_DW8(phy_info->mmio_base), mask, mask,
>  			    "BXT_PORT_REF_DW8(%d)", phy);
>  	}
>  
> @@ -527,10 +574,14 @@ void bxt_ddi_phy_set_lane_optim_mask(struct intel_encoder *encoder,
>  	struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
>  	struct drm_i915_private *dev_priv = to_i915(dport->base.base.dev);
>  	enum port port = dport->port;
> +	u32 phy;
> +	enum dpio_channel ch;
>  	int lane;
>  
> +	bxt_port_to_phy_channel(port, &phy, &ch);
> +
>  	for (lane = 0; lane < 4; lane++) {
> -		u32 val = I915_READ(BXT_PORT_TX_DW14_LN(port, lane));
> +		u32 val = I915_READ(BXT_PORT_TX_DW14_LN(phy, ch, lane));
>  
>  		/*
>  		 * Note that on CHV this flag is called UPAR, but has
> @@ -540,7 +591,7 @@ void bxt_ddi_phy_set_lane_optim_mask(struct intel_encoder *encoder,
>  		if (lane_lat_optim_mask & BIT(lane))
>  			val |= LATENCY_OPTIM;
>  
> -		I915_WRITE(BXT_PORT_TX_DW14_LN(port, lane), val);
> +		I915_WRITE(BXT_PORT_TX_DW14_LN(phy, ch, lane), val);
>  	}
>  }
>  
> @@ -550,12 +601,16 @@ bxt_ddi_phy_get_lane_lat_optim_mask(struct intel_encoder *encoder)
>  	struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
>  	struct drm_i915_private *dev_priv = to_i915(dport->base.base.dev);
>  	enum port port = dport->port;
> +	u32 phy;
> +	enum dpio_channel ch;
>  	int lane;
>  	uint8_t mask;
>  
> +	bxt_port_to_phy_channel(port, &phy, &ch);
> +
>  	mask = 0;
>  	for (lane = 0; lane < 4; lane++) {
> -		u32 val = I915_READ(BXT_PORT_TX_DW14_LN(port, lane));
> +		u32 val = I915_READ(BXT_PORT_TX_DW14_LN(phy, ch, lane));
>  
>  		if (val & LATENCY_OPTIM)
>  			mask |= BIT(lane);
> diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.c b/drivers/gpu/drm/i915/intel_dpll_mgr.c
> index 1c59ca5..a4a9f05 100644
> --- a/drivers/gpu/drm/i915/intel_dpll_mgr.c
> +++ b/drivers/gpu/drm/i915/intel_dpll_mgr.c
> @@ -1371,6 +1371,10 @@ static void bxt_ddi_pll_enable(struct drm_i915_private *dev_priv,
>  {
>  	uint32_t temp;
>  	enum port port = (enum port)pll->id;	/* 1:1 port->PLL mapping */
> +	u32 phy;
> +	enum dpio_channel ch;
> +
> +	bxt_port_to_phy_channel(port, &phy, &ch);
>  
>  	/* Non-SSC reference */
>  	temp = I915_READ(BXT_PORT_PLL_ENABLE(port));
> @@ -1378,72 +1382,72 @@ static void bxt_ddi_pll_enable(struct drm_i915_private *dev_priv,
>  	I915_WRITE(BXT_PORT_PLL_ENABLE(port), temp);
>  
>  	/* Disable 10 bit clock */
> -	temp = I915_READ(BXT_PORT_PLL_EBB_4(port));
> +	temp = I915_READ(BXT_PORT_PLL_EBB_4(phy, ch));
>  	temp &= ~PORT_PLL_10BIT_CLK_ENABLE;
> -	I915_WRITE(BXT_PORT_PLL_EBB_4(port), temp);
> +	I915_WRITE(BXT_PORT_PLL_EBB_4(phy, ch), temp);
>  
>  	/* Write P1 & P2 */
> -	temp = I915_READ(BXT_PORT_PLL_EBB_0(port));
> +	temp = I915_READ(BXT_PORT_PLL_EBB_0(phy, ch));
>  	temp &= ~(PORT_PLL_P1_MASK | PORT_PLL_P2_MASK);
>  	temp |= pll->config.hw_state.ebb0;
> -	I915_WRITE(BXT_PORT_PLL_EBB_0(port), temp);
> +	I915_WRITE(BXT_PORT_PLL_EBB_0(phy, ch), temp);
>  
>  	/* Write M2 integer */
> -	temp = I915_READ(BXT_PORT_PLL(port, 0));
> +	temp = I915_READ(BXT_PORT_PLL(phy, ch, 0));
>  	temp &= ~PORT_PLL_M2_MASK;
>  	temp |= pll->config.hw_state.pll0;
> -	I915_WRITE(BXT_PORT_PLL(port, 0), temp);
> +	I915_WRITE(BXT_PORT_PLL(phy, ch, 0), temp);
>  
>  	/* Write N */
> -	temp = I915_READ(BXT_PORT_PLL(port, 1));
> +	temp = I915_READ(BXT_PORT_PLL(phy, ch, 1));
>  	temp &= ~PORT_PLL_N_MASK;
>  	temp |= pll->config.hw_state.pll1;
> -	I915_WRITE(BXT_PORT_PLL(port, 1), temp);
> +	I915_WRITE(BXT_PORT_PLL(phy, ch, 1), temp);
>  
>  	/* Write M2 fraction */
> -	temp = I915_READ(BXT_PORT_PLL(port, 2));
> +	temp = I915_READ(BXT_PORT_PLL(phy, ch, 2));
>  	temp &= ~PORT_PLL_M2_FRAC_MASK;
>  	temp |= pll->config.hw_state.pll2;
> -	I915_WRITE(BXT_PORT_PLL(port, 2), temp);
> +	I915_WRITE(BXT_PORT_PLL(phy, ch, 2), temp);
>  
>  	/* Write M2 fraction enable */
> -	temp = I915_READ(BXT_PORT_PLL(port, 3));
> +	temp = I915_READ(BXT_PORT_PLL(phy, ch, 3));
>  	temp &= ~PORT_PLL_M2_FRAC_ENABLE;
>  	temp |= pll->config.hw_state.pll3;
> -	I915_WRITE(BXT_PORT_PLL(port, 3), temp);
> +	I915_WRITE(BXT_PORT_PLL(phy, ch, 3), temp);
>  
>  	/* Write coeff */
> -	temp = I915_READ(BXT_PORT_PLL(port, 6));
> +	temp = I915_READ(BXT_PORT_PLL(phy, ch, 6));
>  	temp &= ~PORT_PLL_PROP_COEFF_MASK;
>  	temp &= ~PORT_PLL_INT_COEFF_MASK;
>  	temp &= ~PORT_PLL_GAIN_CTL_MASK;
>  	temp |= pll->config.hw_state.pll6;
> -	I915_WRITE(BXT_PORT_PLL(port, 6), temp);
> +	I915_WRITE(BXT_PORT_PLL(phy, ch, 6), temp);
>  
>  	/* Write calibration val */
> -	temp = I915_READ(BXT_PORT_PLL(port, 8));
> +	temp = I915_READ(BXT_PORT_PLL(phy, ch, 8));
>  	temp &= ~PORT_PLL_TARGET_CNT_MASK;
>  	temp |= pll->config.hw_state.pll8;
> -	I915_WRITE(BXT_PORT_PLL(port, 8), temp);
> +	I915_WRITE(BXT_PORT_PLL(phy, ch, 8), temp);
>  
> -	temp = I915_READ(BXT_PORT_PLL(port, 9));
> +	temp = I915_READ(BXT_PORT_PLL(phy, ch, 9));
>  	temp &= ~PORT_PLL_LOCK_THRESHOLD_MASK;
>  	temp |= pll->config.hw_state.pll9;
> -	I915_WRITE(BXT_PORT_PLL(port, 9), temp);
> +	I915_WRITE(BXT_PORT_PLL(phy, ch, 9), temp);
>  
> -	temp = I915_READ(BXT_PORT_PLL(port, 10));
> +	temp = I915_READ(BXT_PORT_PLL(phy, ch, 10));
>  	temp &= ~PORT_PLL_DCO_AMP_OVR_EN_H;
>  	temp &= ~PORT_PLL_DCO_AMP_MASK;
>  	temp |= pll->config.hw_state.pll10;
> -	I915_WRITE(BXT_PORT_PLL(port, 10), temp);
> +	I915_WRITE(BXT_PORT_PLL(phy, ch, 10), temp);
>  
>  	/* Recalibrate with new settings */
> -	temp = I915_READ(BXT_PORT_PLL_EBB_4(port));
> +	temp = I915_READ(BXT_PORT_PLL_EBB_4(phy, ch));
>  	temp |= PORT_PLL_RECALIBRATE;
> -	I915_WRITE(BXT_PORT_PLL_EBB_4(port), temp);
> +	I915_WRITE(BXT_PORT_PLL_EBB_4(phy, ch), temp);
>  	temp &= ~PORT_PLL_10BIT_CLK_ENABLE;
>  	temp |= pll->config.hw_state.ebb4;
> -	I915_WRITE(BXT_PORT_PLL_EBB_4(port), temp);
> +	I915_WRITE(BXT_PORT_PLL_EBB_4(phy, ch), temp);
>  
>  	/* Enable PLL */
>  	temp = I915_READ(BXT_PORT_PLL_ENABLE(port));
> @@ -1459,11 +1463,11 @@ static void bxt_ddi_pll_enable(struct drm_i915_private *dev_priv,
>  	 * While we write to the group register to program all lanes at once we
>  	 * can read only lane registers and we pick lanes 0/1 for that.
>  	 */
> -	temp = I915_READ(BXT_PORT_PCS_DW12_LN01(port));
> +	temp = I915_READ(BXT_PORT_PCS_DW12_LN01(phy, ch));
>  	temp &= ~LANE_STAGGER_MASK;
>  	temp &= ~LANESTAGGER_STRAP_OVRD;
>  	temp |= pll->config.hw_state.pcsdw12;
> -	I915_WRITE(BXT_PORT_PCS_DW12_GRP(port), temp);
> +	I915_WRITE(BXT_PORT_PCS_DW12_GRP(phy, ch), temp);
>  }
>  
>  static void bxt_ddi_pll_disable(struct drm_i915_private *dev_priv,
> @@ -1485,6 +1489,10 @@ static bool bxt_ddi_pll_get_hw_state(struct drm_i915_private *dev_priv,
>  	enum port port = (enum port)pll->id;	/* 1:1 port->PLL mapping */
>  	uint32_t val;
>  	bool ret;
> +	u32 phy;
> +	enum dpio_channel ch;
> +
> +	bxt_port_to_phy_channel(port, &phy, &ch);
>  
>  	if (!intel_display_power_get_if_enabled(dev_priv, POWER_DOMAIN_PLLS))
>  		return false;
> @@ -1495,36 +1503,36 @@ static bool bxt_ddi_pll_get_hw_state(struct drm_i915_private *dev_priv,
>  	if (!(val & PORT_PLL_ENABLE))
>  		goto out;
>  
> -	hw_state->ebb0 = I915_READ(BXT_PORT_PLL_EBB_0(port));
> +	hw_state->ebb0 = I915_READ(BXT_PORT_PLL_EBB_0(phy, ch));
>  	hw_state->ebb0 &= PORT_PLL_P1_MASK | PORT_PLL_P2_MASK;
>  
> -	hw_state->ebb4 = I915_READ(BXT_PORT_PLL_EBB_4(port));
> +	hw_state->ebb4 = I915_READ(BXT_PORT_PLL_EBB_4(phy, ch));
>  	hw_state->ebb4 &= PORT_PLL_10BIT_CLK_ENABLE;
>  
> -	hw_state->pll0 = I915_READ(BXT_PORT_PLL(port, 0));
> +	hw_state->pll0 = I915_READ(BXT_PORT_PLL(phy, ch, 0));
>  	hw_state->pll0 &= PORT_PLL_M2_MASK;
>  
> -	hw_state->pll1 = I915_READ(BXT_PORT_PLL(port, 1));
> +	hw_state->pll1 = I915_READ(BXT_PORT_PLL(phy, ch, 1));
>  	hw_state->pll1 &= PORT_PLL_N_MASK;
>  
> -	hw_state->pll2 = I915_READ(BXT_PORT_PLL(port, 2));
> +	hw_state->pll2 = I915_READ(BXT_PORT_PLL(phy, ch, 2));
>  	hw_state->pll2 &= PORT_PLL_M2_FRAC_MASK;
>  
> -	hw_state->pll3 = I915_READ(BXT_PORT_PLL(port, 3));
> +	hw_state->pll3 = I915_READ(BXT_PORT_PLL(phy, ch, 3));
>  	hw_state->pll3 &= PORT_PLL_M2_FRAC_ENABLE;
>  
> -	hw_state->pll6 = I915_READ(BXT_PORT_PLL(port, 6));
> +	hw_state->pll6 = I915_READ(BXT_PORT_PLL(phy, ch, 6));
>  	hw_state->pll6 &= PORT_PLL_PROP_COEFF_MASK |
>  			  PORT_PLL_INT_COEFF_MASK |
>  			  PORT_PLL_GAIN_CTL_MASK;
>  
> -	hw_state->pll8 = I915_READ(BXT_PORT_PLL(port, 8));
> +	hw_state->pll8 = I915_READ(BXT_PORT_PLL(phy, ch, 8));
>  	hw_state->pll8 &= PORT_PLL_TARGET_CNT_MASK;
>  
> -	hw_state->pll9 = I915_READ(BXT_PORT_PLL(port, 9));
> +	hw_state->pll9 = I915_READ(BXT_PORT_PLL(phy, ch, 9));
>  	hw_state->pll9 &= PORT_PLL_LOCK_THRESHOLD_MASK;
>  
> -	hw_state->pll10 = I915_READ(BXT_PORT_PLL(port, 10));
> +	hw_state->pll10 = I915_READ(BXT_PORT_PLL(phy, ch, 10));
>  	hw_state->pll10 &= PORT_PLL_DCO_AMP_OVR_EN_H |
>  			   PORT_PLL_DCO_AMP_MASK;
>  
> @@ -1533,11 +1541,11 @@ static bool bxt_ddi_pll_get_hw_state(struct drm_i915_private *dev_priv,
>  	 * can read only lane registers. We configure all lanes the same way, so
>  	 * here just read out lanes 0/1 and output a note if lanes 2/3 differ.
>  	 */
> -	hw_state->pcsdw12 = I915_READ(BXT_PORT_PCS_DW12_LN01(port));
> -	if (I915_READ(BXT_PORT_PCS_DW12_LN23(port)) != hw_state->pcsdw12)
> +	hw_state->pcsdw12 = I915_READ(BXT_PORT_PCS_DW12_LN01(phy, ch));
> +	if (I915_READ(BXT_PORT_PCS_DW12_LN23(phy, ch)) != hw_state->pcsdw12)
>  		DRM_DEBUG_DRIVER("lane stagger config different for lane 01 (%08x) and 23 (%08x)\n",
>  				 hw_state->pcsdw12,
> -				 I915_READ(BXT_PORT_PCS_DW12_LN23(port)));
> +				 I915_READ(BXT_PORT_PCS_DW12_LN23(phy, ch)));
>  	hw_state->pcsdw12 &= LANE_STAGGER_MASK | LANESTAGGER_STRAP_OVRD;
>  
>  	ret = true;
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