From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S936253AbcJFXPM (ORCPT ); Thu, 6 Oct 2016 19:15:12 -0400 Received: from p3plsmtpa12-02.prod.phx3.secureserver.net ([68.178.252.231]:46044 "EHLO p3plsmtpa12-02.prod.phx3.secureserver.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S935057AbcJFXPE (ORCPT ); Thu, 6 Oct 2016 19:15:04 -0400 X-Greylist: delayed 1211 seconds by postgrey-1.27 at vger.kernel.org; Thu, 06 Oct 2016 19:15:04 EDT From: Aaron Brice To: david.russell@datasoft.com, adrian.hunter@intel.com, ulf.hansson@linaro.org, aisheng.dong@nxp.com Cc: linux-mmc@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH] sdhci-esdhc-imx: Correct two register accesses Date: Thu, 6 Oct 2016 15:54:17 -0700 Message-Id: <1475794457-17993-1-git-send-email-aaron.brice@datasoft.com> X-Mailer: git-send-email 2.7.4 X-CMAE-Envelope: MS4wfIJRvQDlhlH5GeDGCke84KhldwL6onmFYYABUsX+CZw9vM0/lsrJrycz6a7QZ2+A4FfZc8tIW9+DNgfW3cB3qCytRGOYIBLVAPMynWjMtn1o3Na5Wgu1 jMojSU6rsjf8pEbnaM2QIhQ/GOEaeSzcCv9Y8+J/67DPn/M6UjYp073DUjbTD83eGY1xGGYs47pEydjq8fOTqTi/M8bsRYKu6+tjPd4jzPnK15EI7HH9mz4z paCMoBqCdOgFOcbsNtJsqggDv5CWn6oPy040W4ntKeLSFci/VHGvoZArWoihIIXwQfRU/hfU8lt34/FKScYg1xBB7KiYQTwsHW0EbxFbSb0lqSN2Xj7fze6+ NVscLqtDeLTlosB14mad1lVD+DptyxBSLIz2uKCNINckHC3Q1Khom4VTwcVDc7Gi/a/5vIfwH8QwJPDZu4ETWZQI7mCR7A== Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org - The DMA error interrupt bit is in a different position as compared to the sdhci standard. This is accounted for in many cases, but not handled in the case of clearing the INT_STATUS register by writing a 1 to that location. - The HOST_CONTROL register is very different as compared to the sdhci standard. This is accounted for in the write case, but not when read back out (which it is in the sdhci code). Signed-off-by: Dave Russell Signed-off-by: Aaron Brice --- drivers/mmc/host/sdhci-esdhc-imx.c | 23 ++++++++++++++++++++++- 1 file changed, 22 insertions(+), 1 deletion(-) diff --git a/drivers/mmc/host/sdhci-esdhc-imx.c b/drivers/mmc/host/sdhci-esdhc-imx.c index 1f54fd8..d61ef16 100644 --- a/drivers/mmc/host/sdhci-esdhc-imx.c +++ b/drivers/mmc/host/sdhci-esdhc-imx.c @@ -346,7 +346,8 @@ static void esdhc_writel_le(struct sdhci_host *host, u32 val, int reg) struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host); u32 data; - if (unlikely(reg == SDHCI_INT_ENABLE || reg == SDHCI_SIGNAL_ENABLE)) { + if (unlikely(reg == SDHCI_INT_ENABLE || reg == SDHCI_SIGNAL_ENABLE || + reg == SDHCI_INT_STATUS)) { if ((val & SDHCI_INT_CARD_INT) && !esdhc_is_usdhc(imx_data)) { /* * Clear and then set D3CD bit to avoid missing the @@ -555,6 +556,25 @@ static void esdhc_writew_le(struct sdhci_host *host, u16 val, int reg) esdhc_clrset_le(host, 0xffff, val, reg); } +static u8 esdhc_readb_le(struct sdhci_host *host, int reg) +{ + u8 ret; + u32 long_val; + + switch (reg) { + case SDHCI_HOST_CONTROL: + long_val = readl(host->ioaddr + reg); + + ret = long_val & SDHCI_CTRL_LED; + ret |= (long_val >> 5) & SDHCI_CTRL_DMA_MASK; + ret |= (long_val & ESDHC_CTRL_4BITBUS); + ret |= (long_val & ESDHC_CTRL_8BITBUS) << 3; + return ret; + } + + return readb(host->ioaddr + reg); +} + static void esdhc_writeb_le(struct sdhci_host *host, u8 val, int reg) { struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); @@ -947,6 +967,7 @@ static void esdhc_set_timeout(struct sdhci_host *host, struct mmc_command *cmd) static struct sdhci_ops sdhci_esdhc_ops = { .read_l = esdhc_readl_le, .read_w = esdhc_readw_le, + .read_b = esdhc_readb_le, .write_l = esdhc_writel_le, .write_w = esdhc_writew_le, .write_b = esdhc_writeb_le, -- 2.7.4 From mboxrd@z Thu Jan 1 00:00:00 1970 From: Aaron Brice Subject: [PATCH] sdhci-esdhc-imx: Correct two register accesses Date: Thu, 6 Oct 2016 15:54:17 -0700 Message-ID: <1475794457-17993-1-git-send-email-aaron.brice@datasoft.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=m.gmane.org@lists.infradead.org To: david.russell@datasoft.com, adrian.hunter@intel.com, ulf.hansson@linaro.org, aisheng.dong@nxp.com Cc: linux-mmc@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org List-Id: linux-mmc@vger.kernel.org - The DMA error interrupt bit is in a different position as compared to the sdhci standard. This is accounted for in many cases, but not handled in the case of clearing the INT_STATUS register by writing a 1 to that location. - The HOST_CONTROL register is very different as compared to the sdhci standard. This is accounted for in the write case, but not when read back out (which it is in the sdhci code). Signed-off-by: Dave Russell Signed-off-by: Aaron Brice --- drivers/mmc/host/sdhci-esdhc-imx.c | 23 ++++++++++++++++++++++- 1 file changed, 22 insertions(+), 1 deletion(-) diff --git a/drivers/mmc/host/sdhci-esdhc-imx.c b/drivers/mmc/host/sdhci-esdhc-imx.c index 1f54fd8..d61ef16 100644 --- a/drivers/mmc/host/sdhci-esdhc-imx.c +++ b/drivers/mmc/host/sdhci-esdhc-imx.c @@ -346,7 +346,8 @@ static void esdhc_writel_le(struct sdhci_host *host, u32 val, int reg) struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host); u32 data; - if (unlikely(reg == SDHCI_INT_ENABLE || reg == SDHCI_SIGNAL_ENABLE)) { + if (unlikely(reg == SDHCI_INT_ENABLE || reg == SDHCI_SIGNAL_ENABLE || + reg == SDHCI_INT_STATUS)) { if ((val & SDHCI_INT_CARD_INT) && !esdhc_is_usdhc(imx_data)) { /* * Clear and then set D3CD bit to avoid missing the @@ -555,6 +556,25 @@ static void esdhc_writew_le(struct sdhci_host *host, u16 val, int reg) esdhc_clrset_le(host, 0xffff, val, reg); } +static u8 esdhc_readb_le(struct sdhci_host *host, int reg) +{ + u8 ret; + u32 long_val; + + switch (reg) { + case SDHCI_HOST_CONTROL: + long_val = readl(host->ioaddr + reg); + + ret = long_val & SDHCI_CTRL_LED; + ret |= (long_val >> 5) & SDHCI_CTRL_DMA_MASK; + ret |= (long_val & ESDHC_CTRL_4BITBUS); + ret |= (long_val & ESDHC_CTRL_8BITBUS) << 3; + return ret; + } + + return readb(host->ioaddr + reg); +} + static void esdhc_writeb_le(struct sdhci_host *host, u8 val, int reg) { struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); @@ -947,6 +967,7 @@ static void esdhc_set_timeout(struct sdhci_host *host, struct mmc_command *cmd) static struct sdhci_ops sdhci_esdhc_ops = { .read_l = esdhc_readl_le, .read_w = esdhc_readw_le, + .read_b = esdhc_readb_le, .write_l = esdhc_writel_le, .write_w = esdhc_writew_le, .write_b = esdhc_writeb_le, -- 2.7.4 From mboxrd@z Thu Jan 1 00:00:00 1970 From: aaron.brice@datasoft.com (Aaron Brice) Date: Thu, 6 Oct 2016 15:54:17 -0700 Subject: [PATCH] sdhci-esdhc-imx: Correct two register accesses Message-ID: <1475794457-17993-1-git-send-email-aaron.brice@datasoft.com> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org - The DMA error interrupt bit is in a different position as compared to the sdhci standard. This is accounted for in many cases, but not handled in the case of clearing the INT_STATUS register by writing a 1 to that location. - The HOST_CONTROL register is very different as compared to the sdhci standard. This is accounted for in the write case, but not when read back out (which it is in the sdhci code). Signed-off-by: Dave Russell Signed-off-by: Aaron Brice --- drivers/mmc/host/sdhci-esdhc-imx.c | 23 ++++++++++++++++++++++- 1 file changed, 22 insertions(+), 1 deletion(-) diff --git a/drivers/mmc/host/sdhci-esdhc-imx.c b/drivers/mmc/host/sdhci-esdhc-imx.c index 1f54fd8..d61ef16 100644 --- a/drivers/mmc/host/sdhci-esdhc-imx.c +++ b/drivers/mmc/host/sdhci-esdhc-imx.c @@ -346,7 +346,8 @@ static void esdhc_writel_le(struct sdhci_host *host, u32 val, int reg) struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host); u32 data; - if (unlikely(reg == SDHCI_INT_ENABLE || reg == SDHCI_SIGNAL_ENABLE)) { + if (unlikely(reg == SDHCI_INT_ENABLE || reg == SDHCI_SIGNAL_ENABLE || + reg == SDHCI_INT_STATUS)) { if ((val & SDHCI_INT_CARD_INT) && !esdhc_is_usdhc(imx_data)) { /* * Clear and then set D3CD bit to avoid missing the @@ -555,6 +556,25 @@ static void esdhc_writew_le(struct sdhci_host *host, u16 val, int reg) esdhc_clrset_le(host, 0xffff, val, reg); } +static u8 esdhc_readb_le(struct sdhci_host *host, int reg) +{ + u8 ret; + u32 long_val; + + switch (reg) { + case SDHCI_HOST_CONTROL: + long_val = readl(host->ioaddr + reg); + + ret = long_val & SDHCI_CTRL_LED; + ret |= (long_val >> 5) & SDHCI_CTRL_DMA_MASK; + ret |= (long_val & ESDHC_CTRL_4BITBUS); + ret |= (long_val & ESDHC_CTRL_8BITBUS) << 3; + return ret; + } + + return readb(host->ioaddr + reg); +} + static void esdhc_writeb_le(struct sdhci_host *host, u8 val, int reg) { struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); @@ -947,6 +967,7 @@ static void esdhc_set_timeout(struct sdhci_host *host, struct mmc_command *cmd) static struct sdhci_ops sdhci_esdhc_ops = { .read_l = esdhc_readl_le, .read_w = esdhc_readw_le, + .read_b = esdhc_readb_le, .write_l = esdhc_writel_le, .write_w = esdhc_writew_le, .write_b = esdhc_writeb_le, -- 2.7.4