* [U-Boot] [PATCH 1/9] dm: pci: return the real controller in pci_bus_to_hose()
@ 2016-10-10 8:47 Minghuan Lian
2016-10-10 8:47 ` [U-Boot] [PATCH 2/9] dm: pci: remove pci_bus_to_hose(0) calling Minghuan Lian
` (9 more replies)
0 siblings, 10 replies; 26+ messages in thread
From: Minghuan Lian @ 2016-10-10 8:47 UTC (permalink / raw)
To: u-boot
for the legacy PCI driver, the function pci_bus_to_hose() returns
the real PCIe controller. To keep consistency, this function is
changed to return the PCIe controller pointer of the root bus
instead of the current PCIe bus.
Signed-off-by: Minghuan Lian <Minghuan.Lian@nxp.com>
---
drivers/pci/pci_compat.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/pci/pci_compat.c b/drivers/pci/pci_compat.c
index ddaf358..25bc095 100644
--- a/drivers/pci/pci_compat.c
+++ b/drivers/pci/pci_compat.c
@@ -49,5 +49,5 @@ struct pci_controller *pci_bus_to_hose(int busnum)
return NULL;
}
- return dev_get_uclass_priv(bus);
+ return dev_get_uclass_priv(pci_get_controller(bus));
}
--
1.9.1
^ permalink raw reply related [flat|nested] 26+ messages in thread
* [U-Boot] [PATCH 2/9] dm: pci: remove pci_bus_to_hose(0) calling
2016-10-10 8:47 [U-Boot] [PATCH 1/9] dm: pci: return the real controller in pci_bus_to_hose() Minghuan Lian
@ 2016-10-10 8:47 ` Minghuan Lian
2016-10-10 11:54 ` Bin Meng
2016-10-10 8:47 ` [U-Boot] [PATCH 3/9] arm: ls1021a: add PCIe dts node Minghuan Lian
` (8 subsequent siblings)
9 siblings, 1 reply; 26+ messages in thread
From: Minghuan Lian @ 2016-10-10 8:47 UTC (permalink / raw)
To: u-boot
There may be multiple PCIe controllers in a SoC.
It is not correct that always calling pci_bus_to_hose(0) to get
the first PCIe controller for the PCIe device connected other
controllers. We just remove this calling because hose always point
the correct PCIe controller.
Signed-off-by: Minghuan Lian <Minghuan.Lian@nxp.com>
---
drivers/pci/pci_common.c | 10 ----------
1 file changed, 10 deletions(-)
diff --git a/drivers/pci/pci_common.c b/drivers/pci/pci_common.c
index 1755914..448e814 100644
--- a/drivers/pci/pci_common.c
+++ b/drivers/pci/pci_common.c
@@ -181,11 +181,6 @@ phys_addr_t pci_hose_bus_to_phys(struct pci_controller *hose,
return phys_addr;
}
-#ifdef CONFIG_DM_PCI
- /* The root controller has the region information */
- hose = pci_bus_to_hose(0);
-#endif
-
/*
* if PCI_REGION_MEM is set we do a two pass search with preference
* on matches that don't have PCI_REGION_SYS_MEMORY set
@@ -248,11 +243,6 @@ pci_addr_t pci_hose_phys_to_bus(struct pci_controller *hose,
return bus_addr;
}
-#ifdef CONFIG_DM_PCI
- /* The root controller has the region information */
- hose = pci_bus_to_hose(0);
-#endif
-
/*
* if PCI_REGION_MEM is set we do a two pass search with preference
* on matches that don't have PCI_REGION_SYS_MEMORY set
--
1.9.1
^ permalink raw reply related [flat|nested] 26+ messages in thread
* [U-Boot] [PATCH 3/9] arm: ls1021a: add PCIe dts node
2016-10-10 8:47 [U-Boot] [PATCH 1/9] dm: pci: return the real controller in pci_bus_to_hose() Minghuan Lian
2016-10-10 8:47 ` [U-Boot] [PATCH 2/9] dm: pci: remove pci_bus_to_hose(0) calling Minghuan Lian
@ 2016-10-10 8:47 ` Minghuan Lian
2016-10-10 8:47 ` [U-Boot] [PATCH 4/9] arm: ls1012a: " Minghuan Lian
` (7 subsequent siblings)
9 siblings, 0 replies; 26+ messages in thread
From: Minghuan Lian @ 2016-10-10 8:47 UTC (permalink / raw)
To: u-boot
Signed-off-by: Minghuan Lian <Minghuan.Lian@nxp.com>
---
arch/arm/dts/ls1021a.dtsi | 31 +++++++++++++++++++++++++++++++
1 file changed, 31 insertions(+)
diff --git a/arch/arm/dts/ls1021a.dtsi b/arch/arm/dts/ls1021a.dtsi
index 119b1af..e06cf60 100644
--- a/arch/arm/dts/ls1021a.dtsi
+++ b/arch/arm/dts/ls1021a.dtsi
@@ -373,5 +373,36 @@
interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
dr_mode = "host";
};
+
+ pcie at 3400000 {
+ compatible = "fsl,ls-pcie", "snps,dw-pcie";
+ reg = <0x03400000 0x20000 /* dbi registers */
+ 0x01570000 0x10000 /* pf controls registers */
+ 0x24000000 0x20000>; /* configuration space */
+ reg-names = "dbi", "ctrl", "config";
+ big-endian;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ bus-range = <0x0 0xff>;
+ ranges = <0x81000000 0x0 0x00000000 0x24020000 0x0 0x00010000 /* downstream I/O */
+ 0x82000000 0x0 0x28000000 0x28000000 0x0 0x08000000>; /* non-prefetchable memory */
+ };
+
+ pcie at 3500000 {
+ compatible = "fsl,ls-pcie", "snps,dw-pcie";
+ reg = <0x03500000 0x10000 /* dbi registers */
+ 0x01570000 0x10000 /* pf controls registers */
+ 0x34000000 0x20000>; /* configuration space */
+ reg-names = "dbi", "ctrl", "config";
+ big-endian;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ num-lanes = <2>;
+ bus-range = <0x0 0xff>;
+ ranges = <0x81000000 0x0 0x00000000 0x34020000 0x0 0x00010000 /* downstream I/O */
+ 0x82000000 0x0 0x38000000 0x38000000 0x0 0x08000000>; /* non-prefetchable memory */
+ };
};
};
--
1.9.1
^ permalink raw reply related [flat|nested] 26+ messages in thread
* [U-Boot] [PATCH 4/9] arm: ls1012a: add PCIe dts node
2016-10-10 8:47 [U-Boot] [PATCH 1/9] dm: pci: return the real controller in pci_bus_to_hose() Minghuan Lian
2016-10-10 8:47 ` [U-Boot] [PATCH 2/9] dm: pci: remove pci_bus_to_hose(0) calling Minghuan Lian
2016-10-10 8:47 ` [U-Boot] [PATCH 3/9] arm: ls1021a: add PCIe dts node Minghuan Lian
@ 2016-10-10 8:47 ` Minghuan Lian
2016-10-10 8:47 ` [U-Boot] [PATCH 5/9] armv8: ls1043a: " Minghuan Lian
` (6 subsequent siblings)
9 siblings, 0 replies; 26+ messages in thread
From: Minghuan Lian @ 2016-10-10 8:47 UTC (permalink / raw)
To: u-boot
Signed-off-by: Minghuan Lian <Minghuan.Lian@nxp.com>
---
arch/arm/dts/fsl-ls1012a.dtsi | 15 +++++++++++++++
1 file changed, 15 insertions(+)
diff --git a/arch/arm/dts/fsl-ls1012a.dtsi b/arch/arm/dts/fsl-ls1012a.dtsi
index 024527e..c4ca9c1 100644
--- a/arch/arm/dts/fsl-ls1012a.dtsi
+++ b/arch/arm/dts/fsl-ls1012a.dtsi
@@ -103,5 +103,20 @@
status = "disabled";
};
+ pcie at 3400000 {
+ compatible = "fsl,ls-pcie", "snps,dw-pcie";
+ reg = <0x00 0x03400000 0x0 0x80000 /* dbi registers */
+ 0x00 0x03480000 0x0 0x40000 /* lut registers */
+ 0x00 0x034c0000 0x0 0x40000 /* pf controls registers */
+ 0x40 0x00000000 0x0 0x20000>; /* configuration space */
+ reg-names = "dbi", "lut", "ctrl", "config";
+ big-endian;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ bus-range = <0x0 0xff>;
+ ranges = <0x81000000 0x0 0x00000000 0x40 0x00020000 0x0 0x00010000 /* downstream I/O */
+ 0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
+ };
};
};
--
1.9.1
^ permalink raw reply related [flat|nested] 26+ messages in thread
* [U-Boot] [PATCH 5/9] armv8: ls1043a: add PCIe dts node
2016-10-10 8:47 [U-Boot] [PATCH 1/9] dm: pci: return the real controller in pci_bus_to_hose() Minghuan Lian
` (2 preceding siblings ...)
2016-10-10 8:47 ` [U-Boot] [PATCH 4/9] arm: ls1012a: " Minghuan Lian
@ 2016-10-10 8:47 ` Minghuan Lian
2016-10-10 8:47 ` [U-Boot] [PATCH 6/9] armv8: ls1046a: " Minghuan Lian
` (5 subsequent siblings)
9 siblings, 0 replies; 26+ messages in thread
From: Minghuan Lian @ 2016-10-10 8:47 UTC (permalink / raw)
To: u-boot
Signed-off-by: Minghuan Lian <Minghuan.Lian@nxp.com>
---
arch/arm/dts/fsl-ls1043a.dtsi | 46 +++++++++++++++++++++++++++++++++++++++++++
1 file changed, 46 insertions(+)
diff --git a/arch/arm/dts/fsl-ls1043a.dtsi b/arch/arm/dts/fsl-ls1043a.dtsi
index a8bffba..a9894d0 100644
--- a/arch/arm/dts/fsl-ls1043a.dtsi
+++ b/arch/arm/dts/fsl-ls1043a.dtsi
@@ -215,5 +215,51 @@
big-endian;
status = "disabled";
};
+
+ pcie at 3400000 {
+ compatible = "fsl,ls-pcie", "snps,dw-pcie";
+ reg = <0x00 0x03400000 0x0 0x10000 /* dbi registers */
+ 0x00 0x03410000 0x0 0x10000 /* lut registers */
+ 0x40 0x00000000 0x0 0x20000>; /* configuration space */
+ reg-names = "dbi", "lut", "config";
+ big-endian;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ bus-range = <0x0 0xff>;
+ ranges = <0x81000000 0x0 0x00000000 0x40 0x00020000 0x0 0x00010000 /* downstream I/O */
+ 0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
+ };
+
+ pcie at 3500000 {
+ compatible = "fsl,ls-pcie", "snps,dw-pcie";
+ reg = <0x00 0x03500000 0x0 0x10000 /* dbi registers */
+ 0x00 0x03510000 0x0 0x10000 /* lut registers */
+ 0x48 0x00000000 0x0 0x20000>; /* configuration space */
+ reg-names = "dbi", "lut", "config";
+ big-endian;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ num-lanes = <2>;
+ bus-range = <0x0 0xff>;
+ ranges = <0x81000000 0x0 0x00000000 0x48 0x00020000 0x0 0x00010000 /* downstream I/O */
+ 0x82000000 0x0 0x40000000 0x48 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
+ };
+
+ pcie at 3600000 {
+ compatible = "fsl,ls-pcie", "snps,dw-pcie";
+ reg = <0x00 0x03600000 0x0 0x10000 /* dbi registers */
+ 0x00 0x03610000 0x0 0x10000 /* lut registers */
+ 0x50 0x00000000 0x0 0x20000>; /* configuration space */
+ reg-names = "dbi", "lut", "config";
+ big-endian;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ bus-range = <0x0 0xff>;
+ ranges = <0x81000000 0x0 0x00000000 0x50 0x00020000 0x0 0x00010000 /* downstream I/O */
+ 0x82000000 0x0 0x40000000 0x50 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
+ };
};
};
--
1.9.1
^ permalink raw reply related [flat|nested] 26+ messages in thread
* [U-Boot] [PATCH 6/9] armv8: ls1046a: add PCIe dts node
2016-10-10 8:47 [U-Boot] [PATCH 1/9] dm: pci: return the real controller in pci_bus_to_hose() Minghuan Lian
` (3 preceding siblings ...)
2016-10-10 8:47 ` [U-Boot] [PATCH 5/9] armv8: ls1043a: " Minghuan Lian
@ 2016-10-10 8:47 ` Minghuan Lian
2016-10-10 8:47 ` [U-Boot] [PATCH 7/9] armv8: ls2080a: " Minghuan Lian
` (4 subsequent siblings)
9 siblings, 0 replies; 26+ messages in thread
From: Minghuan Lian @ 2016-10-10 8:47 UTC (permalink / raw)
To: u-boot
Signed-off-by: Minghuan Lian <Minghuan.Lian@nxp.com>
---
arch/arm/dts/fsl-ls1046a.dtsi | 49 +++++++++++++++++++++++++++++++++++++++++++
1 file changed, 49 insertions(+)
diff --git a/arch/arm/dts/fsl-ls1046a.dtsi b/arch/arm/dts/fsl-ls1046a.dtsi
index 87dd997..5d30112 100644
--- a/arch/arm/dts/fsl-ls1046a.dtsi
+++ b/arch/arm/dts/fsl-ls1046a.dtsi
@@ -162,5 +162,54 @@
big-endian;
status = "disabled";
};
+
+ pcie at 3400000 {
+ compatible = "fsl,ls-pcie", "snps,dw-pcie";
+ reg = <0x00 0x03400000 0x0 0x80000 /* dbi registers */
+ 0x00 0x03480000 0x0 0x40000 /* lut registers */
+ 0x00 0x034c0000 0x0 0x40000 /* pf controls registers */
+ 0x40 0x00000000 0x0 0x20000>; /* configuration space */
+ reg-names = "dbi", "lut", "ctrl", "config";
+ big-endian;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ bus-range = <0x0 0xff>;
+ ranges = <0x81000000 0x0 0x00000000 0x40 0x00020000 0x0 0x00010000 /* downstream I/O */
+ 0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
+ };
+
+ pcie at 3500000 {
+ compatible = "fsl,ls-pcie", "snps,dw-pcie";
+ reg = <0x00 0x03500000 0x0 0x80000 /* dbi registers */
+ 0x00 0x03580000 0x0 0x40000 /* lut registers */
+ 0x00 0x035c0000 0x0 0x40000 /* pf controls registers */
+ 0x48 0x00000000 0x0 0x20000>; /* configuration space */
+ reg-names = "dbi", "lut", "ctrl", "config";
+ big-endian;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ num-lanes = <2>;
+ bus-range = <0x0 0xff>;
+ ranges = <0x81000000 0x0 0x00000000 0x48 0x00020000 0x0 0x00010000 /* downstream I/O */
+ 0x82000000 0x0 0x40000000 0x48 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
+ };
+
+ pcie at 3600000 {
+ compatible = "fsl,ls-pcie", "snps,dw-pcie";
+ reg = <0x00 0x03600000 0x0 0x80000 /* dbi registers */
+ 0x00 0x03680000 0x0 0x40000 /* lut registers */
+ 0x00 0x036c0000 0x0 0x40000 /* pf controls registers */
+ 0x50 0x00000000 0x0 0x20000>; /* configuration space */
+ reg-names = "dbi", "lut", "ctrl", "config";
+ big-endian;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ bus-range = <0x0 0xff>;
+ ranges = <0x81000000 0x0 0x00000000 0x50 0x00020000 0x0 0x00010000 /* downstream I/O */
+ 0x82000000 0x0 0x40000000 0x50 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
+ };
};
};
--
1.9.1
^ permalink raw reply related [flat|nested] 26+ messages in thread
* [U-Boot] [PATCH 7/9] armv8: ls2080a: add PCIe dts node
2016-10-10 8:47 [U-Boot] [PATCH 1/9] dm: pci: return the real controller in pci_bus_to_hose() Minghuan Lian
` (4 preceding siblings ...)
2016-10-10 8:47 ` [U-Boot] [PATCH 6/9] armv8: ls1046a: " Minghuan Lian
@ 2016-10-10 8:47 ` Minghuan Lian
2016-10-10 8:47 ` [U-Boot] [PATCH 8/9] pci: layerscape: rewrite pci driver based on DM Minghuan Lian
` (3 subsequent siblings)
9 siblings, 0 replies; 26+ messages in thread
From: Minghuan Lian @ 2016-10-10 8:47 UTC (permalink / raw)
To: u-boot
Signed-off-by: Minghuan Lian <Minghuan.Lian@nxp.com>
---
arch/arm/dts/fsl-ls2080a.dtsi | 60 +++++++++++++++++++++++++++++++++++++++++++
1 file changed, 60 insertions(+)
diff --git a/arch/arm/dts/fsl-ls2080a.dtsi b/arch/arm/dts/fsl-ls2080a.dtsi
index b308c8b..4ed066f 100644
--- a/arch/arm/dts/fsl-ls2080a.dtsi
+++ b/arch/arm/dts/fsl-ls2080a.dtsi
@@ -75,4 +75,64 @@
reg-names = "QuadSPI", "QuadSPI-memory";
num-cs = <4>;
};
+
+ pcie at 3400000 {
+ compatible = "fsl,ls-pcie", "snps,dw-pcie";
+ reg = <0x00 0x03400000 0x0 0x80000 /* dbi registers */
+ 0x00 0x03480000 0x0 0x80000 /* lut registers */
+ 0x10 0x00000000 0x0 0x20000>; /* configuration space */
+ reg-names = "dbi", "lut", "config";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ num-lanes = <4>;
+ bus-range = <0x0 0xff>;
+ ranges = <0x81000000 0x0 0x00000000 0x10 0x00020000 0x0 0x00010000 /* downstream I/O */
+ 0x82000000 0x0 0x40000000 0x10 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
+ };
+
+ pcie at 3500000 {
+ compatible = "fsl,ls-pcie", "snps,dw-pcie";
+ reg = <0x00 0x03500000 0x0 0x80000 /* dbi registers */
+ 0x00 0x03580000 0x0 0x80000 /* lut registers */
+ 0x12 0x00000000 0x0 0x20000>; /* configuration space */
+ reg-names = "dbi", "lut", "config";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ num-lanes = <4>;
+ bus-range = <0x0 0xff>;
+ ranges = <0x81000000 0x0 0x00000000 0x12 0x00020000 0x0 0x00010000 /* downstream I/O */
+ 0x82000000 0x0 0x40000000 0x12 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
+ };
+
+ pcie at 3600000 {
+ compatible = "fsl,ls-pcie", "snps,dw-pcie";
+ reg = <0x00 0x03600000 0x0 0x80000 /* dbi registers */
+ 0x00 0x03680000 0x0 0x80000 /* lut registers */
+ 0x14 0x00000000 0x0 0x20000>; /* configuration space */
+ reg-names = "dbi", "lut", "config";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ num-lanes = <8>;
+ bus-range = <0x0 0xff>;
+ ranges = <0x81000000 0x0 0x00000000 0x14 0x00020000 0x0 0x00010000 /* downstream I/O */
+ 0x82000000 0x0 0x40000000 0x14 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
+ };
+
+ pcie at 3700000 {
+ compatible = "fsl,ls-pcie", "snps,dw-pcie";
+ reg = <0x00 0x03700000 0x0 0x80000 /* dbi registers */
+ 0x00 0x03780000 0x0 0x80000 /* lut registers */
+ 0x16 0x00000000 0x0 0x20000>; /* configuration space */
+ reg-names = "dbi", "lut", "config";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ num-lanes = <4>;
+ bus-range = <0x0 0xff>;
+ ranges = <0x81000000 0x0 0x00000000 0x16 0x00020000 0x0 0x00010000 /* downstream I/O */
+ 0x82000000 0x0 0x40000000 0x16 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
+ };
};
--
1.9.1
^ permalink raw reply related [flat|nested] 26+ messages in thread
* [U-Boot] [PATCH 8/9] pci: layerscape: rewrite pci driver based on DM
2016-10-10 8:47 [U-Boot] [PATCH 1/9] dm: pci: return the real controller in pci_bus_to_hose() Minghuan Lian
` (5 preceding siblings ...)
2016-10-10 8:47 ` [U-Boot] [PATCH 7/9] armv8: ls2080a: " Minghuan Lian
@ 2016-10-10 8:47 ` Minghuan Lian
2016-10-10 11:49 ` Bin Meng
2016-10-10 8:47 ` [U-Boot] [PATCH 9/9] armv8: ls1046a: Enable PCIe support Minghuan Lian
` (2 subsequent siblings)
9 siblings, 1 reply; 26+ messages in thread
From: Minghuan Lian @ 2016-10-10 8:47 UTC (permalink / raw)
To: u-boot
There are more than five kinds of Layerscape SoCs. unfortunately,
PCIe controller of each SoC is a little bit different. In order
to avoid too many macro definitions, the patch re-implement PCIe
driver based on DM. PCIe dts node is to describe the difference.
Signed-off-by: Minghuan Lian <Minghuan.Lian@nxp.com>
---
.../include/asm/arch-fsl-layerscape/immap_lsch3.h | 8 -
drivers/pci/Kconfig | 8 +
drivers/pci/pcie_layerscape.c | 958 +++++++++++----------
include/configs/ls1012a_common.h | 12 +
include/configs/ls1012aqds.h | 24 -
include/configs/ls1012ardb.h | 24 -
include/configs/ls1021aqds.h | 18 +-
include/configs/ls1021atwr.h | 18 +-
include/configs/ls1043a_common.h | 23 +-
include/configs/ls2080a_common.h | 27 +-
include/configs/ls2080aqds.h | 8 -
include/configs/ls2080ardb.h | 8 -
12 files changed, 526 insertions(+), 610 deletions(-)
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
index 7acba27..bd07808 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
@@ -104,14 +104,6 @@
#define CONFIG_SYS_PCIE2_PHYS_ADDR 0x1200000000ULL
#define CONFIG_SYS_PCIE3_PHYS_ADDR 0x1400000000ULL
#define CONFIG_SYS_PCIE4_PHYS_ADDR 0x1600000000ULL
-/* LUT registers */
-#define PCIE_LUT_BASE 0x80000
-#define PCIE_LUT_LCTRL0 0x7F8
-#define PCIE_LUT_DBG 0x7FC
-#define PCIE_LUT_UDR(n) (0x800 + (n) * 8)
-#define PCIE_LUT_LDR(n) (0x804 + (n) * 8)
-#define PCIE_LUT_ENABLE (1 << 31)
-#define PCIE_LUT_ENTRY_COUNT 32
/* Device Configuration */
#define DCFG_BASE 0x01e00000
diff --git a/drivers/pci/Kconfig b/drivers/pci/Kconfig
index 9a7c187..3752d5f 100644
--- a/drivers/pci/Kconfig
+++ b/drivers/pci/Kconfig
@@ -46,4 +46,12 @@ config PCI_XILINX
Enable support for the Xilinx AXI bridge for PCI express, an IP block
which can be used on some generations of Xilinx FPGAs.
+config PCI_LAYERSCAPE
+ bool "Layerscape PCI support"
+ depends on (FSL_LAYERSCAPE || CONFIG_LS102XA) && DM_PCI
+ help
+ Support Layerscape PCI. The Layerscape SoC may have one or several
+ PCIe controllers. The PCIe may works in RC or EP mode according to
+ RCW setting.
+
endmenu
diff --git a/drivers/pci/pcie_layerscape.c b/drivers/pci/pcie_layerscape.c
index 2e6b986..3bdcbff 100644
--- a/drivers/pci/pcie_layerscape.c
+++ b/drivers/pci/pcie_layerscape.c
@@ -10,12 +10,14 @@
#include <pci.h>
#include <asm/io.h>
#include <errno.h>
-#include <malloc.h>
+#include <dm.h>
#ifndef CONFIG_LS102XA
#include <asm/arch/fdt.h>
#include <asm/arch/soc.h>
#endif
+DECLARE_GLOBAL_DATA_PTR;
+
#ifndef CONFIG_SYS_PCI_MEMORY_BUS
#define CONFIG_SYS_PCI_MEMORY_BUS CONFIG_SYS_SDRAM_BASE
#endif
@@ -32,14 +34,23 @@
#define CONFIG_SYS_PCI_EP_MEMORY_BASE CONFIG_SYS_LOAD_ADDR
#endif
+#ifdef CONFIG_LS102XA
+/* LS1021a PCIE space */
+#define LS1021_PCIE_SPACE_OFFSET 0x4000000000ULL
+#define LS1021_PCIE_SPACE_SIZE 0x0800000000ULL
+
+/* LS1021a PEX1/2 Misc Ports Status Register */
+#define LS1021_PEXMSCPORTSR(pex_idx) (0x94 + (pex_idx) * 4)
+#define LS1021_LTSSM_STATE_SHIFT 20
+#endif
+
/* iATU registers */
#define PCIE_ATU_VIEWPORT 0x900
#define PCIE_ATU_REGION_INBOUND (0x1 << 31)
#define PCIE_ATU_REGION_OUTBOUND (0x0 << 31)
#define PCIE_ATU_REGION_INDEX0 (0x0 << 0)
#define PCIE_ATU_REGION_INDEX1 (0x1 << 0)
-#define PCIE_ATU_REGION_INDEX2 (0x2 << 0)
-#define PCIE_ATU_REGION_INDEX3 (0x3 << 0)
+#define PCIE_ATU_REGION_NUM 6
#define PCIE_ATU_CR1 0x904
#define PCIE_ATU_TYPE_MEM (0x0 << 0)
#define PCIE_ATU_TYPE_IO (0x2 << 0)
@@ -58,6 +69,8 @@
#define PCIE_ATU_FUNC(x) (((x) & 0x7) << 16)
#define PCIE_ATU_UPPER_TARGET 0x91C
+#define PCIE_SRIOV 0x178
+#define PCIE_STRFMR1 0x71c /* Symbol Timer & Filter Mask Register1 */
#define PCIE_DBI_RO_WR_EN 0x8bc
#define PCIE_LINK_CAP 0x7c
@@ -67,7 +80,15 @@
#define LTSSM_STATE_MASK 0x3f
#define LTSSM_PCIE_L0 0x11 /* L0 state */
-#define PCIE_DBI_SIZE 0x100000 /* 1M */
+/* LUT registers */
+#define PCIE_LUT_UDR(n) (0x800 + (n) * 8)
+#define PCIE_LUT_LDR(n) (0x804 + (n) * 8)
+#define PCIE_LUT_ENABLE (1 << 31)
+#define PCIE_LUT_ENTRY_COUNT 32
+
+/* PF Controll registers */
+#define PCIE_PF_VF_CTRL 0x7F8
+#define PCIE_PF_DBG 0x7FC
#define PCIE_LCTRL0_CFG2_ENABLE (1 << 31)
#define PCIE_LCTRL0_VF(vf) ((vf) << 22)
@@ -88,329 +109,388 @@
#define PCIE_BAR2_SIZE (4 * 1024) /* 4K */
#define PCIE_BAR4_SIZE (1 * 1024 * 1024) /* 1M */
+#define PCIE_SRDS_PRTCL(idx) (PCIE1 + (idx))
+#define PCIE_SYS_BASE_ADDR 0x3400000
+#define PCIE_CCSR_SIZE 0x0100000
+
+/* CS2 */
+#define PCIE_CS2_OFFSET 0x1000 /* For PCIe without SR-IOV */
+
struct ls_pcie {
int idx;
+ struct list_head list;
+ struct udevice *bus;
+ struct fdt_resource dbi_res;
+ struct fdt_resource lut_res;
+ struct fdt_resource ctrl_res;
+ struct fdt_resource cfg_res;
void __iomem *dbi;
- void __iomem *va_cfg0;
- void __iomem *va_cfg1;
+ void __iomem *lut;
+ void __iomem *ctrl;
+ void __iomem *cfg0;
+ void __iomem *cfg1;
+ bool big_endian;
+ bool enabled;
int next_lut_index;
struct pci_controller hose;
};
-struct ls_pcie_info {
- unsigned long regs;
- int pci_num;
- u64 phys_base;
- u64 cfg0_phys;
- u64 cfg0_size;
- u64 cfg1_phys;
- u64 cfg1_size;
- u64 mem_bus;
- u64 mem_phys;
- u64 mem_size;
- u64 io_bus;
- u64 io_phys;
- u64 io_size;
-};
+static LIST_HEAD(ls_pcie_list);
-#define SET_LS_PCIE_INFO(x, num) \
-{ \
- x.regs = CONFIG_SYS_PCIE##num##_ADDR; \
- x.phys_base = CONFIG_SYS_PCIE##num##_PHYS_ADDR; \
- x.cfg0_phys = CONFIG_SYS_PCIE_CFG0_PHYS_OFF + \
- CONFIG_SYS_PCIE##num##_PHYS_ADDR; \
- x.cfg0_size = CONFIG_SYS_PCIE_CFG0_SIZE; \
- x.cfg1_phys = CONFIG_SYS_PCIE_CFG1_PHYS_OFF + \
- CONFIG_SYS_PCIE##num##_PHYS_ADDR; \
- x.cfg1_size = CONFIG_SYS_PCIE_CFG1_SIZE; \
- x.mem_bus = CONFIG_SYS_PCIE_MEM_BUS; \
- x.mem_phys = CONFIG_SYS_PCIE_MEM_PHYS_OFF + \
- CONFIG_SYS_PCIE##num##_PHYS_ADDR; \
- x.mem_size = CONFIG_SYS_PCIE_MEM_SIZE; \
- x.io_bus = CONFIG_SYS_PCIE_IO_BUS; \
- x.io_phys = CONFIG_SYS_PCIE_IO_PHYS_OFF + \
- CONFIG_SYS_PCIE##num##_PHYS_ADDR; \
- x.io_size = CONFIG_SYS_PCIE_IO_SIZE; \
- x.pci_num = num; \
+static unsigned int dbi_readl(struct ls_pcie *pcie, unsigned int offset)
+{
+ return in_le32(pcie->dbi + offset);
}
-#ifdef CONFIG_LS102XA
-#include <asm/arch/immap_ls102xa.h>
-
-/* PEX1/2 Misc Ports Status Register */
-#define LTSSM_STATE_SHIFT 20
+static void dbi_writel(struct ls_pcie *pcie, unsigned int value,
+ unsigned int offset)
+{
+ out_le32(pcie->dbi + offset, value);
+}
-static int ls_pcie_link_state(struct ls_pcie *pcie)
+#ifdef CONFIG_FSL_LSCH3
+static void lut_writel(struct ls_pcie *pcie, unsigned int value,
+ unsigned int offset)
{
- u32 state;
- struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
+ if (pcie->big_endian)
+ out_be32(pcie->lut + offset, value);
+ else
+ out_le32(pcie->lut + offset, value);
+}
+#endif
- state = in_be32(&scfg->pexmscportsr[pcie->idx]);
- state = (state >> LTSSM_STATE_SHIFT) & LTSSM_STATE_MASK;
- if (state < LTSSM_PCIE_L0) {
- debug("....PCIe link error. LTSSM=0x%02x.\n", state);
- return 0;
- }
+static unsigned int ctrl_readl(struct ls_pcie *pcie, unsigned int offset)
+{
+ if (pcie->big_endian)
+ return in_be32(pcie->ctrl + offset);
+ else
+ return in_le32(pcie->ctrl + offset);
+}
- return 1;
+static void ctrl_writel(struct ls_pcie *pcie, unsigned int value,
+ unsigned int offset)
+{
+ if (pcie->big_endian)
+ out_be32(pcie->ctrl + offset, value);
+ else
+ out_le32(pcie->ctrl + offset, value);
}
-#else
-static int ls_pcie_link_state(struct ls_pcie *pcie)
+
+#ifdef CONFIG_LS102XA
+static int ls_pcie_ltssm(struct ls_pcie *pcie)
{
u32 state;
- state = pex_lut_in32(pcie->dbi + PCIE_LUT_BASE + PCIE_LUT_DBG) &
- LTSSM_STATE_MASK;
- if (state < LTSSM_PCIE_L0) {
- debug("....PCIe link error. LTSSM=0x%02x.\n", state);
- return 0;
- }
+ state = ctrl_readl(pcie, LS1021_PEXMSCPORTSR(pcie->idx));
+ state = (state >> LS1021_LTSSM_STATE_SHIFT) & LTSSM_STATE_MASK;
- return 1;
+ return state;
+}
+#else
+static int ls_pcie_ltssm(struct ls_pcie *pcie)
+{
+ return ctrl_readl(pcie, PCIE_PF_DBG) & LTSSM_STATE_MASK;
}
#endif
static int ls_pcie_link_up(struct ls_pcie *pcie)
{
- int state;
- u32 cap;
-
- state = ls_pcie_link_state(pcie);
- if (state)
- return state;
+ int ltssm;
- /* Try to download speed to gen1 */
- cap = readl(pcie->dbi + PCIE_LINK_CAP);
- writel((cap & (~PCIE_LINK_SPEED_MASK)) | 1, pcie->dbi + PCIE_LINK_CAP);
- /*
- * Notice: the following delay has critical impact on link training
- * if too short (<30ms) the link doesn't get up.
- */
- mdelay(100);
- state = ls_pcie_link_state(pcie);
- if (state)
- return state;
-
- writel(cap, pcie->dbi + PCIE_LINK_CAP);
+ ltssm = ls_pcie_ltssm(pcie);
+ if (ltssm < LTSSM_PCIE_L0)
+ return 0;
- return 0;
+ return 1;
}
static void ls_pcie_cfg0_set_busdev(struct ls_pcie *pcie, u32 busdev)
{
- writel(PCIE_ATU_REGION_OUTBOUND | PCIE_ATU_REGION_INDEX0,
- pcie->dbi + PCIE_ATU_VIEWPORT);
- writel(busdev, pcie->dbi + PCIE_ATU_LOWER_TARGET);
+ dbi_writel(pcie, PCIE_ATU_REGION_OUTBOUND | PCIE_ATU_REGION_INDEX0,
+ PCIE_ATU_VIEWPORT);
+ dbi_writel(pcie, busdev, PCIE_ATU_LOWER_TARGET);
}
static void ls_pcie_cfg1_set_busdev(struct ls_pcie *pcie, u32 busdev)
{
- writel(PCIE_ATU_REGION_OUTBOUND | PCIE_ATU_REGION_INDEX1,
- pcie->dbi + PCIE_ATU_VIEWPORT);
- writel(busdev, pcie->dbi + PCIE_ATU_LOWER_TARGET);
+ dbi_writel(pcie, PCIE_ATU_REGION_OUTBOUND | PCIE_ATU_REGION_INDEX1,
+ PCIE_ATU_VIEWPORT);
+ dbi_writel(pcie, busdev, PCIE_ATU_LOWER_TARGET);
}
-static void ls_pcie_iatu_outbound_set(struct ls_pcie *pcie, int idx, int type,
+static void ls_pcie_atu_outbound_set(struct ls_pcie *pcie, int idx, int type,
u64 phys, u64 bus_addr, pci_size_t size)
{
- writel(PCIE_ATU_REGION_OUTBOUND | idx, pcie->dbi + PCIE_ATU_VIEWPORT);
- writel((u32)phys, pcie->dbi + PCIE_ATU_LOWER_BASE);
- writel(phys >> 32, pcie->dbi + PCIE_ATU_UPPER_BASE);
- writel(phys + size - 1, pcie->dbi + PCIE_ATU_LIMIT);
- writel((u32)bus_addr, pcie->dbi + PCIE_ATU_LOWER_TARGET);
- writel(bus_addr >> 32, pcie->dbi + PCIE_ATU_UPPER_TARGET);
- writel(type, pcie->dbi + PCIE_ATU_CR1);
- writel(PCIE_ATU_ENABLE, pcie->dbi + PCIE_ATU_CR2);
+ dbi_writel(pcie, PCIE_ATU_REGION_OUTBOUND | idx, PCIE_ATU_VIEWPORT);
+ dbi_writel(pcie, (u32)phys, PCIE_ATU_LOWER_BASE);
+ dbi_writel(pcie, phys >> 32, PCIE_ATU_UPPER_BASE);
+ dbi_writel(pcie, (u32)phys + size - 1, PCIE_ATU_LIMIT);
+ dbi_writel(pcie, (u32)bus_addr, PCIE_ATU_LOWER_TARGET);
+ dbi_writel(pcie, bus_addr >> 32, PCIE_ATU_UPPER_TARGET);
+ dbi_writel(pcie, type, PCIE_ATU_CR1);
+ dbi_writel(pcie, PCIE_ATU_ENABLE, PCIE_ATU_CR2);
}
/* Use bar match mode and MEM type as default */
-static void ls_pcie_iatu_inbound_set(struct ls_pcie *pcie, int idx,
+static void ls_pcie_atu_inbound_set(struct ls_pcie *pcie, int idx,
int bar, u64 phys)
{
- writel(PCIE_ATU_REGION_INBOUND | idx, pcie->dbi + PCIE_ATU_VIEWPORT);
- writel((u32)phys, pcie->dbi + PCIE_ATU_LOWER_TARGET);
- writel(phys >> 32, pcie->dbi + PCIE_ATU_UPPER_TARGET);
- writel(PCIE_ATU_TYPE_MEM, pcie->dbi + PCIE_ATU_CR1);
- writel(PCIE_ATU_ENABLE | PCIE_ATU_BAR_MODE_ENABLE |
- PCIE_ATU_BAR_NUM(bar), pcie->dbi + PCIE_ATU_CR2);
+ dbi_writel(pcie, PCIE_ATU_REGION_INBOUND | idx, PCIE_ATU_VIEWPORT);
+ dbi_writel(pcie, (u32)phys, PCIE_ATU_LOWER_TARGET);
+ dbi_writel(pcie, phys >> 32, PCIE_ATU_UPPER_TARGET);
+ dbi_writel(pcie, PCIE_ATU_TYPE_MEM, PCIE_ATU_CR1);
+ dbi_writel(pcie, PCIE_ATU_ENABLE | PCIE_ATU_BAR_MODE_ENABLE |
+ PCIE_ATU_BAR_NUM(bar), PCIE_ATU_CR2);
}
-static void ls_pcie_setup_atu(struct ls_pcie *pcie, struct ls_pcie_info *info)
+static void ls_pcie_dump_atu(struct ls_pcie *pcie)
{
-#ifdef DEBUG
int i;
-#endif
- /* ATU 0 : OUTBOUND : CFG0 */
- ls_pcie_iatu_outbound_set(pcie, PCIE_ATU_REGION_INDEX0,
- PCIE_ATU_TYPE_CFG0,
- info->cfg0_phys,
- 0,
- info->cfg0_size);
- /* ATU 1 : OUTBOUND : CFG1 */
- ls_pcie_iatu_outbound_set(pcie, PCIE_ATU_REGION_INDEX1,
- PCIE_ATU_TYPE_CFG1,
- info->cfg1_phys,
- 0,
- info->cfg1_size);
- /* ATU 2 : OUTBOUND : MEM */
- ls_pcie_iatu_outbound_set(pcie, PCIE_ATU_REGION_INDEX2,
- PCIE_ATU_TYPE_MEM,
- info->mem_phys,
- info->mem_bus,
- info->mem_size);
- /* ATU 3 : OUTBOUND : IO */
- ls_pcie_iatu_outbound_set(pcie, PCIE_ATU_REGION_INDEX3,
- PCIE_ATU_TYPE_IO,
- info->io_phys,
- info->io_bus,
- info->io_size);
-
-#ifdef DEBUG
- for (i = 0; i <= PCIE_ATU_REGION_INDEX3; i++) {
- writel(PCIE_ATU_REGION_OUTBOUND | i,
- pcie->dbi + PCIE_ATU_VIEWPORT);
+ for (i = 0; i < PCIE_ATU_REGION_NUM; i++) {
+ dbi_writel(pcie, PCIE_ATU_REGION_OUTBOUND | i,
+ PCIE_ATU_VIEWPORT);
debug("iATU%d:\n", i);
debug("\tLOWER PHYS 0x%08x\n",
- readl(pcie->dbi + PCIE_ATU_LOWER_BASE));
+ dbi_readl(pcie, PCIE_ATU_LOWER_BASE));
debug("\tUPPER PHYS 0x%08x\n",
- readl(pcie->dbi + PCIE_ATU_UPPER_BASE));
+ dbi_readl(pcie, PCIE_ATU_UPPER_BASE));
debug("\tLOWER BUS 0x%08x\n",
- readl(pcie->dbi + PCIE_ATU_LOWER_TARGET));
+ dbi_readl(pcie, PCIE_ATU_LOWER_TARGET));
debug("\tUPPER BUS 0x%08x\n",
- readl(pcie->dbi + PCIE_ATU_UPPER_TARGET));
+ dbi_readl(pcie, PCIE_ATU_UPPER_TARGET));
debug("\tLIMIT 0x%08x\n",
readl(pcie->dbi + PCIE_ATU_LIMIT));
debug("\tCR1 0x%08x\n",
- readl(pcie->dbi + PCIE_ATU_CR1));
+ dbi_readl(pcie, PCIE_ATU_CR1));
debug("\tCR2 0x%08x\n",
- readl(pcie->dbi + PCIE_ATU_CR2));
+ dbi_readl(pcie, PCIE_ATU_CR2));
}
-#endif
}
-int pci_skip_dev(struct pci_controller *hose, pci_dev_t dev)
+static void ls_pcie_setup_atu(struct ls_pcie *pcie)
{
- /* Do not skip controller */
- return 0;
+ struct pci_region *io, *mem, *pref;
+ unsigned long long offset = 0;
+ int idx = 0;
+
+#ifdef CONFIG_LS102XA
+ offset = LS1021_PCIE_SPACE_OFFSET + LS1021_PCIE_SPACE_SIZE * pcie->idx;
+#endif
+
+ /* ATU 0 : OUTBOUND : CFG0 */
+ ls_pcie_atu_outbound_set(pcie, PCIE_ATU_REGION_INDEX0,
+ PCIE_ATU_TYPE_CFG0,
+ pcie->cfg_res.start + offset,
+ 0,
+ fdt_resource_size(&pcie->cfg_res) / 2);
+ /* ATU 1 : OUTBOUND : CFG1 */
+ ls_pcie_atu_outbound_set(pcie, PCIE_ATU_REGION_INDEX1,
+ PCIE_ATU_TYPE_CFG1,
+ pcie->cfg_res.start + offset +
+ fdt_resource_size(&pcie->cfg_res) / 2,
+ 0,
+ fdt_resource_size(&pcie->cfg_res) / 2);
+
+ pci_get_regions(pcie->bus, &io, &mem, &pref);
+ idx = PCIE_ATU_REGION_INDEX1 + 1;
+
+ if (io)
+ /* ATU : OUTBOUND : IO */
+ ls_pcie_atu_outbound_set(pcie, idx++,
+ PCIE_ATU_TYPE_IO,
+ io->phys_start + offset,
+ io->bus_start,
+ io->size);
+
+ if (mem)
+ /* ATU : OUTBOUND : MEM */
+ ls_pcie_atu_outbound_set(pcie, idx++,
+ PCIE_ATU_TYPE_MEM,
+ mem->phys_start + offset,
+ mem->bus_start,
+ mem->size);
+
+ if (pref)
+ /* ATU : OUTBOUND : pref */
+ ls_pcie_atu_outbound_set(pcie, idx++,
+ PCIE_ATU_TYPE_MEM,
+ pref->phys_start + offset,
+ pref->bus_start,
+ pref->size);
+
+ ls_pcie_dump_atu(pcie);
}
-static int ls_pcie_addr_valid(struct pci_controller *hose, pci_dev_t d)
+static int ls_pcie_addr_valid(struct ls_pcie *pcie, pci_dev_t bdf)
{
- if (PCI_DEV(d) > 0)
+ struct udevice *bus = pcie->bus;
+
+ if (!pcie->enabled)
+ return -ENODEV;
+
+ if (PCI_BUS(bdf) < bus->seq)
+ return -EINVAL;
+
+ if ((PCI_BUS(bdf) > bus->seq) && (!ls_pcie_link_up(pcie)))
return -EINVAL;
- /* Controller does not support multi-function in RC mode */
- if ((PCI_BUS(d) == hose->first_busno) && (PCI_FUNC(d) > 0))
+ if (PCI_BUS(bdf) <= (bus->seq + 1) && (PCI_DEV(bdf) > 0))
return -EINVAL;
return 0;
}
-static int ls_pcie_read_config(struct pci_controller *hose, pci_dev_t d,
- int where, u32 *val)
+void *ls_pcie_conf_address(struct ls_pcie *pcie, pci_dev_t bdf,
+ int offset)
{
- struct ls_pcie *pcie = hose->priv_data;
- u32 busdev, *addr;
+ struct udevice *bus = pcie->bus;
+ u32 busdev;
- if (ls_pcie_addr_valid(hose, d)) {
- *val = 0xffffffff;
- return 0;
- }
+ if (PCI_BUS(bdf) == bus->seq)
+ return pcie->dbi + offset;
+
+ busdev = PCIE_ATU_BUS(PCI_BUS(bdf)) |
+ PCIE_ATU_DEV(PCI_DEV(bdf)) |
+ PCIE_ATU_FUNC(PCI_FUNC(bdf));
- if (PCI_BUS(d) == hose->first_busno) {
- addr = pcie->dbi + (where & ~0x3);
+ if (PCI_BUS(bdf) == bus->seq + 1) {
+ ls_pcie_cfg0_set_busdev(pcie, busdev);
+ return pcie->cfg0 + offset;
} else {
- busdev = PCIE_ATU_BUS(PCI_BUS(d)) |
- PCIE_ATU_DEV(PCI_DEV(d)) |
- PCIE_ATU_FUNC(PCI_FUNC(d));
-
- if (PCI_BUS(d) == hose->first_busno + 1) {
- ls_pcie_cfg0_set_busdev(pcie, busdev);
- addr = pcie->va_cfg0 + (where & ~0x3);
- } else {
- ls_pcie_cfg1_set_busdev(pcie, busdev);
- addr = pcie->va_cfg1 + (where & ~0x3);
- }
+ ls_pcie_cfg1_set_busdev(pcie, busdev);
+ return pcie->cfg1 + offset;
}
+}
- *val = readl(addr);
+static int ls_pcie_read_config(struct udevice *bus, pci_dev_t bdf,
+ uint offset, ulong *valuep,
+ enum pci_size_t size)
+{
+ struct ls_pcie *pcie = dev_get_priv(bus);
+ void *address;
- return 0;
+ if (ls_pcie_addr_valid(pcie, bdf)) {
+ *valuep = pci_get_ff(size);
+ return 0;
+ }
+
+ address = ls_pcie_conf_address(pcie, bdf, offset);
+
+ switch (size) {
+ case PCI_SIZE_8:
+ *valuep = readb(address);
+ return 0;
+ case PCI_SIZE_16:
+ *valuep = readw(address);
+ return 0;
+ case PCI_SIZE_32:
+ *valuep = readl(address);
+ return 0;
+ default:
+ return -EINVAL;
+ }
}
-static int ls_pcie_write_config(struct pci_controller *hose, pci_dev_t d,
- int where, u32 val)
+static int ls_pcie_write_config(struct udevice *bus, pci_dev_t bdf,
+ uint offset, ulong value,
+ enum pci_size_t size)
{
- struct ls_pcie *pcie = hose->priv_data;
- u32 busdev, *addr;
+ struct ls_pcie *pcie = dev_get_priv(bus);
+ void *address;
- if (ls_pcie_addr_valid(hose, d))
- return -EINVAL;
+ if (ls_pcie_addr_valid(pcie, bdf))
+ return 0;
- if (PCI_BUS(d) == hose->first_busno) {
- addr = pcie->dbi + (where & ~0x3);
- } else {
- busdev = PCIE_ATU_BUS(PCI_BUS(d)) |
- PCIE_ATU_DEV(PCI_DEV(d)) |
- PCIE_ATU_FUNC(PCI_FUNC(d));
-
- if (PCI_BUS(d) == hose->first_busno + 1) {
- ls_pcie_cfg0_set_busdev(pcie, busdev);
- addr = pcie->va_cfg0 + (where & ~0x3);
- } else {
- ls_pcie_cfg1_set_busdev(pcie, busdev);
- addr = pcie->va_cfg1 + (where & ~0x3);
- }
+ address = ls_pcie_conf_address(pcie, bdf, offset);
+
+ switch (size) {
+ case PCI_SIZE_8:
+ writeb(value, address);
+ return 0;
+ case PCI_SIZE_16:
+ writew(value, address);
+ return 0;
+ case PCI_SIZE_32:
+ writel(value, address);
+ return 0;
+ default:
+ return -EINVAL;
}
+}
- writel(val, addr);
+/* Clear multi-function bit */
+static void ls_pcie_clear_multifunction(struct ls_pcie *pcie)
+{
+ writeb(PCI_HEADER_TYPE_BRIDGE, pcie->dbi + PCI_HEADER_TYPE);
+}
- return 0;
+/* Fix class value */
+static void ls_pcie_fix_class(struct ls_pcie *pcie)
+{
+ writew(PCI_CLASS_BRIDGE_PCI, pcie->dbi + PCI_CLASS_DEVICE);
}
-static void ls_pcie_setup_ctrl(struct ls_pcie *pcie,
- struct ls_pcie_info *info)
+/* Drop MSG TLP except for Vendor MSG */
+static void ls_pcie_drop_msg_tlp(struct ls_pcie *pcie)
{
- struct pci_controller *hose = &pcie->hose;
- pci_dev_t dev = PCI_BDF(hose->first_busno, 0, 0);
+ u32 val;
- ls_pcie_setup_atu(pcie, info);
+ val = dbi_readl(pcie, PCIE_STRFMR1);
+ val &= 0xDFFFFFFF;
+ dbi_writel(pcie, val, PCIE_STRFMR1);
+}
- pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_0, 0);
+/* Disable all bars in RC mode */
+static void ls_pcie_disable_bars(struct ls_pcie *pcie)
+{
+ u32 sriov;
- /* program correct class for RC */
- writel(1, pcie->dbi + PCIE_DBI_RO_WR_EN);
- pci_hose_write_config_word(hose, dev, PCI_CLASS_DEVICE,
- PCI_CLASS_BRIDGE_PCI);
-#ifndef CONFIG_LS102XA
- writel(0, pcie->dbi + PCIE_DBI_RO_WR_EN);
-#endif
+ sriov = in_le32(pcie->dbi + PCIE_SRIOV);
+
+ if (PCI_EXT_CAP_ID(sriov) == PCI_EXT_CAP_ID_SRIOV)
+ return;
+
+ dbi_writel(pcie, 0, PCIE_CS2_OFFSET + PCI_BASE_ADDRESS_0);
+ dbi_writel(pcie, 0, PCIE_CS2_OFFSET + PCI_BASE_ADDRESS_1);
+ dbi_writel(pcie, 0, PCIE_CS2_OFFSET + PCI_ROM_ADDRESS1);
}
-static void ls_pcie_ep_setup_atu(struct ls_pcie *pcie,
- struct ls_pcie_info *info)
+static void ls_pcie_setup_ctrl(struct ls_pcie *pcie)
+{
+ ls_pcie_setup_atu(pcie);
+
+ dbi_writel(pcie, 1, PCIE_DBI_RO_WR_EN);
+ ls_pcie_fix_class(pcie);
+ ls_pcie_clear_multifunction(pcie);
+ ls_pcie_drop_msg_tlp(pcie);
+ dbi_writel(pcie, 0, PCIE_DBI_RO_WR_EN);
+
+ ls_pcie_disable_bars(pcie);
+}
+
+static void ls_pcie_ep_setup_atu(struct ls_pcie *pcie)
{
u64 phys = CONFIG_SYS_PCI_EP_MEMORY_BASE;
/* ATU 0 : INBOUND : map BAR0 */
- ls_pcie_iatu_inbound_set(pcie, PCIE_ATU_REGION_INDEX0, 0, phys);
+ ls_pcie_atu_inbound_set(pcie, 0, 0, phys);
/* ATU 1 : INBOUND : map BAR1 */
phys += PCIE_BAR1_SIZE;
- ls_pcie_iatu_inbound_set(pcie, PCIE_ATU_REGION_INDEX1, 1, phys);
+ ls_pcie_atu_inbound_set(pcie, 1, 1, phys);
/* ATU 2 : INBOUND : map BAR2 */
phys += PCIE_BAR2_SIZE;
- ls_pcie_iatu_inbound_set(pcie, PCIE_ATU_REGION_INDEX2, 2, phys);
+ ls_pcie_atu_inbound_set(pcie, 2, 2, phys);
/* ATU 3 : INBOUND : map BAR4 */
phys = CONFIG_SYS_PCI_EP_MEMORY_BASE + PCIE_BAR4_SIZE;
- ls_pcie_iatu_inbound_set(pcie, PCIE_ATU_REGION_INDEX3, 4, phys);
-
- /* ATU 0 : OUTBOUND : map 4G MEM */
- ls_pcie_iatu_outbound_set(pcie, PCIE_ATU_REGION_INDEX0,
- PCIE_ATU_TYPE_MEM,
- info->phys_base,
- 0,
- 4 * 1024 * 1024 * 1024ULL);
+ ls_pcie_atu_inbound_set(pcie, 3, 4, phys);
+
+ /* ATU 0 : OUTBOUND : map MEM */
+ ls_pcie_atu_outbound_set(pcie, 0,
+ PCIE_ATU_TYPE_MEM,
+ pcie->cfg_res.start,
+ 0,
+ CONFIG_SYS_PCI_MEMORY_SIZE);
}
/* BAR0 and BAR1 are 32bit BAR2 and BAR4 are 64bit */
@@ -451,35 +531,28 @@ static void ls_pcie_ep_setup_bars(void *bar_base)
ls_pcie_ep_setup_bar(bar_base, 4, PCIE_BAR4_SIZE);
}
-static void ls_pcie_setup_ep(struct ls_pcie *pcie, struct ls_pcie_info *info)
+static void ls_pcie_setup_ep(struct ls_pcie *pcie)
{
- struct pci_controller *hose = &pcie->hose;
- pci_dev_t dev = PCI_BDF(hose->first_busno, 0, 0);
- int sriov;
+ u32 sriov;
- sriov = pci_hose_find_ext_capability(hose, dev, PCI_EXT_CAP_ID_SRIOV);
- if (sriov) {
+ sriov = readl(pcie->dbi + PCIE_SRIOV);
+ if (PCI_EXT_CAP_ID(sriov) == PCI_EXT_CAP_ID_SRIOV) {
int pf, vf;
for (pf = 0; pf < PCIE_PF_NUM; pf++) {
for (vf = 0; vf <= PCIE_VF_NUM; vf++) {
-#ifndef CONFIG_LS102XA
- writel(PCIE_LCTRL0_VAL(pf, vf),
- pcie->dbi + PCIE_LUT_BASE +
- PCIE_LUT_LCTRL0);
-#endif
+ ctrl_writel(pcie, PCIE_LCTRL0_VAL(pf, vf),
+ PCIE_PF_VF_CTRL);
+
ls_pcie_ep_setup_bars(pcie->dbi);
- ls_pcie_ep_setup_atu(pcie, info);
+ ls_pcie_ep_setup_atu(pcie);
}
}
-
/* Disable CFG2 */
-#ifndef CONFIG_LS102XA
- writel(0, pcie->dbi + PCIE_LUT_BASE + PCIE_LUT_LCTRL0);
-#endif
+ ctrl_writel(pcie, 0, PCIE_PF_VF_CTRL);
} else {
ls_pcie_ep_setup_bars(pcie->dbi + PCIE_NO_SRIOV_BAR_BASE);
- ls_pcie_ep_setup_atu(pcie, info);
+ ls_pcie_ep_setup_atu(pcie);
}
}
@@ -499,15 +572,11 @@ static int ls_pcie_next_lut_index(struct ls_pcie *pcie)
* Program a single LUT entry
*/
static void ls_pcie_lut_set_mapping(struct ls_pcie *pcie, int index, u32 devid,
- u32 streamid)
+ u32 streamid)
{
- void __iomem *lut;
-
- lut = pcie->dbi + PCIE_LUT_BASE;
-
/* leave mask as all zeroes, want to match all bits */
- writel((devid << 16), lut + PCIE_LUT_UDR(index));
- writel(streamid | PCIE_LUT_ENABLE, lut + PCIE_LUT_LDR(index));
+ lut_writel(pcie, devid << 16, PCIE_LUT_UDR(index));
+ lut_writel(pcie, streamid | PCIE_LUT_ENABLE, PCIE_LUT_LDR(index));
}
/* returns the next available streamid */
@@ -532,26 +601,30 @@ static u32 ls_pcie_next_streamid(void)
static void fdt_pcie_set_msi_map_entry(void *blob, struct ls_pcie *pcie,
u32 devid, u32 streamid)
{
- char pcie_path[19];
u32 *prop;
u32 phandle;
int nodeoffset;
/* find pci controller node */
- snprintf(pcie_path, sizeof(pcie_path), "/soc/pcie@%llx",
- (u64)pcie->dbi);
- nodeoffset = fdt_path_offset(blob, pcie_path);
+ nodeoffset = fdt_node_offset_by_compat_reg(blob, "fsl,ls-pcie",
+ pcie->dbi_res.start);
if (nodeoffset < 0) {
- printf("\n%s: ERROR: unable to update PCIe node: %s\n",
- __func__, pcie_path);
+ #ifdef FSL_PCIE_COMPAT /* Compatible with older version of dts node */
+ nodeoffset = fdt_node_offset_by_compat_reg(blob,
+ FSL_PCIE_COMPAT,
+ pcie->dbi_res.start);
+ if (nodeoffset < 0)
+ return;
+ #else
return;
+ #endif
}
/* get phandle to MSI controller */
prop = (u32 *)fdt_getprop(blob, nodeoffset, "msi-parent", 0);
if (prop == NULL) {
- printf("\n%s: ERROR: missing msi-parent: %s\n", __func__,
- pcie_path);
+ printf("\n%s: ERROR: missing msi-parent: PCIe%d\n",
+ __func__, pcie->idx);
return;
}
phandle = be32_to_cpu(*prop);
@@ -565,252 +638,201 @@ static void fdt_pcie_set_msi_map_entry(void *blob, struct ls_pcie *pcie,
static void fdt_fixup_pcie(void *blob)
{
- unsigned int found_multi = 0;
- unsigned char header_type;
- int index;
- u32 streamid;
- pci_dev_t dev, bdf;
- int bus;
- unsigned short id;
- struct pci_controller *hose;
+ struct udevice *dev, *bus;
struct ls_pcie *pcie;
- int i;
-
- for (i = 0, hose = pci_get_hose_head(); hose; hose = hose->next, i++) {
- pcie = hose->priv_data;
- for (bus = hose->first_busno; bus <= hose->last_busno; bus++) {
-
- for (dev = PCI_BDF(bus, 0, 0);
- dev < PCI_BDF(bus, PCI_MAX_PCI_DEVICES - 1,
- PCI_MAX_PCI_FUNCTIONS - 1);
- dev += PCI_BDF(0, 0, 1)) {
-
- if (PCI_FUNC(dev) && !found_multi)
- continue;
-
- pci_read_config_word(dev, PCI_VENDOR_ID, &id);
-
- pci_read_config_byte(dev, PCI_HEADER_TYPE,
- &header_type);
-
- if ((id == 0xFFFF) || (id == 0x0000))
- continue;
-
- if (!PCI_FUNC(dev))
- found_multi = header_type & 0x80;
-
- streamid = ls_pcie_next_streamid();
- if (streamid == 0xffffffff) {
- printf("ERROR: no stream ids free\n");
- continue;
- }
-
- index = ls_pcie_next_lut_index(pcie);
- if (index < 0) {
- printf("ERROR: no LUT indexes free\n");
- continue;
- }
-
- /* the DT fixup must be relative to the hose first_busno */
- bdf = dev - PCI_BDF(hose->first_busno, 0, 0);
-
- /* map PCI b.d.f to streamID in LUT */
- ls_pcie_lut_set_mapping(pcie, index, bdf >> 8,
- streamid);
+ u32 streamid;
+ int index;
+ pci_dev_t bdf;
+
+ /* Scan all known buses */
+ for (pci_find_first_device(&dev);
+ dev;
+ pci_find_next_device(&dev)) {
+ for (bus = dev; device_is_on_pci_bus(bus);)
+ bus = bus->parent;
+ pcie = dev_get_priv(bus);
+
+ streamid = ls_pcie_next_streamid();
+ if (streamid == 0xffffffff) {
+ printf("ERROR: no stream ids free\n");
+ continue;
+ }
- /* update msi-map in device tree */
- fdt_pcie_set_msi_map_entry(blob, pcie, bdf >> 8,
- streamid);
- }
+ index = ls_pcie_next_lut_index(pcie);
+ if (index < 0) {
+ printf("ERROR: no LUT indexes free\n");
+ continue;
}
+
+ /* the DT fixup must be relative to the hose first_busno */
+ bdf = dm_pci_get_bdf(dev) - PCI_BDF(bus->seq, 0, 0);
+ /* map PCI b.d.f to streamID in LUT */
+ ls_pcie_lut_set_mapping(pcie, index, bdf >> 8,
+ streamid);
+ /* update msi-map in device tree */
+ fdt_pcie_set_msi_map_entry(blob, pcie, bdf >> 8,
+ streamid);
}
}
#endif
-int ls_pcie_init_ctrl(int busno, enum srds_prtcl dev, struct ls_pcie_info *info)
+#ifdef CONFIG_OF_BOARD_SETUP
+#include <libfdt.h>
+#include <fdt_support.h>
+
+static void ft_pcie_ls_setup(void *blob, struct ls_pcie *pcie)
{
- struct ls_pcie *pcie;
- struct pci_controller *hose;
- int num = dev - PCIE1;
- pci_dev_t pdev = PCI_BDF(busno, 0, 0);
- int i, linkup, ep_mode;
- u8 header_type;
- u16 temp16;
+ int off;
- if (!is_serdes_configured(dev)) {
- printf("PCIe%d: disabled\n", num + 1);
- return busno;
+ off = fdt_node_offset_by_compat_reg(blob, "fsl,ls-pcie",
+ pcie->dbi_res.start);
+ if (off < 0) {
+ #ifdef FSL_PCIE_COMPAT /* Compatible with older version of dts node */
+ off = fdt_node_offset_by_compat_reg(blob,
+ FSL_PCIE_COMPAT,
+ pcie->dbi_res.start);
+ if (off < 0)
+ return;
+ #else
+ return;
+ #endif
}
- pcie = malloc(sizeof(*pcie));
- if (!pcie)
- return busno;
- memset(pcie, 0, sizeof(*pcie));
-
- hose = &pcie->hose;
- hose->priv_data = pcie;
- hose->first_busno = busno;
- pcie->idx = num;
- pcie->dbi = map_physmem(info->regs, PCIE_DBI_SIZE, MAP_NOCACHE);
- pcie->va_cfg0 = map_physmem(info->cfg0_phys,
- info->cfg0_size,
- MAP_NOCACHE);
- pcie->va_cfg1 = map_physmem(info->cfg1_phys,
- info->cfg1_size,
- MAP_NOCACHE);
- pcie->next_lut_index = 0;
-
- /* outbound memory */
- pci_set_region(&hose->regions[0],
- (pci_size_t)info->mem_bus,
- (phys_size_t)info->mem_phys,
- (pci_size_t)info->mem_size,
- PCI_REGION_MEM);
-
- /* outbound io */
- pci_set_region(&hose->regions[1],
- (pci_size_t)info->io_bus,
- (phys_size_t)info->io_phys,
- (pci_size_t)info->io_size,
- PCI_REGION_IO);
-
- /* System memory space */
- pci_set_region(&hose->regions[2],
- CONFIG_SYS_PCI_MEMORY_BUS,
- CONFIG_SYS_PCI_MEMORY_PHYS,
- CONFIG_SYS_PCI_MEMORY_SIZE,
- PCI_REGION_SYS_MEMORY);
-
- hose->region_count = 3;
-
- for (i = 0; i < hose->region_count; i++)
- debug("PCI reg:%d %016llx:%016llx %016llx %08lx\n",
- i,
- (u64)hose->regions[i].phys_start,
- (u64)hose->regions[i].bus_start,
- (u64)hose->regions[i].size,
- hose->regions[i].flags);
-
- pci_set_ops(hose,
- pci_hose_read_config_byte_via_dword,
- pci_hose_read_config_word_via_dword,
- ls_pcie_read_config,
- pci_hose_write_config_byte_via_dword,
- pci_hose_write_config_word_via_dword,
- ls_pcie_write_config);
-
- pci_hose_read_config_byte(hose, pdev, PCI_HEADER_TYPE, &header_type);
- ep_mode = (header_type & 0x7f) == PCI_HEADER_TYPE_NORMAL;
- printf("PCIe%u: %s ", info->pci_num,
- ep_mode ? "Endpoint" : "Root Complex");
-
- if (ep_mode)
- ls_pcie_setup_ep(pcie, info);
+ if (pcie->enabled)
+ fdt_set_node_status(blob, off, FDT_STATUS_OKAY, 0);
else
- ls_pcie_setup_ctrl(pcie, info);
-
- linkup = ls_pcie_link_up(pcie);
-
- if (!linkup) {
- /* Let the user know there's no PCIe link */
- printf("no link, regs @ 0x%lx\n", info->regs);
- hose->last_busno = hose->first_busno;
- return busno;
- }
-
- /* Print the negotiated PCIe link width */
- pci_hose_read_config_word(hose, pdev, PCIE_LINK_STA, &temp16);
- printf("x%d gen%d, regs @ 0x%lx\n", (temp16 & 0x3f0) >> 4,
- (temp16 & 0xf), info->regs);
-
- if (ep_mode)
- return busno;
+ fdt_set_node_status(blob, off, FDT_STATUS_DISABLED, 0);
+}
- pci_register_hose(hose);
+void ft_pci_setup(void *blob, bd_t *bd)
+{
+ struct ls_pcie *pcie;
- hose->last_busno = pci_hose_scan(hose);
+ list_for_each_entry(pcie, &ls_pcie_list, list)
+ ft_pcie_ls_setup(blob, pcie);
- printf("PCIe%x: Bus %02x - %02x\n",
- info->pci_num, hose->first_busno, hose->last_busno);
+ #ifdef CONFIG_FSL_LSCH3
+ fdt_fixup_pcie(blob);
+ #endif
+}
- return hose->last_busno + 1;
+#else
+void ft_pci_setup(void *blob, bd_t *bd)
+{
}
+#endif
-int ls_pcie_init_board(int busno)
+static int ls_pcie_probe(struct udevice *dev)
{
- struct ls_pcie_info info;
+ struct ls_pcie *pcie = dev_get_priv(dev);
+ void *fdt = (void *)gd->fdt_blob;
+ int node = dev->of_offset;
+ u8 header_type;
+ u16 link_sta;
+ bool ep_mode;
+ int ret;
-#ifdef CONFIG_PCIE1
- SET_LS_PCIE_INFO(info, 1);
- busno = ls_pcie_init_ctrl(busno, PCIE1, &info);
-#endif
+ pcie->bus = dev;
-#ifdef CONFIG_PCIE2
- SET_LS_PCIE_INFO(info, 2);
- busno = ls_pcie_init_ctrl(busno, PCIE2, &info);
-#endif
+ ret = fdt_get_named_resource(fdt, node, "reg", "reg-names",
+ "dbi", &pcie->dbi_res);
+ if (ret) {
+ printf("ls-pcie: resource \"dbi\" not found\n");
+ return ret;
+ }
-#ifdef CONFIG_PCIE3
- SET_LS_PCIE_INFO(info, 3);
- busno = ls_pcie_init_ctrl(busno, PCIE3, &info);
-#endif
+ pcie->idx = (pcie->dbi_res.start - PCIE_SYS_BASE_ADDR) / PCIE_CCSR_SIZE;
-#ifdef CONFIG_PCIE4
- SET_LS_PCIE_INFO(info, 4);
- busno = ls_pcie_init_ctrl(busno, PCIE4, &info);
-#endif
+ list_add(&pcie->list, &ls_pcie_list);
- return busno;
-}
+ pcie->enabled = is_serdes_configured(PCIE_SRDS_PRTCL(pcie->idx));
+ if (!pcie->enabled) {
+ printf("PCIe%d: %s disabled\n", pcie->idx, dev->name);
+ return 0;
+ }
-void pci_init_board(void)
-{
- ls_pcie_init_board(0);
-}
+ pcie->dbi = map_physmem(pcie->dbi_res.start,
+ fdt_resource_size(&pcie->dbi_res),
+ MAP_NOCACHE);
+
+ ret = fdt_get_named_resource(fdt, node, "reg", "reg-names",
+ "lut", &pcie->lut_res);
+ if (!ret)
+ pcie->lut = map_physmem(pcie->lut_res.start,
+ fdt_resource_size(&pcie->lut_res),
+ MAP_NOCACHE);
+
+ ret = fdt_get_named_resource(fdt, node, "reg", "reg-names",
+ "ctrl", &pcie->ctrl_res);
+ if (!ret)
+ pcie->ctrl = map_physmem(pcie->ctrl_res.start,
+ fdt_resource_size(&pcie->ctrl_res),
+ MAP_NOCACHE);
+ if (!pcie->ctrl)
+ pcie->ctrl = pcie->lut;
+
+ if (!pcie->ctrl) {
+ printf("%s: NOT find CTRL\n", dev->name);
+ return 0;
+ }
-#ifdef CONFIG_OF_BOARD_SETUP
-#include <libfdt.h>
-#include <fdt_support.h>
+ ret = fdt_get_named_resource(fdt, node, "reg", "reg-names",
+ "config", &pcie->cfg_res);
+ if (ret) {
+ printf("%s: resource \"config\" not found\n", dev->name);
+ return 0;
+ }
-static void ft_pcie_ls_setup(void *blob, const char *pci_compat,
- unsigned long ctrl_addr, enum srds_prtcl dev)
-{
- int off;
+ pcie->cfg0 = map_physmem(pcie->cfg_res.start,
+ fdt_resource_size(&pcie->cfg_res),
+ MAP_NOCACHE);
+ pcie->cfg1 = pcie->cfg0 + fdt_resource_size(&pcie->cfg_res) / 2;
- off = fdt_node_offset_by_compat_reg(blob, pci_compat,
- (phys_addr_t)ctrl_addr);
- if (off < 0)
- return;
+ pcie->big_endian = fdtdec_get_bool(fdt, node, "big-endian");
- if (!is_serdes_configured(dev))
- fdt_set_node_status(blob, off, FDT_STATUS_DISABLED, 0);
-}
+ debug("%s dbi:%lx lut:%lx ctrl:0x%lx cfg0:0x%lx, big-endian:%d\n",
+ dev->name, (unsigned long)pcie->dbi, (unsigned long)pcie->lut,
+ (unsigned long)pcie->ctrl, (unsigned long)pcie->cfg0,
+ pcie->big_endian);
-void ft_pci_setup(void *blob, bd_t *bd)
-{
- #ifdef CONFIG_PCIE1
- ft_pcie_ls_setup(blob, FSL_PCIE_COMPAT, CONFIG_SYS_PCIE1_ADDR, PCIE1);
- #endif
+ header_type = readb(pcie->dbi + PCI_HEADER_TYPE);
+ ep_mode = (header_type & 0x7f) == PCI_HEADER_TYPE_NORMAL;
+ printf("PCIe%u: %s %s", pcie->idx, dev->name,
+ ep_mode ? "Endpoint" : "Root Complex");
- #ifdef CONFIG_PCIE2
- ft_pcie_ls_setup(blob, FSL_PCIE_COMPAT, CONFIG_SYS_PCIE2_ADDR, PCIE2);
- #endif
+ if (ep_mode)
+ ls_pcie_setup_ep(pcie);
+ else
+ ls_pcie_setup_ctrl(pcie);
- #ifdef CONFIG_PCIE3
- ft_pcie_ls_setup(blob, FSL_PCIE_COMPAT, CONFIG_SYS_PCIE3_ADDR, PCIE3);
- #endif
+ if (!ls_pcie_link_up(pcie)) {
+ /* Let the user know there's no PCIe link */
+ printf(": no link\n");
+ return 0;
+ }
- #ifdef CONFIG_PCIE4
- ft_pcie_ls_setup(blob, FSL_PCIE_COMPAT, CONFIG_SYS_PCIE4_ADDR, PCIE4);
- #endif
+ /* Print the negotiated PCIe link width */
+ link_sta = readw(pcie->dbi + PCIE_LINK_STA);
+ printf(": x%d gen%d\n", (link_sta & 0x3f0) >> 4, link_sta & 0xf);
- #ifdef CONFIG_FSL_LSCH3
- fdt_fixup_pcie(blob);
- #endif
+ return 0;
}
-#else
-void ft_pci_setup(void *blob, bd_t *bd)
-{
-}
-#endif
+static const struct dm_pci_ops ls_pcie_ops = {
+ .read_config = ls_pcie_read_config,
+ .write_config = ls_pcie_write_config,
+};
+
+static const struct udevice_id ls_pcie_ids[] = {
+ { .compatible = "fsl,ls-pcie" },
+ { }
+};
+
+U_BOOT_DRIVER(pci_layerscape) = {
+ .name = "pci_layerscape",
+ .id = UCLASS_PCI,
+ .of_match = ls_pcie_ids,
+ .ops = &ls_pcie_ops,
+ .probe = ls_pcie_probe,
+ .priv_auto_alloc_size = sizeof(struct ls_pcie),
+};
diff --git a/include/configs/ls1012a_common.h b/include/configs/ls1012a_common.h
index 5fb6c47..d9471c5 100644
--- a/include/configs/ls1012a_common.h
+++ b/include/configs/ls1012a_common.h
@@ -90,6 +90,18 @@
#define CONFIG_BAUDRATE 115200
#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
+/* PCIe */
+#define CONFIG_PCI /* Enable PCI/PCIE */
+#define CONFIG_DM_PCI /* Enable driver mode for PCI */
+#define CONFIG_DM_PCI_COMPAT
+#define CONFIG_PCIE_LAYERSCAPE /* Use common FSL Layerscape PCIe code */
+#define CONFIG_SYS_PCI_64BIT
+
+#define CONFIG_NET_MULTI
+#define CONFIG_PCI_PNP
+#define CONFIG_PCI_SCAN_SHOW
+#define CONFIG_CMD_PCI
+
/* Command line configuration */
#define CONFIG_CMD_ENV
#undef CONFIG_CMD_IMLS
diff --git a/include/configs/ls1012aqds.h b/include/configs/ls1012aqds.h
index 54abf30..4238ccd 100644
--- a/include/configs/ls1012aqds.h
+++ b/include/configs/ls1012aqds.h
@@ -154,30 +154,6 @@
#define CONFIG_SYS_SCSI_MAX_LUN 1
#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
CONFIG_SYS_SCSI_MAX_LUN)
-#define CONFIG_PCI /* Enable PCI/PCIE */
-#define CONFIG_PCIE1 /* PCIE controller 1 */
-#define CONFIG_PCIE_LAYERSCAPE /* Use common FSL Layerscape PCIe code */
-#define FSL_PCIE_COMPAT "fsl,ls1043a-pcie"
-
-#define CONFIG_SYS_PCI_64BIT
-
-#define CONFIG_SYS_PCIE_CFG0_PHYS_OFF 0x00000000
-#define CONFIG_SYS_PCIE_CFG0_SIZE 0x00001000 /* 4k */
-#define CONFIG_SYS_PCIE_CFG1_PHYS_OFF 0x00001000
-#define CONFIG_SYS_PCIE_CFG1_SIZE 0x00001000 /* 4k */
-
-#define CONFIG_SYS_PCIE_IO_BUS 0x00000000
-#define CONFIG_SYS_PCIE_IO_PHYS_OFF 0x00010000
-#define CONFIG_SYS_PCIE_IO_SIZE 0x00010000 /* 64k */
-
-#define CONFIG_SYS_PCIE_MEM_BUS 0x08000000
-#define CONFIG_SYS_PCIE_MEM_PHYS_OFF 0x04000000
-#define CONFIG_SYS_PCIE_MEM_SIZE 0x80000000 /* 128M */
-
-#define CONFIG_NET_MULTI
-#define CONFIG_PCI_PNP
-#define CONFIG_PCI_SCAN_SHOW
-#define CONFIG_CMD_PCI
#define CONFIG_CMD_MEMINFO
#define CONFIG_CMD_MEMTEST
diff --git a/include/configs/ls1012ardb.h b/include/configs/ls1012ardb.h
index 0c13dde..6d0d308 100644
--- a/include/configs/ls1012ardb.h
+++ b/include/configs/ls1012ardb.h
@@ -67,30 +67,6 @@
#define CONFIG_SYS_SCSI_MAX_LUN 1
#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
CONFIG_SYS_SCSI_MAX_LUN)
-#define CONFIG_PCI /* Enable PCI/PCIE */
-#define CONFIG_PCIE1 /* PCIE controller 1 */
-#define CONFIG_PCIE_LAYERSCAPE /* Use common FSL Layerscape PCIe code */
-#define FSL_PCIE_COMPAT "fsl,ls1043a-pcie"
-
-#define CONFIG_SYS_PCI_64BIT
-
-#define CONFIG_SYS_PCIE_CFG0_PHYS_OFF 0x00000000
-#define CONFIG_SYS_PCIE_CFG0_SIZE 0x00001000 /* 4k */
-#define CONFIG_SYS_PCIE_CFG1_PHYS_OFF 0x00001000
-#define CONFIG_SYS_PCIE_CFG1_SIZE 0x00001000 /* 4k */
-
-#define CONFIG_SYS_PCIE_IO_BUS 0x00000000
-#define CONFIG_SYS_PCIE_IO_PHYS_OFF 0x00010000
-#define CONFIG_SYS_PCIE_IO_SIZE 0x00010000 /* 64k */
-
-#define CONFIG_SYS_PCIE_MEM_BUS 0x08000000
-#define CONFIG_SYS_PCIE_MEM_PHYS_OFF 0x04000000
-#define CONFIG_SYS_PCIE_MEM_SIZE 0x80000000 /* 128M */
-
-#define CONFIG_NET_MULTI
-#define CONFIG_PCI_PNP
-#define CONFIG_PCI_SCAN_SHOW
-#define CONFIG_CMD_PCI
#define CONFIG_CMD_MEMINFO
#define CONFIG_CMD_MEMTEST
diff --git a/include/configs/ls1021aqds.h b/include/configs/ls1021aqds.h
index 0d72e69..fc2cd1a 100644
--- a/include/configs/ls1021aqds.h
+++ b/include/configs/ls1021aqds.h
@@ -515,26 +515,12 @@ unsigned long get_board_ddr_clk(void);
/* PCIe */
#define CONFIG_PCI /* Enable PCI/PCIE */
-#define CONFIG_PCIE1 /* PCIE controller 1 */
-#define CONFIG_PCIE2 /* PCIE controller 2 */
+#define CONFIG_DM_PCI /* Enable driver mode for PCI */
+#define CONFIG_DM_PCI_COMPAT
#define CONFIG_PCIE_LAYERSCAPE /* Use common FSL Layerscape PCIe code */
#define FSL_PCIE_COMPAT "fsl,ls1021a-pcie"
-
#define CONFIG_SYS_PCI_64BIT
-#define CONFIG_SYS_PCIE_CFG0_PHYS_OFF 0x00000000
-#define CONFIG_SYS_PCIE_CFG0_SIZE 0x00001000 /* 4k */
-#define CONFIG_SYS_PCIE_CFG1_PHYS_OFF 0x00001000
-#define CONFIG_SYS_PCIE_CFG1_SIZE 0x00001000 /* 4k */
-
-#define CONFIG_SYS_PCIE_IO_BUS 0x00000000
-#define CONFIG_SYS_PCIE_IO_PHYS_OFF 0x00010000
-#define CONFIG_SYS_PCIE_IO_SIZE 0x00010000 /* 64k */
-
-#define CONFIG_SYS_PCIE_MEM_BUS 0x08000000
-#define CONFIG_SYS_PCIE_MEM_PHYS_OFF 0x04000000
-#define CONFIG_SYS_PCIE_MEM_SIZE 0x08000000 /* 128M */
-
#ifdef CONFIG_PCI
#define CONFIG_PCI_PNP
#define CONFIG_PCI_SCAN_SHOW
diff --git a/include/configs/ls1021atwr.h b/include/configs/ls1021atwr.h
index e5ac50e..db792a0 100644
--- a/include/configs/ls1021atwr.h
+++ b/include/configs/ls1021atwr.h
@@ -387,26 +387,12 @@
/* PCIe */
#define CONFIG_PCI /* Enable PCI/PCIE */
-#define CONFIG_PCIE1 /* PCIE controller 1 */
-#define CONFIG_PCIE2 /* PCIE controller 2 */
+#define CONFIG_DM_PCI /* Enable driver mode for PCI */
+#define CONFIG_DM_PCI_COMPAT
#define CONFIG_PCIE_LAYERSCAPE /* Use common FSL Layerscape PCIe code */
#define FSL_PCIE_COMPAT "fsl,ls1021a-pcie"
-
#define CONFIG_SYS_PCI_64BIT
-#define CONFIG_SYS_PCIE_CFG0_PHYS_OFF 0x00000000
-#define CONFIG_SYS_PCIE_CFG0_SIZE 0x00001000 /* 4k */
-#define CONFIG_SYS_PCIE_CFG1_PHYS_OFF 0x00001000
-#define CONFIG_SYS_PCIE_CFG1_SIZE 0x00001000 /* 4k */
-
-#define CONFIG_SYS_PCIE_IO_BUS 0x00000000
-#define CONFIG_SYS_PCIE_IO_PHYS_OFF 0x00010000
-#define CONFIG_SYS_PCIE_IO_SIZE 0x00010000 /* 64k */
-
-#define CONFIG_SYS_PCIE_MEM_BUS 0x08000000
-#define CONFIG_SYS_PCIE_MEM_PHYS_OFF 0x04000000
-#define CONFIG_SYS_PCIE_MEM_SIZE 0x08000000 /* 128M */
-
#ifdef CONFIG_PCI
#define CONFIG_PCI_PNP
#define CONFIG_PCI_SCAN_SHOW
diff --git a/include/configs/ls1043a_common.h b/include/configs/ls1043a_common.h
index ed0e434..c195b07 100644
--- a/include/configs/ls1043a_common.h
+++ b/include/configs/ls1043a_common.h
@@ -126,33 +126,18 @@
/* PCIe */
#define CONFIG_PCI /* Enable PCI/PCIE */
-#define CONFIG_PCIE1 /* PCIE controller 1 */
-#define CONFIG_PCIE2 /* PCIE controller 2 */
-#define CONFIG_PCIE3 /* PCIE controller 3 */
+#define CONFIG_DM_PCI /* Enable driver mode for PCI */
+#define CONFIG_DM_PCI_COMPAT
#define CONFIG_PCIE_LAYERSCAPE /* Use common FSL Layerscape PCIe code */
#define FSL_PCIE_COMPAT "fsl,ls1043a-pcie"
-
#define CONFIG_SYS_PCI_64BIT
-#define CONFIG_SYS_PCIE_CFG0_PHYS_OFF 0x00000000
-#define CONFIG_SYS_PCIE_CFG0_SIZE 0x00001000 /* 4k */
-#define CONFIG_SYS_PCIE_CFG1_PHYS_OFF 0x00001000
-#define CONFIG_SYS_PCIE_CFG1_SIZE 0x00001000 /* 4k */
-
-#define CONFIG_SYS_PCIE_IO_BUS 0x00000000
-#define CONFIG_SYS_PCIE_IO_PHYS_OFF 0x00010000
-#define CONFIG_SYS_PCIE_IO_SIZE 0x00010000 /* 64k */
-
-#define CONFIG_SYS_PCIE_MEM_BUS 0x40000000
-#define CONFIG_SYS_PCIE_MEM_PHYS_OFF 0x40000000
-#define CONFIG_SYS_PCIE_MEM_SIZE 0x40000000 /* 1G */
-
#ifdef CONFIG_PCI
-#define CONFIG_NET_MULTI
#define CONFIG_PCI_PNP
-#define CONFIG_E1000
#define CONFIG_PCI_SCAN_SHOW
#define CONFIG_CMD_PCI
+#define CONFIG_NET_MULTI
+#define CONFIG_E1000
#endif
/* Command line configuration */
diff --git a/include/configs/ls2080a_common.h b/include/configs/ls2080a_common.h
index 42d0298..a6c8f9f 100644
--- a/include/configs/ls2080a_common.h
+++ b/include/configs/ls2080a_common.h
@@ -176,29 +176,18 @@ unsigned long long get_qixis_addr(void);
#endif
/* PCIe */
-#define CONFIG_PCIE1 /* PCIE controller 1 */
-#define CONFIG_PCIE2 /* PCIE controller 2 */
-#define CONFIG_PCIE3 /* PCIE controller 3 */
-#define CONFIG_PCIE4 /* PCIE controller 4 */
+#define CONFIG_PCI /* Enable PCIE */
+#define CONFIG_DM_PCI /* Enable driver mode for PCI */
+#define CONFIG_DM_PCI_COMPAT
#define CONFIG_PCIE_LAYERSCAPE /* Use common FSL Layerscape PCIe code */
-#ifdef CONFIG_LS2080A
#define FSL_PCIE_COMPAT "fsl,ls2080a-pcie"
-#endif
-
#define CONFIG_SYS_PCI_64BIT
-#define CONFIG_SYS_PCIE_CFG0_PHYS_OFF 0x00000000
-#define CONFIG_SYS_PCIE_CFG0_SIZE 0x00001000 /* 4k */
-#define CONFIG_SYS_PCIE_CFG1_PHYS_OFF 0x00001000
-#define CONFIG_SYS_PCIE_CFG1_SIZE 0x00001000 /* 4k */
-
-#define CONFIG_SYS_PCIE_IO_BUS 0x00000000
-#define CONFIG_SYS_PCIE_IO_PHYS_OFF 0x00010000
-#define CONFIG_SYS_PCIE_IO_SIZE 0x00010000 /* 64k */
-
-#define CONFIG_SYS_PCIE_MEM_BUS 0x40000000
-#define CONFIG_SYS_PCIE_MEM_PHYS_OFF 0x40000000
-#define CONFIG_SYS_PCIE_MEM_SIZE 0x40000000 /* 1G */
+#ifdef CONFIG_PCI
+#define CONFIG_PCI_PNP
+#define CONFIG_PCI_SCAN_SHOW
+#define CONFIG_CMD_PCI
+#endif
/* Command line configuration */
#define CONFIG_CMD_ENV
diff --git a/include/configs/ls2080aqds.h b/include/configs/ls2080aqds.h
index 5e36ca7..9af6d7e 100644
--- a/include/configs/ls2080aqds.h
+++ b/include/configs/ls2080aqds.h
@@ -349,14 +349,6 @@ unsigned long get_board_ddr_clk(void);
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
#define CONFIG_FSL_MEMAC
-#define CONFIG_PCI /* Enable PCIE */
-#define CONFIG_PCIE_LAYERSCAPE /* Use common FSL Layerscape PCIe code */
-
-#ifdef CONFIG_PCI
-#define CONFIG_PCI_PNP
-#define CONFIG_PCI_SCAN_SHOW
-#define CONFIG_CMD_PCI
-#endif
/* MMC */
#define CONFIG_MMC
diff --git a/include/configs/ls2080ardb.h b/include/configs/ls2080ardb.h
index b93e919..8df3042 100644
--- a/include/configs/ls2080ardb.h
+++ b/include/configs/ls2080ardb.h
@@ -292,14 +292,6 @@ unsigned long get_board_sys_clk(void);
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
#define CONFIG_FSL_MEMAC
-#define CONFIG_PCI /* Enable PCIE */
-#define CONFIG_PCIE_LAYERSCAPE /* Use common FSL Layerscape PCIe code */
-
-#ifdef CONFIG_PCI
-#define CONFIG_PCI_PNP
-#define CONFIG_PCI_SCAN_SHOW
-#define CONFIG_CMD_PCI
-#endif
/* MMC */
#define CONFIG_MMC
--
1.9.1
^ permalink raw reply related [flat|nested] 26+ messages in thread
* [U-Boot] [PATCH 9/9] armv8: ls1046a: Enable PCIe support
2016-10-10 8:47 [U-Boot] [PATCH 1/9] dm: pci: return the real controller in pci_bus_to_hose() Minghuan Lian
` (6 preceding siblings ...)
2016-10-10 8:47 ` [U-Boot] [PATCH 8/9] pci: layerscape: rewrite pci driver based on DM Minghuan Lian
@ 2016-10-10 8:47 ` Minghuan Lian
2016-10-10 8:47 ` Minghuan Lian
2016-10-10 9:03 ` [U-Boot] [PATCH 1/9] dm: pci: return the real controller in pci_bus_to_hose() Bin Meng
9 siblings, 0 replies; 26+ messages in thread
From: Minghuan Lian @ 2016-10-10 8:47 UTC (permalink / raw)
To: u-boot
Signed-off-by: Minghuan Lian <Minghuan.Lian@nxp.com>
---
include/configs/ls1046a_common.h | 15 +++++++++++++++
1 file changed, 15 insertions(+)
diff --git a/include/configs/ls1046a_common.h b/include/configs/ls1046a_common.h
index 7c5e635..f8f5ee2 100644
--- a/include/configs/ls1046a_common.h
+++ b/include/configs/ls1046a_common.h
@@ -117,6 +117,21 @@
#define CONFIG_SYS_I2C_MXC_I2C3
#define CONFIG_SYS_I2C_MXC_I2C4
+/* PCIe */
+#define CONFIG_PCI /* Enable PCI/PCIE */
+#define CONFIG_DM_PCI /* Enable driver mode for PCI */
+#define CONFIG_DM_PCI_COMPAT
+#define CONFIG_PCIE_LAYERSCAPE /* Use common FSL Layerscape PCIe code */
+#define CONFIG_SYS_PCI_64BIT
+
+#ifdef CONFIG_PCI
+#define CONFIG_PCI_PNP
+#define CONFIG_PCI_SCAN_SHOW
+#define CONFIG_CMD_PCI
+#define CONFIG_NET_MULTI
+#define CONFIG_E1000
+#endif
+
/* Command line configuration */
#define CONFIG_CMD_ENV
--
1.9.1
^ permalink raw reply related [flat|nested] 26+ messages in thread
* [U-Boot] [PATCH 9/9] armv8: ls1046a: Enable PCIe support
2016-10-10 8:47 [U-Boot] [PATCH 1/9] dm: pci: return the real controller in pci_bus_to_hose() Minghuan Lian
` (7 preceding siblings ...)
2016-10-10 8:47 ` [U-Boot] [PATCH 9/9] armv8: ls1046a: Enable PCIe support Minghuan Lian
@ 2016-10-10 8:47 ` Minghuan Lian
2016-10-10 11:41 ` Bin Meng
2016-10-10 9:03 ` [U-Boot] [PATCH 1/9] dm: pci: return the real controller in pci_bus_to_hose() Bin Meng
9 siblings, 1 reply; 26+ messages in thread
From: Minghuan Lian @ 2016-10-10 8:47 UTC (permalink / raw)
To: u-boot
Signed-off-by: Minghuan Lian <Minghuan.Lian@nxp.com>
---
include/configs/ls1046a_common.h | 15 +++++++++++++++
1 file changed, 15 insertions(+)
diff --git a/include/configs/ls1046a_common.h b/include/configs/ls1046a_common.h
index 7c5e635..f8f5ee2 100644
--- a/include/configs/ls1046a_common.h
+++ b/include/configs/ls1046a_common.h
@@ -117,6 +117,21 @@
#define CONFIG_SYS_I2C_MXC_I2C3
#define CONFIG_SYS_I2C_MXC_I2C4
+/* PCIe */
+#define CONFIG_PCI /* Enable PCI/PCIE */
+#define CONFIG_DM_PCI /* Enable driver mode for PCI */
+#define CONFIG_DM_PCI_COMPAT
+#define CONFIG_PCIE_LAYERSCAPE /* Use common FSL Layerscape PCIe code */
+#define CONFIG_SYS_PCI_64BIT
+
+#ifdef CONFIG_PCI
+#define CONFIG_PCI_PNP
+#define CONFIG_PCI_SCAN_SHOW
+#define CONFIG_CMD_PCI
+#define CONFIG_NET_MULTI
+#define CONFIG_E1000
+#endif
+
/* Command line configuration */
#define CONFIG_CMD_ENV
--
1.9.1
^ permalink raw reply related [flat|nested] 26+ messages in thread
* [U-Boot] [PATCH 1/9] dm: pci: return the real controller in pci_bus_to_hose()
2016-10-10 8:47 [U-Boot] [PATCH 1/9] dm: pci: return the real controller in pci_bus_to_hose() Minghuan Lian
` (8 preceding siblings ...)
2016-10-10 8:47 ` Minghuan Lian
@ 2016-10-10 9:03 ` Bin Meng
2016-10-10 9:09 ` M.H. Lian
9 siblings, 1 reply; 26+ messages in thread
From: Bin Meng @ 2016-10-10 9:03 UTC (permalink / raw)
To: u-boot
+Simon
Hi Minghuan,
On Mon, Oct 10, 2016 at 4:47 PM, Minghuan Lian <Minghuan.Lian@nxp.com> wrote:
> for the legacy PCI driver, the function pci_bus_to_hose() returns
> the real PCIe controller. To keep consistency, this function is
> changed to return the PCIe controller pointer of the root bus
> instead of the current PCIe bus.
>
> Signed-off-by: Minghuan Lian <Minghuan.Lian@nxp.com>
> ---
> drivers/pci/pci_compat.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/pci/pci_compat.c b/drivers/pci/pci_compat.c
> index ddaf358..25bc095 100644
> --- a/drivers/pci/pci_compat.c
> +++ b/drivers/pci/pci_compat.c
> @@ -49,5 +49,5 @@ struct pci_controller *pci_bus_to_hose(int busnum)
> return NULL;
> }
>
> - return dev_get_uclass_priv(bus);
> + return dev_get_uclass_priv(pci_get_controller(bus));
> }
> --
Any reason why don't we add DM PCI to the new board?
Regards,
Bin
^ permalink raw reply [flat|nested] 26+ messages in thread
* [U-Boot] [PATCH 1/9] dm: pci: return the real controller in pci_bus_to_hose()
2016-10-10 9:03 ` [U-Boot] [PATCH 1/9] dm: pci: return the real controller in pci_bus_to_hose() Bin Meng
@ 2016-10-10 9:09 ` M.H. Lian
2016-10-10 10:37 ` Bin Meng
0 siblings, 1 reply; 26+ messages in thread
From: M.H. Lian @ 2016-10-10 9:09 UTC (permalink / raw)
To: u-boot
Hi Bin?
Thanks for your comments.
The series of patches is to change legacy PCIe driver to DM PCIe driver.
The first two patches are to change DM to support multiple PCIe controllers.
The 8th patch is to change Layerscape PCIe driver based on DM
Other patches are to add PCIe dts node for five SoCs.
Thanks,
Minghuan
> -----Original Message-----
> From: Bin Meng [mailto:bmeng.cn at gmail.com]
> Sent: Monday, October 10, 2016 5:03 PM
> To: M.H. Lian <minghuan.lian@nxp.com>; Simon Glass <sjg@chromium.org>
> Cc: U-Boot Mailing List <u-boot@lists.denx.de>; Mingkai Hu
> <mingkai.hu@nxp.com>; Leo Li <leoyang.li@nxp.com>
> Subject: Re: [U-Boot] [PATCH 1/9] dm: pci: return the real controller in
> pci_bus_to_hose()
>
> +Simon
>
> Hi Minghuan,
>
> On Mon, Oct 10, 2016 at 4:47 PM, Minghuan Lian <Minghuan.Lian@nxp.com>
> wrote:
> > for the legacy PCI driver, the function pci_bus_to_hose() returns the
> > real PCIe controller. To keep consistency, this function is changed to
> > return the PCIe controller pointer of the root bus instead of the
> > current PCIe bus.
> >
> > Signed-off-by: Minghuan Lian <Minghuan.Lian@nxp.com>
> > ---
> > drivers/pci/pci_compat.c | 2 +-
> > 1 file changed, 1 insertion(+), 1 deletion(-)
> >
> > diff --git a/drivers/pci/pci_compat.c b/drivers/pci/pci_compat.c index
> > ddaf358..25bc095 100644
> > --- a/drivers/pci/pci_compat.c
> > +++ b/drivers/pci/pci_compat.c
> > @@ -49,5 +49,5 @@ struct pci_controller *pci_bus_to_hose(int busnum)
> > return NULL;
> > }
> >
> > - return dev_get_uclass_priv(bus);
> > + return dev_get_uclass_priv(pci_get_controller(bus));
> > }
> > --
>
> Any reason why don't we add DM PCI to the new board?
>
> Regards,
> Bin
^ permalink raw reply [flat|nested] 26+ messages in thread
* [U-Boot] [PATCH 1/9] dm: pci: return the real controller in pci_bus_to_hose()
2016-10-10 9:09 ` M.H. Lian
@ 2016-10-10 10:37 ` Bin Meng
2016-10-11 7:12 ` M.H. Lian
0 siblings, 1 reply; 26+ messages in thread
From: Bin Meng @ 2016-10-10 10:37 UTC (permalink / raw)
To: u-boot
Hi Minghuan,
On Mon, Oct 10, 2016 at 5:09 PM, M.H. Lian <minghuan.lian@nxp.com> wrote:
> Hi Bin?
>
> Thanks for your comments.
>
> The series of patches is to change legacy PCIe driver to DM PCIe driver.
> The first two patches are to change DM to support multiple PCIe controllers.
I don't understand what is broken. If you fully convert the driver to
DM PCI, I don't think we need ever touch the pci_compat codes. Could
you please elaborate more?
> The 8th patch is to change Layerscape PCIe driver based on DM
> Other patches are to add PCIe dts node for five SoCs.
>
> Thanks,
> Minghuan
>
Regards,
Bin
^ permalink raw reply [flat|nested] 26+ messages in thread
* [U-Boot] [PATCH 9/9] armv8: ls1046a: Enable PCIe support
2016-10-10 8:47 ` Minghuan Lian
@ 2016-10-10 11:41 ` Bin Meng
2016-10-11 7:14 ` M.H. Lian
0 siblings, 1 reply; 26+ messages in thread
From: Bin Meng @ 2016-10-10 11:41 UTC (permalink / raw)
To: u-boot
Hi Minghuan,
On Mon, Oct 10, 2016 at 4:47 PM, Minghuan Lian <Minghuan.Lian@nxp.com> wrote:
> Signed-off-by: Minghuan Lian <Minghuan.Lian@nxp.com>
> ---
> include/configs/ls1046a_common.h | 15 +++++++++++++++
> 1 file changed, 15 insertions(+)
>
> diff --git a/include/configs/ls1046a_common.h b/include/configs/ls1046a_common.h
> index 7c5e635..f8f5ee2 100644
> --- a/include/configs/ls1046a_common.h
> +++ b/include/configs/ls1046a_common.h
> @@ -117,6 +117,21 @@
> #define CONFIG_SYS_I2C_MXC_I2C3
> #define CONFIG_SYS_I2C_MXC_I2C4
>
> +/* PCIe */
> +#define CONFIG_PCI /* Enable PCI/PCIE */
> +#define CONFIG_DM_PCI /* Enable driver mode for PCI */
> +#define CONFIG_DM_PCI_COMPAT
> +#define CONFIG_PCIE_LAYERSCAPE /* Use common FSL Layerscape PCIe code */
> +#define CONFIG_SYS_PCI_64BIT
Please do not add any Kconfig option in the header file any more.
These already converted Kconfig options should be moved to boards'
defconfig files.
> +
> +#ifdef CONFIG_PCI
> +#define CONFIG_PCI_PNP
> +#define CONFIG_PCI_SCAN_SHOW
> +#define CONFIG_CMD_PCI
> +#define CONFIG_NET_MULTI
> +#define CONFIG_E1000
> +#endif
> +
> /* Command line configuration */
> #define CONFIG_CMD_ENV
>
> --
Regards,
Bin
^ permalink raw reply [flat|nested] 26+ messages in thread
* [U-Boot] [PATCH 8/9] pci: layerscape: rewrite pci driver based on DM
2016-10-10 8:47 ` [U-Boot] [PATCH 8/9] pci: layerscape: rewrite pci driver based on DM Minghuan Lian
@ 2016-10-10 11:49 ` Bin Meng
2016-10-11 7:21 ` M.H. Lian
0 siblings, 1 reply; 26+ messages in thread
From: Bin Meng @ 2016-10-10 11:49 UTC (permalink / raw)
To: u-boot
Hi Minghuan,
On Mon, Oct 10, 2016 at 4:47 PM, Minghuan Lian <Minghuan.Lian@nxp.com> wrote:
> There are more than five kinds of Layerscape SoCs. unfortunately,
> PCIe controller of each SoC is a little bit different. In order
> to avoid too many macro definitions, the patch re-implement PCIe
> driver based on DM. PCIe dts node is to describe the difference.
>
> Signed-off-by: Minghuan Lian <Minghuan.Lian@nxp.com>
> ---
> .../include/asm/arch-fsl-layerscape/immap_lsch3.h | 8 -
> drivers/pci/Kconfig | 8 +
> drivers/pci/pcie_layerscape.c | 958 +++++++++++----------
> include/configs/ls1012a_common.h | 12 +
> include/configs/ls1012aqds.h | 24 -
> include/configs/ls1012ardb.h | 24 -
> include/configs/ls1021aqds.h | 18 +-
> include/configs/ls1021atwr.h | 18 +-
> include/configs/ls1043a_common.h | 23 +-
> include/configs/ls2080a_common.h | 27 +-
> include/configs/ls2080aqds.h | 8 -
> include/configs/ls2080ardb.h | 8 -
These header file changes should not be put in the same commit of the
layerscape PCIe driver conversion. They should be in a separate
commit. So you are likely to have 3 commits: firstly add DM codes with
#ifdef CONFIG_DM_PCI #endif in the layerscape PCIe driver, without
breaking the existing board support. 2nd commit to update the boards
configuration files (defconfig and the header), and 3rd commit to
remove the #ifdef CONFIG_DM_PCI #endif, only leaving the DM version
codes.
> 12 files changed, 526 insertions(+), 610 deletions(-)
>
> diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
> index 7acba27..bd07808 100644
> --- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
> +++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
> @@ -104,14 +104,6 @@
> #define CONFIG_SYS_PCIE2_PHYS_ADDR 0x1200000000ULL
> #define CONFIG_SYS_PCIE3_PHYS_ADDR 0x1400000000ULL
> #define CONFIG_SYS_PCIE4_PHYS_ADDR 0x1600000000ULL
> -/* LUT registers */
> -#define PCIE_LUT_BASE 0x80000
> -#define PCIE_LUT_LCTRL0 0x7F8
> -#define PCIE_LUT_DBG 0x7FC
> -#define PCIE_LUT_UDR(n) (0x800 + (n) * 8)
> -#define PCIE_LUT_LDR(n) (0x804 + (n) * 8)
> -#define PCIE_LUT_ENABLE (1 << 31)
> -#define PCIE_LUT_ENTRY_COUNT 32
>
[snip]
Regards,
Bin
^ permalink raw reply [flat|nested] 26+ messages in thread
* [U-Boot] [PATCH 2/9] dm: pci: remove pci_bus_to_hose(0) calling
2016-10-10 8:47 ` [U-Boot] [PATCH 2/9] dm: pci: remove pci_bus_to_hose(0) calling Minghuan Lian
@ 2016-10-10 11:54 ` Bin Meng
2016-10-11 7:26 ` M.H. Lian
0 siblings, 1 reply; 26+ messages in thread
From: Bin Meng @ 2016-10-10 11:54 UTC (permalink / raw)
To: u-boot
+Simon
Hi Minghuan,
On Mon, Oct 10, 2016 at 4:47 PM, Minghuan Lian <Minghuan.Lian@nxp.com> wrote:
> There may be multiple PCIe controllers in a SoC.
> It is not correct that always calling pci_bus_to_hose(0) to get
> the first PCIe controller for the PCIe device connected other
> controllers. We just remove this calling because hose always point
> the correct PCIe controller.
>
> Signed-off-by: Minghuan Lian <Minghuan.Lian@nxp.com>
> ---
> drivers/pci/pci_common.c | 10 ----------
> 1 file changed, 10 deletions(-)
>
> diff --git a/drivers/pci/pci_common.c b/drivers/pci/pci_common.c
> index 1755914..448e814 100644
> --- a/drivers/pci/pci_common.c
> +++ b/drivers/pci/pci_common.c
> @@ -181,11 +181,6 @@ phys_addr_t pci_hose_bus_to_phys(struct pci_controller *hose,
> return phys_addr;
> }
>
> -#ifdef CONFIG_DM_PCI
> - /* The root controller has the region information */
> - hose = pci_bus_to_hose(0);
> -#endif
Again if you fully convert the driver to use DM PCI, this API won't be
called. And what's broken here? The comment says "The root controller
has the region information", which is correct.
> -
> /*
> * if PCI_REGION_MEM is set we do a two pass search with preference
> * on matches that don't have PCI_REGION_SYS_MEMORY set
> @@ -248,11 +243,6 @@ pci_addr_t pci_hose_phys_to_bus(struct pci_controller *hose,
> return bus_addr;
> }
>
> -#ifdef CONFIG_DM_PCI
> - /* The root controller has the region information */
> - hose = pci_bus_to_hose(0);
> -#endif
> -
> /*
> * if PCI_REGION_MEM is set we do a two pass search with preference
> * on matches that don't have PCI_REGION_SYS_MEMORY set
> --
Regards,
Bin
^ permalink raw reply [flat|nested] 26+ messages in thread
* [U-Boot] [PATCH 1/9] dm: pci: return the real controller in pci_bus_to_hose()
2016-10-10 10:37 ` Bin Meng
@ 2016-10-11 7:12 ` M.H. Lian
2016-10-11 7:43 ` Bin Meng
0 siblings, 1 reply; 26+ messages in thread
From: M.H. Lian @ 2016-10-11 7:12 UTC (permalink / raw)
To: u-boot
Hi Bin,
With the patches our Layerscape PCIe driver has been fully based on DM.
Ethernet driver E1000 needs to define "CONFIG_DM_ETH" to use PCIe DM API instead of legacy PCI API.
But our other Ethernet driver FM(drivers/net/fm/eth.c) is still not support DM. So we cannot define "CONFIG_DM_ETH"
Well, we must define "CONFIG_DM_PCI_COMPAT" to support e1000 and fm at the same time.
After FM driver is changed to support DM, we can define "CONFIG_DM_ETH" and remove "CONFIG_DM_PCI_COMPAT "
But the current DM driver has an issue.
1.
pci_bus_to_hose(int busnum) defined in driver/pci/pci_compat.c is to return the hose associated current busnum(PCIe device) instead of PCIe controller (RC)
pci_bus_to_hose(int bus) defined in driver/pci/pci.c for legacy PCI driver is to return the hose pointed to the PCIe controller(RC).
My first patch is to keep consistency and return the hose pointer of the PCIe controller.
- return dev_get_uclass_priv(bus);
+ return dev_get_uclass_priv(pci_get_controller(bus));
2
In pci/pci_common.c phys_addr_t pci_hose_bus_to_phys()
#ifdef CONFIG_DM_PCI
/* The root controller has the region information */
hose = pci_bus_to_hose(0);
#endif
Is always to return hose of the bus0.
But our SoC has more than one PCIe controllers(RC).
For example:
PCI0 bus 0 -- e1000#0 bus1
PCI1 bus 2 -- e1000#1 bus3.
PCI1 is the second PCIe controller (RC) has different PCIe space to PCI0.
For E1000#1, we want to get the host pointed to PCI1 bus2 not bus0.
Thanks,
Minghuan
> -----Original Message-----
> From: Bin Meng [mailto:bmeng.cn at gmail.com]
> Sent: Monday, October 10, 2016 6:38 PM
> To: M.H. Lian <minghuan.lian@nxp.com>
> Cc: Simon Glass <sjg@chromium.org>; U-Boot Mailing List <u-
> boot at lists.denx.de>; Mingkai Hu <mingkai.hu@nxp.com>; Leo Li
> <leoyang.li@nxp.com>
> Subject: Re: [U-Boot] [PATCH 1/9] dm: pci: return the real controller in
> pci_bus_to_hose()
>
> Hi Minghuan,
>
> On Mon, Oct 10, 2016 at 5:09 PM, M.H. Lian <minghuan.lian@nxp.com>
> wrote:
> > Hi Bin?
> >
> > Thanks for your comments.
> >
> > The series of patches is to change legacy PCIe driver to DM PCIe driver.
> > The first two patches are to change DM to support multiple PCIe controllers.
>
> I don't understand what is broken. If you fully convert the driver to DM PCI, I
> don't think we need ever touch the pci_compat codes. Could you please
> elaborate more?
>
> > The 8th patch is to change Layerscape PCIe driver based on DM Other
> > patches are to add PCIe dts node for five SoCs.
> >
> > Thanks,
> > Minghuan
> >
>
> Regards,
> Bin
^ permalink raw reply [flat|nested] 26+ messages in thread
* [U-Boot] [PATCH 9/9] armv8: ls1046a: Enable PCIe support
2016-10-10 11:41 ` Bin Meng
@ 2016-10-11 7:14 ` M.H. Lian
0 siblings, 0 replies; 26+ messages in thread
From: M.H. Lian @ 2016-10-11 7:14 UTC (permalink / raw)
To: u-boot
Hi Bin,
Please see my comment inline.
Thanks,
Minghuan
> -----Original Message-----
> From: Bin Meng [mailto:bmeng.cn at gmail.com]
> Sent: Monday, October 10, 2016 7:42 PM
> To: M.H. Lian <minghuan.lian@nxp.com>
> Cc: U-Boot Mailing List <u-boot@lists.denx.de>; Mingkai Hu
> <mingkai.hu@nxp.com>; Leo Li <leoyang.li@nxp.com>
> Subject: Re: [U-Boot] [PATCH 9/9] armv8: ls1046a: Enable PCIe support
>
> Hi Minghuan,
>
> On Mon, Oct 10, 2016 at 4:47 PM, Minghuan Lian <Minghuan.Lian@nxp.com>
> wrote:
> > Signed-off-by: Minghuan Lian <Minghuan.Lian@nxp.com>
> > ---
> > include/configs/ls1046a_common.h | 15 +++++++++++++++
> > 1 file changed, 15 insertions(+)
> >
> > diff --git a/include/configs/ls1046a_common.h
> > b/include/configs/ls1046a_common.h
> > index 7c5e635..f8f5ee2 100644
> > --- a/include/configs/ls1046a_common.h
> > +++ b/include/configs/ls1046a_common.h
> > @@ -117,6 +117,21 @@
> > #define CONFIG_SYS_I2C_MXC_I2C3
> > #define CONFIG_SYS_I2C_MXC_I2C4
> >
> > +/* PCIe */
> > +#define CONFIG_PCI /* Enable PCI/PCIE */
> > +#define CONFIG_DM_PCI /* Enable driver mode for PCI */
> > +#define CONFIG_DM_PCI_COMPAT
> > +#define CONFIG_PCIE_LAYERSCAPE /* Use common FSL Layerscape PCIe
> code
> > +*/ #define CONFIG_SYS_PCI_64BIT
>
> Please do not add any Kconfig option in the header file any more.
> These already converted Kconfig options should be moved to boards'
> defconfig files.
[Minghuan Lian] Ok. I will move them to defconfig files.
>
> > +
> > +#ifdef CONFIG_PCI
> > +#define CONFIG_PCI_PNP
> > +#define CONFIG_PCI_SCAN_SHOW
> > +#define CONFIG_CMD_PCI
> > +#define CONFIG_NET_MULTI
> > +#define CONFIG_E1000
> > +#endif
> > +
> > /* Command line configuration */
> > #define CONFIG_CMD_ENV
> >
> > --
>
> Regards,
> Bin
^ permalink raw reply [flat|nested] 26+ messages in thread
* [U-Boot] [PATCH 8/9] pci: layerscape: rewrite pci driver based on DM
2016-10-10 11:49 ` Bin Meng
@ 2016-10-11 7:21 ` M.H. Lian
2016-10-11 7:28 ` Bin Meng
0 siblings, 1 reply; 26+ messages in thread
From: M.H. Lian @ 2016-10-11 7:21 UTC (permalink / raw)
To: u-boot
Hi Bin,
Thanks for your suggestion.
Please see my comments inline.
Thanks,
Minghuan
> -----Original Message-----
> From: Bin Meng [mailto:bmeng.cn at gmail.com]
> Sent: Monday, October 10, 2016 7:49 PM
> To: M.H. Lian <minghuan.lian@nxp.com>; Simon Glass <sjg@chromium.org>
> Cc: U-Boot Mailing List <u-boot@lists.denx.de>; Mingkai Hu
> <mingkai.hu@nxp.com>; Leo Li <leoyang.li@nxp.com>
> Subject: Re: [U-Boot] [PATCH 8/9] pci: layerscape: rewrite pci driver based on
> DM
>
> Hi Minghuan,
>
> On Mon, Oct 10, 2016 at 4:47 PM, Minghuan Lian <Minghuan.Lian@nxp.com>
> wrote:
> > There are more than five kinds of Layerscape SoCs. unfortunately, PCIe
> > controller of each SoC is a little bit different. In order to avoid
> > too many macro definitions, the patch re-implement PCIe driver based
> > on DM. PCIe dts node is to describe the difference.
> >
> > Signed-off-by: Minghuan Lian <Minghuan.Lian@nxp.com>
> > ---
> > .../include/asm/arch-fsl-layerscape/immap_lsch3.h | 8 -
> > drivers/pci/Kconfig | 8 +
> > drivers/pci/pcie_layerscape.c | 958 +++++++++++----------
> > include/configs/ls1012a_common.h | 12 +
> > include/configs/ls1012aqds.h | 24 -
> > include/configs/ls1012ardb.h | 24 -
> > include/configs/ls1021aqds.h | 18 +-
> > include/configs/ls1021atwr.h | 18 +-
> > include/configs/ls1043a_common.h | 23 +-
> > include/configs/ls2080a_common.h | 27 +-
> > include/configs/ls2080aqds.h | 8 -
> > include/configs/ls2080ardb.h | 8 -
>
> These header file changes should not be put in the same commit of the
> layerscape PCIe driver conversion. They should be in a separate commit. So
> you are likely to have 3 commits: firstly add DM codes with #ifdef
> CONFIG_DM_PCI #endif in the layerscape PCIe driver, without breaking the
> existing board support. 2nd commit to update the boards configuration files
> (defconfig and the header), and 3rd commit to remove the #ifdef
> CONFIG_DM_PCI #endif, only leaving the DM version codes.
[Minghuan Lian] Your suggestion is excellent. I will change the patch.
For the header and defconfig files, do I need to separate them to several patches for different SoC?
I mean a patch is for ls1012, a patch is for ls1043 ...
>
> > 12 files changed, 526 insertions(+), 610 deletions(-)
> >
> > diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
> > b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
> > index 7acba27..bd07808 100644
> > --- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
> > +++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
> > @@ -104,14 +104,6 @@
> > #define CONFIG_SYS_PCIE2_PHYS_ADDR 0x1200000000ULL
> > #define CONFIG_SYS_PCIE3_PHYS_ADDR 0x1400000000ULL
> > #define CONFIG_SYS_PCIE4_PHYS_ADDR 0x1600000000ULL
> > -/* LUT registers */
> > -#define PCIE_LUT_BASE 0x80000
> > -#define PCIE_LUT_LCTRL0 0x7F8
> > -#define PCIE_LUT_DBG 0x7FC
> > -#define PCIE_LUT_UDR(n) (0x800 + (n) * 8)
> > -#define PCIE_LUT_LDR(n) (0x804 + (n) * 8)
> > -#define PCIE_LUT_ENABLE (1 << 31)
> > -#define PCIE_LUT_ENTRY_COUNT 32
> >
>
> [snip]
>
> Regards,
> Bin
^ permalink raw reply [flat|nested] 26+ messages in thread
* [U-Boot] [PATCH 2/9] dm: pci: remove pci_bus_to_hose(0) calling
2016-10-10 11:54 ` Bin Meng
@ 2016-10-11 7:26 ` M.H. Lian
0 siblings, 0 replies; 26+ messages in thread
From: M.H. Lian @ 2016-10-11 7:26 UTC (permalink / raw)
To: u-boot
Hi Bin,
Please see my comments inline.
Thanks,
Minghuan
> -----Original Message-----
> From: Bin Meng [mailto:bmeng.cn at gmail.com]
> Sent: Monday, October 10, 2016 7:55 PM
> To: M.H. Lian <minghuan.lian@nxp.com>; Simon Glass <sjg@chromium.org>
> Cc: U-Boot Mailing List <u-boot@lists.denx.de>; Mingkai Hu
> <mingkai.hu@nxp.com>; Leo Li <leoyang.li@nxp.com>
> Subject: Re: [U-Boot] [PATCH 2/9] dm: pci: remove pci_bus_to_hose(0)
> calling
>
> +Simon
>
> Hi Minghuan,
>
> On Mon, Oct 10, 2016 at 4:47 PM, Minghuan Lian <Minghuan.Lian@nxp.com>
> wrote:
> > There may be multiple PCIe controllers in a SoC.
> > It is not correct that always calling pci_bus_to_hose(0) to get the
> > first PCIe controller for the PCIe device connected other controllers.
> > We just remove this calling because hose always point the correct PCIe
> > controller.
> >
> > Signed-off-by: Minghuan Lian <Minghuan.Lian@nxp.com>
> > ---
> > drivers/pci/pci_common.c | 10 ----------
> > 1 file changed, 10 deletions(-)
> >
> > diff --git a/drivers/pci/pci_common.c b/drivers/pci/pci_common.c index
> > 1755914..448e814 100644
> > --- a/drivers/pci/pci_common.c
> > +++ b/drivers/pci/pci_common.c
> > @@ -181,11 +181,6 @@ phys_addr_t pci_hose_bus_to_phys(struct
> pci_controller *hose,
> > return phys_addr;
> > }
> >
> > -#ifdef CONFIG_DM_PCI
> > - /* The root controller has the region information */
> > - hose = pci_bus_to_hose(0);
> > -#endif
>
> Again if you fully convert the driver to use DM PCI, this API won't be called.
> And what's broken here? The comment says "The root controller has the
> region information", which is correct.
[Minghuan Lian] Our SoCs have multiple PCIe controllers - RCs.
Each PCIe controller has different region information.
Only the first PCIe controller is assigned to bus number 0.
The second/third PCIe controllers may be assigned bus number 2 / 3.
pci_bus_to_hose(0) is only correct for the first PCIe controller.
>
> > -
> > /*
> > * if PCI_REGION_MEM is set we do a two pass search with preference
> > * on matches that don't have PCI_REGION_SYS_MEMORY set @@
> > -248,11 +243,6 @@ pci_addr_t pci_hose_phys_to_bus(struct pci_controller
> *hose,
> > return bus_addr;
> > }
> >
> > -#ifdef CONFIG_DM_PCI
> > - /* The root controller has the region information */
> > - hose = pci_bus_to_hose(0);
> > -#endif
> > -
> > /*
> > * if PCI_REGION_MEM is set we do a two pass search with preference
> > * on matches that don't have PCI_REGION_SYS_MEMORY set
> > --
>
> Regards,
> Bin
^ permalink raw reply [flat|nested] 26+ messages in thread
* [U-Boot] [PATCH 8/9] pci: layerscape: rewrite pci driver based on DM
2016-10-11 7:21 ` M.H. Lian
@ 2016-10-11 7:28 ` Bin Meng
0 siblings, 0 replies; 26+ messages in thread
From: Bin Meng @ 2016-10-11 7:28 UTC (permalink / raw)
To: u-boot
Hi Minghuan,
On Tue, Oct 11, 2016 at 3:21 PM, M.H. Lian <minghuan.lian@nxp.com> wrote:
> Hi Bin,
>
> Thanks for your suggestion.
> Please see my comments inline.
>
> Thanks,
> Minghuan
>
>> -----Original Message-----
>> From: Bin Meng [mailto:bmeng.cn at gmail.com]
>> Sent: Monday, October 10, 2016 7:49 PM
>> To: M.H. Lian <minghuan.lian@nxp.com>; Simon Glass <sjg@chromium.org>
>> Cc: U-Boot Mailing List <u-boot@lists.denx.de>; Mingkai Hu
>> <mingkai.hu@nxp.com>; Leo Li <leoyang.li@nxp.com>
>> Subject: Re: [U-Boot] [PATCH 8/9] pci: layerscape: rewrite pci driver based on
>> DM
>>
>> Hi Minghuan,
>>
>> On Mon, Oct 10, 2016 at 4:47 PM, Minghuan Lian <Minghuan.Lian@nxp.com>
>> wrote:
>> > There are more than five kinds of Layerscape SoCs. unfortunately, PCIe
>> > controller of each SoC is a little bit different. In order to avoid
>> > too many macro definitions, the patch re-implement PCIe driver based
>> > on DM. PCIe dts node is to describe the difference.
>> >
>> > Signed-off-by: Minghuan Lian <Minghuan.Lian@nxp.com>
>> > ---
>> > .../include/asm/arch-fsl-layerscape/immap_lsch3.h | 8 -
>> > drivers/pci/Kconfig | 8 +
>> > drivers/pci/pcie_layerscape.c | 958 +++++++++++----------
>> > include/configs/ls1012a_common.h | 12 +
>> > include/configs/ls1012aqds.h | 24 -
>> > include/configs/ls1012ardb.h | 24 -
>> > include/configs/ls1021aqds.h | 18 +-
>> > include/configs/ls1021atwr.h | 18 +-
>> > include/configs/ls1043a_common.h | 23 +-
>> > include/configs/ls2080a_common.h | 27 +-
>> > include/configs/ls2080aqds.h | 8 -
>> > include/configs/ls2080ardb.h | 8 -
>>
>> These header file changes should not be put in the same commit of the
>> layerscape PCIe driver conversion. They should be in a separate commit. So
>> you are likely to have 3 commits: firstly add DM codes with #ifdef
>> CONFIG_DM_PCI #endif in the layerscape PCIe driver, without breaking the
>> existing board support. 2nd commit to update the boards configuration files
>> (defconfig and the header), and 3rd commit to remove the #ifdef
>> CONFIG_DM_PCI #endif, only leaving the DM version codes.
>
> [Minghuan Lian] Your suggestion is excellent. I will change the patch.
> For the header and defconfig files, do I need to separate them to several patches for different SoC?
> I mean a patch is for ls1012, a patch is for ls1043 ...
It depends on how you organize your patch series. We should make every
commit bisectable, eg: the commit itself does not break build or any
functionality. If all SoC header files need to change all together, it
should be in one patch. Otherwise, you can put them into separate
patch.
Regards,
Bin
^ permalink raw reply [flat|nested] 26+ messages in thread
* [U-Boot] [PATCH 1/9] dm: pci: return the real controller in pci_bus_to_hose()
2016-10-11 7:12 ` M.H. Lian
@ 2016-10-11 7:43 ` Bin Meng
2016-10-11 9:36 ` M.H. Lian
0 siblings, 1 reply; 26+ messages in thread
From: Bin Meng @ 2016-10-11 7:43 UTC (permalink / raw)
To: u-boot
Hi Minghuan,
On Tue, Oct 11, 2016 at 3:12 PM, M.H. Lian <minghuan.lian@nxp.com> wrote:
> Hi Bin,
>
> With the patches our Layerscape PCIe driver has been fully based on DM.
> Ethernet driver E1000 needs to define "CONFIG_DM_ETH" to use PCIe DM API instead of legacy PCI API.
> But our other Ethernet driver FM(drivers/net/fm/eth.c) is still not support DM. So we cannot define "CONFIG_DM_ETH"
For LS1021a ethernet, please pick up this patch to see if it works:
http://patchwork.ozlabs.org/patch/566347/
> Well, we must define "CONFIG_DM_PCI_COMPAT" to support e1000 and fm at the same time.
> After FM driver is changed to support DM, we can define "CONFIG_DM_ETH" and remove "CONFIG_DM_PCI_COMPAT "
>
> But the current DM driver has an issue.
>
> 1.
> pci_bus_to_hose(int busnum) defined in driver/pci/pci_compat.c is to return the hose associated current busnum(PCIe device) instead of PCIe controller (RC)
>
> pci_bus_to_hose(int bus) defined in driver/pci/pci.c for legacy PCI driver is to return the hose pointed to the PCIe controller(RC).
>
> My first patch is to keep consistency and return the hose pointer of the PCIe controller.
> - return dev_get_uclass_priv(bus);
> + return dev_get_uclass_priv(pci_get_controller(bus));
>
> 2
> In pci/pci_common.c phys_addr_t pci_hose_bus_to_phys()
>
> #ifdef CONFIG_DM_PCI
> /* The root controller has the region information */
> hose = pci_bus_to_hose(0);
> #endif
>
> Is always to return hose of the bus0.
>
> But our SoC has more than one PCIe controllers(RC).
>
> For example:
> PCI0 bus 0 -- e1000#0 bus1
> PCI1 bus 2 -- e1000#1 bus3.
I got it. But this does not look that good to me. There are two
controllers, and bus number should be relative to the controller
itself, not system wide. It's definitely right to assign bus number 0
to both PCIe host controllers, as they forward the bus number on their
own bus link. I am wondering we should add a controller number to the
PCI command, like the storage device command. The first parameter is
the controller number, while the second parameter is the bus number.
>
> PCI1 is the second PCIe controller (RC) has different PCIe space to PCI0.
> For E1000#1, we want to get the host pointed to PCI1 bus2 not bus0.
>
Regards,
Bin
^ permalink raw reply [flat|nested] 26+ messages in thread
* [U-Boot] [PATCH 1/9] dm: pci: return the real controller in pci_bus_to_hose()
2016-10-11 7:43 ` Bin Meng
@ 2016-10-11 9:36 ` M.H. Lian
2016-10-11 10:35 ` Bin Meng
2016-11-07 18:13 ` york sun
0 siblings, 2 replies; 26+ messages in thread
From: M.H. Lian @ 2016-10-11 9:36 UTC (permalink / raw)
To: u-boot
Hi Bin,
Please see my comments inline.
Thanks,
Minghuan
> -----Original Message-----
> From: Bin Meng [mailto:bmeng.cn at gmail.com]
> Sent: Tuesday, October 11, 2016 3:43 PM
> To: M.H. Lian <minghuan.lian@nxp.com>
> Cc: Simon Glass <sjg@chromium.org>; U-Boot Mailing List <u-
> boot at lists.denx.de>; Mingkai Hu <mingkai.hu@nxp.com>; Leo Li
> <leoyang.li@nxp.com>
> Subject: Re: [U-Boot] [PATCH 1/9] dm: pci: return the real controller in
> pci_bus_to_hose()
>
> Hi Minghuan,
>
> On Tue, Oct 11, 2016 at 3:12 PM, M.H. Lian <minghuan.lian@nxp.com> wrote:
> > Hi Bin,
> >
> > With the patches our Layerscape PCIe driver has been fully based on DM.
> > Ethernet driver E1000 needs to define "CONFIG_DM_ETH" to use PCIe DM
> API instead of legacy PCI API.
> > But our other Ethernet driver FM(drivers/net/fm/eth.c) is still not support
> DM. So we cannot define "CONFIG_DM_ETH"
>
> For LS1021a ethernet, please pick up this patch to see if it works:
> http://patchwork.ozlabs.org/patch/566347/
[Minghuan Lian] fm.c is used by ls1043 and ls1046. So if this patch is merged, I may remove " CONFIG_DM_PCI_COMPAT "
On LS1021a.
>
> > Well, we must define "CONFIG_DM_PCI_COMPAT" to support e1000 and
> fm at the same time.
> > After FM driver is changed to support DM, we can define
> "CONFIG_DM_ETH" and remove "CONFIG_DM_PCI_COMPAT "
> >
> > But the current DM driver has an issue.
> >
> > 1.
> > pci_bus_to_hose(int busnum) defined in driver/pci/pci_compat.c is
> > to return the hose associated current busnum(PCIe device) instead of
> > PCIe controller (RC)
> >
> > pci_bus_to_hose(int bus) defined in driver/pci/pci.c for legacy PCI driver is
> to return the hose pointed to the PCIe controller(RC).
> >
> > My first patch is to keep consistency and return the hose pointer of the
> PCIe controller.
> > - return dev_get_uclass_priv(bus);
> > + return dev_get_uclass_priv(pci_get_controller(bus));
> >
> > 2
> > In pci/pci_common.c phys_addr_t pci_hose_bus_to_phys()
> >
> > #ifdef CONFIG_DM_PCI
> > /* The root controller has the region information */
> > hose = pci_bus_to_hose(0);
> > #endif
> >
> > Is always to return hose of the bus0.
> >
> > But our SoC has more than one PCIe controllers(RC).
> >
> > For example:
> > PCI0 bus 0 -- e1000#0 bus1
> > PCI1 bus 2 -- e1000#1 bus3.
>
> I got it. But this does not look that good to me. There are two controllers, and
> bus number should be relative to the controller itself, not system wide. It's
> definitely right to assign bus number 0 to both PCIe host controllers, as they
> forward the bus number on their own bus link. I am wondering we should
> add a controller number to the PCI command, like the storage device
> command. The first parameter is the controller number, while the second
> parameter is the bus number.
[Minghuan Lian] Yes. Linux uses "PCI domain" to isolate PCIe controllers.
And config "CONFIG_PCI_DOMAINS" is to enable domain like controllers number.
But, under Linux if disable "CONFIG_PCI_DOMAINS ", all PCIe controllers will be assigned continuous bus
Number like the current uboot.
>
> >
> > PCI1 is the second PCIe controller (RC) has different PCIe space to PCI0.
> > For E1000#1, we want to get the host pointed to PCI1 bus2 not bus0.
> >
>
> Regards,
> Bin
^ permalink raw reply [flat|nested] 26+ messages in thread
* [U-Boot] [PATCH 1/9] dm: pci: return the real controller in pci_bus_to_hose()
2016-10-11 9:36 ` M.H. Lian
@ 2016-10-11 10:35 ` Bin Meng
2016-10-11 11:01 ` M.H. Lian
2016-11-07 18:13 ` york sun
1 sibling, 1 reply; 26+ messages in thread
From: Bin Meng @ 2016-10-11 10:35 UTC (permalink / raw)
To: u-boot
Hi Minghuan,
On Tue, Oct 11, 2016 at 5:36 PM, M.H. Lian <minghuan.lian@nxp.com> wrote:
> Hi Bin,
>
> Please see my comments inline.
>
> Thanks,
> Minghuan
>
>> -----Original Message-----
>> From: Bin Meng [mailto:bmeng.cn at gmail.com]
>> Sent: Tuesday, October 11, 2016 3:43 PM
>> To: M.H. Lian <minghuan.lian@nxp.com>
>> Cc: Simon Glass <sjg@chromium.org>; U-Boot Mailing List <u-
>> boot at lists.denx.de>; Mingkai Hu <mingkai.hu@nxp.com>; Leo Li
>> <leoyang.li@nxp.com>
>> Subject: Re: [U-Boot] [PATCH 1/9] dm: pci: return the real controller in
>> pci_bus_to_hose()
>>
>> Hi Minghuan,
>>
>> On Tue, Oct 11, 2016 at 3:12 PM, M.H. Lian <minghuan.lian@nxp.com> wrote:
>> > Hi Bin,
>> >
>> > With the patches our Layerscape PCIe driver has been fully based on DM.
>> > Ethernet driver E1000 needs to define "CONFIG_DM_ETH" to use PCIe DM
>> API instead of legacy PCI API.
>> > But our other Ethernet driver FM(drivers/net/fm/eth.c) is still not support
>> DM. So we cannot define "CONFIG_DM_ETH"
>>
>> For LS1021a ethernet, please pick up this patch to see if it works:
>> http://patchwork.ozlabs.org/patch/566347/
> [Minghuan Lian] fm.c is used by ls1043 and ls1046. So if this patch is merged, I may remove " CONFIG_DM_PCI_COMPAT "
> On LS1021a.
>>
Yep, I think so.
>> > Well, we must define "CONFIG_DM_PCI_COMPAT" to support e1000 and
>> fm at the same time.
>> > After FM driver is changed to support DM, we can define
>> "CONFIG_DM_ETH" and remove "CONFIG_DM_PCI_COMPAT "
>> >
>> > But the current DM driver has an issue.
>> >
>> > 1.
>> > pci_bus_to_hose(int busnum) defined in driver/pci/pci_compat.c is
>> > to return the hose associated current busnum(PCIe device) instead of
>> > PCIe controller (RC)
>> >
>> > pci_bus_to_hose(int bus) defined in driver/pci/pci.c for legacy PCI driver is
>> to return the hose pointed to the PCIe controller(RC).
>> >
>> > My first patch is to keep consistency and return the hose pointer of the
>> PCIe controller.
>> > - return dev_get_uclass_priv(bus);
>> > + return dev_get_uclass_priv(pci_get_controller(bus));
>> >
>> > 2
>> > In pci/pci_common.c phys_addr_t pci_hose_bus_to_phys()
>> >
>> > #ifdef CONFIG_DM_PCI
>> > /* The root controller has the region information */
>> > hose = pci_bus_to_hose(0);
>> > #endif
>> >
>> > Is always to return hose of the bus0.
>> >
>> > But our SoC has more than one PCIe controllers(RC).
>> >
>> > For example:
>> > PCI0 bus 0 -- e1000#0 bus1
>> > PCI1 bus 2 -- e1000#1 bus3.
>>
>> I got it. But this does not look that good to me. There are two controllers, and
>> bus number should be relative to the controller itself, not system wide. It's
>> definitely right to assign bus number 0 to both PCIe host controllers, as they
>> forward the bus number on their own bus link. I am wondering we should
>> add a controller number to the PCI command, like the storage device
>> command. The first parameter is the controller number, while the second
>> parameter is the bus number.
> [Minghuan Lian] Yes. Linux uses "PCI domain" to isolate PCIe controllers.
> And config "CONFIG_PCI_DOMAINS" is to enable domain like controllers number.
> But, under Linux if disable "CONFIG_PCI_DOMAINS ", all PCIe controllers will be assigned continuous bus
> Number like the current uboot.
>
Yep, I guess you will need introduce CONFIG_PCI_DOMAINS to U-Boot DM PCI codes.
Regards,
Bin
^ permalink raw reply [flat|nested] 26+ messages in thread
* [U-Boot] [PATCH 1/9] dm: pci: return the real controller in pci_bus_to_hose()
2016-10-11 10:35 ` Bin Meng
@ 2016-10-11 11:01 ` M.H. Lian
0 siblings, 0 replies; 26+ messages in thread
From: M.H. Lian @ 2016-10-11 11:01 UTC (permalink / raw)
To: u-boot
Hi Bin,
I noticed Sandbox architecture has added PCI menu to the arch/sandbox/Kconfig
Could I move this PCI menu to the driver/pci/kconfig?
So I could add all PCI related config to defconfig files.
Please see my comments inline.
Thanks,
Minghuan
> -----Original Message-----
> From: Bin Meng [mailto:bmeng.cn at gmail.com]
> Sent: Tuesday, October 11, 2016 6:35 PM
> To: M.H. Lian <minghuan.lian@nxp.com>
> Cc: Simon Glass <sjg@chromium.org>; U-Boot Mailing List <u-
> boot at lists.denx.de>; Mingkai Hu <mingkai.hu@nxp.com>; Leo Li
> <leoyang.li@nxp.com>
> Subject: Re: [U-Boot] [PATCH 1/9] dm: pci: return the real controller in
> pci_bus_to_hose()
>
> Hi Minghuan,
>
> On Tue, Oct 11, 2016 at 5:36 PM, M.H. Lian <minghuan.lian@nxp.com> wrote:
> > Hi Bin,
> >
> > Please see my comments inline.
> >
> > Thanks,
> > Minghuan
> >
> >> -----Original Message-----
> >> From: Bin Meng [mailto:bmeng.cn at gmail.com]
> >> Sent: Tuesday, October 11, 2016 3:43 PM
> >> To: M.H. Lian <minghuan.lian@nxp.com>
> >> Cc: Simon Glass <sjg@chromium.org>; U-Boot Mailing List <u-
> >> boot at lists.denx.de>; Mingkai Hu <mingkai.hu@nxp.com>; Leo Li
> >> <leoyang.li@nxp.com>
> >> Subject: Re: [U-Boot] [PATCH 1/9] dm: pci: return the real controller
> >> in
> >> pci_bus_to_hose()
> >>
> >> Hi Minghuan,
> >>
> >> On Tue, Oct 11, 2016 at 3:12 PM, M.H. Lian <minghuan.lian@nxp.com>
> wrote:
> >> > Hi Bin,
> >> >
> >> > With the patches our Layerscape PCIe driver has been fully based on
> DM.
> >> > Ethernet driver E1000 needs to define "CONFIG_DM_ETH" to use PCIe
> >> > DM
> >> API instead of legacy PCI API.
> >> > But our other Ethernet driver FM(drivers/net/fm/eth.c) is still not
> >> > support
> >> DM. So we cannot define "CONFIG_DM_ETH"
> >>
> >> For LS1021a ethernet, please pick up this patch to see if it works:
> >> http://patchwork.ozlabs.org/patch/566347/
> > [Minghuan Lian] fm.c is used by ls1043 and ls1046. So if this patch is merged,
> I may remove " CONFIG_DM_PCI_COMPAT "
> > On LS1021a.
> >>
>
> Yep, I think so.
>
> >> > Well, we must define "CONFIG_DM_PCI_COMPAT" to support e1000
> and
> >> fm at the same time.
> >> > After FM driver is changed to support DM, we can define
> >> "CONFIG_DM_ETH" and remove "CONFIG_DM_PCI_COMPAT "
> >> >
> >> > But the current DM driver has an issue.
> >> >
> >> > 1.
> >> > pci_bus_to_hose(int busnum) defined in driver/pci/pci_compat.c
> >> > is to return the hose associated current busnum(PCIe device)
> >> > instead of PCIe controller (RC)
> >> >
> >> > pci_bus_to_hose(int bus) defined in driver/pci/pci.c for legacy PCI
> >> > driver is
> >> to return the hose pointed to the PCIe controller(RC).
> >> >
> >> > My first patch is to keep consistency and return the hose pointer
> >> > of the
> >> PCIe controller.
> >> > - return dev_get_uclass_priv(bus);
> >> > + return dev_get_uclass_priv(pci_get_controller(bus));
> >> >
> >> > 2
> >> > In pci/pci_common.c phys_addr_t pci_hose_bus_to_phys()
> >> >
> >> > #ifdef CONFIG_DM_PCI
> >> > /* The root controller has the region information */
> >> > hose = pci_bus_to_hose(0);
> >> > #endif
> >> >
> >> > Is always to return hose of the bus0.
> >> >
> >> > But our SoC has more than one PCIe controllers(RC).
> >> >
> >> > For example:
> >> > PCI0 bus 0 -- e1000#0 bus1
> >> > PCI1 bus 2 -- e1000#1 bus3.
> >>
> >> I got it. But this does not look that good to me. There are two
> >> controllers, and bus number should be relative to the controller
> >> itself, not system wide. It's definitely right to assign bus number 0
> >> to both PCIe host controllers, as they forward the bus number on
> >> their own bus link. I am wondering we should add a controller number
> >> to the PCI command, like the storage device command. The first
> >> parameter is the controller number, while the second parameter is the
> bus number.
> > [Minghuan Lian] Yes. Linux uses "PCI domain" to isolate PCIe controllers.
> > And config "CONFIG_PCI_DOMAINS" is to enable domain like controllers
> number.
> > But, under Linux if disable "CONFIG_PCI_DOMAINS ", all PCIe
> > controllers will be assigned continuous bus Number like the current uboot.
> >
>
> Yep, I guess you will need introduce CONFIG_PCI_DOMAINS to U-Boot DM
> PCI codes.
>
[Minghuan Lian] For Linux, "DOMAINS" is an option, not a must.
And we need to change many PCIe code carefully to compatible with all PCIe driver.
It will take plenty of time. And there are still very pressing jobs on hand. So I will add this to my todo list.
> Regards,
> Bin
^ permalink raw reply [flat|nested] 26+ messages in thread
* [U-Boot] [PATCH 1/9] dm: pci: return the real controller in pci_bus_to_hose()
2016-10-11 9:36 ` M.H. Lian
2016-10-11 10:35 ` Bin Meng
@ 2016-11-07 18:13 ` york sun
1 sibling, 0 replies; 26+ messages in thread
From: york sun @ 2016-11-07 18:13 UTC (permalink / raw)
To: u-boot
On 10/11/2016 07:11 AM, M.H. Lian wrote:
>>
>> I got it. But this does not look that good to me. There are two controllers, and
>> bus number should be relative to the controller itself, not system wide. It's
>> definitely right to assign bus number 0 to both PCIe host controllers, as they
>> forward the bus number on their own bus link. I am wondering we should
>> add a controller number to the PCI command, like the storage device
>> command. The first parameter is the controller number, while the second
>> parameter is the bus number.
> [Minghuan Lian] Yes. Linux uses "PCI domain" to isolate PCIe controllers.
> And config "CONFIG_PCI_DOMAINS" is to enable domain like controllers number.
> But, under Linux if disable "CONFIG_PCI_DOMAINS ", all PCIe controllers will be assigned continuous bus
> Number like the current uboot.
>
Where are we on this set?
York
^ permalink raw reply [flat|nested] 26+ messages in thread
end of thread, other threads:[~2016-11-07 18:13 UTC | newest]
Thread overview: 26+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2016-10-10 8:47 [U-Boot] [PATCH 1/9] dm: pci: return the real controller in pci_bus_to_hose() Minghuan Lian
2016-10-10 8:47 ` [U-Boot] [PATCH 2/9] dm: pci: remove pci_bus_to_hose(0) calling Minghuan Lian
2016-10-10 11:54 ` Bin Meng
2016-10-11 7:26 ` M.H. Lian
2016-10-10 8:47 ` [U-Boot] [PATCH 3/9] arm: ls1021a: add PCIe dts node Minghuan Lian
2016-10-10 8:47 ` [U-Boot] [PATCH 4/9] arm: ls1012a: " Minghuan Lian
2016-10-10 8:47 ` [U-Boot] [PATCH 5/9] armv8: ls1043a: " Minghuan Lian
2016-10-10 8:47 ` [U-Boot] [PATCH 6/9] armv8: ls1046a: " Minghuan Lian
2016-10-10 8:47 ` [U-Boot] [PATCH 7/9] armv8: ls2080a: " Minghuan Lian
2016-10-10 8:47 ` [U-Boot] [PATCH 8/9] pci: layerscape: rewrite pci driver based on DM Minghuan Lian
2016-10-10 11:49 ` Bin Meng
2016-10-11 7:21 ` M.H. Lian
2016-10-11 7:28 ` Bin Meng
2016-10-10 8:47 ` [U-Boot] [PATCH 9/9] armv8: ls1046a: Enable PCIe support Minghuan Lian
2016-10-10 8:47 ` Minghuan Lian
2016-10-10 11:41 ` Bin Meng
2016-10-11 7:14 ` M.H. Lian
2016-10-10 9:03 ` [U-Boot] [PATCH 1/9] dm: pci: return the real controller in pci_bus_to_hose() Bin Meng
2016-10-10 9:09 ` M.H. Lian
2016-10-10 10:37 ` Bin Meng
2016-10-11 7:12 ` M.H. Lian
2016-10-11 7:43 ` Bin Meng
2016-10-11 9:36 ` M.H. Lian
2016-10-11 10:35 ` Bin Meng
2016-10-11 11:01 ` M.H. Lian
2016-11-07 18:13 ` york sun
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.