From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754063AbcJMK5h (ORCPT ); Thu, 13 Oct 2016 06:57:37 -0400 Received: from mail-pf0-f195.google.com ([209.85.192.195]:35440 "EHLO mail-pf0-f195.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753784AbcJMK50 (ORCPT ); Thu, 13 Oct 2016 06:57:26 -0400 From: Cheng Chao To: tglx@linutronix.de, jason@lakedaemon.net, marc.zyngier@arm.com Cc: linux-kernel@vger.kernel.org, Cheng Chao Subject: [PATCH] irqchip/gic: Enable gic_set_affinity set more than one cpu Date: Thu, 13 Oct 2016 18:57:14 +0800 Message-Id: <1476356234-7570-1-git-send-email-cs.os.kernel@gmail.com> X-Mailer: git-send-email 2.4.11 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org GIC can distribute an interrupt to more than one cpu, but now, gic_set_affinity sets only one cpu to handle interrupt. Signed-off-by: Cheng Chao --- drivers/irqchip/irq-gic.c | 28 ++++++++++++++++++++++++---- 1 file changed, 24 insertions(+), 4 deletions(-) diff --git a/drivers/irqchip/irq-gic.c b/drivers/irqchip/irq-gic.c index 58e5b4e..198d33f 100644 --- a/drivers/irqchip/irq-gic.c +++ b/drivers/irqchip/irq-gic.c @@ -328,18 +328,38 @@ static int gic_set_affinity(struct irq_data *d, const struct cpumask *mask_val, unsigned int cpu, shift = (gic_irq(d) % 4) * 8; u32 val, mask, bit; unsigned long flags; + u32 valid_mask; - if (!force) - cpu = cpumask_any_and(mask_val, cpu_online_mask); - else + if (!force) { + valid_mask = cpumask_bits(mask_val)[0]; + valid_mask &= cpumask_bits(cpu_online_mask)[0]; + + cpu = cpumask_any((struct cpumask *)&valid_mask); + } else { cpu = cpumask_first(mask_val); + } if (cpu >= NR_GIC_CPU_IF || cpu >= nr_cpu_ids) return -EINVAL; gic_lock_irqsave(flags); mask = 0xff << shift; - bit = gic_cpu_map[cpu] << shift; + + if (!force) { + bit = 0; + + for_each_cpu(cpu, (struct cpumask *)&valid_mask) { + if (cpu >= NR_GIC_CPU_IF || cpu >= nr_cpu_ids) + break; + + bit |= gic_cpu_map[cpu]; + } + + bit = bit << shift; + } else { + bit = gic_cpu_map[cpu] << shift; + } + val = readl_relaxed(reg) & ~mask; writel_relaxed(val | bit, reg); gic_unlock_irqrestore(flags); -- 2.4.11