From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1757087AbcJMUsI (ORCPT ); Thu, 13 Oct 2016 16:48:08 -0400 Received: from mga03.intel.com ([134.134.136.65]:51651 "EHLO mga03.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1755503AbcJMUr6 (ORCPT ); Thu, 13 Oct 2016 16:47:58 -0400 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.31,489,1473145200"; d="scan'208";a="19423788" Message-ID: <1476391230.2478.44.camel@intel.com> Subject: Re: [PATCH 08/10] drm/i915/gen9: Add skl_wm_level_equals() From: Paulo Zanoni To: Lyude , intel-gfx@lists.freedesktop.org Cc: Maarten Lankhorst , Ville =?ISO-8859-1?Q?Syrj=E4l=E4?= , Daniel Vetter , Jani Nikula , David Airlie , dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org Date: Thu, 13 Oct 2016 17:40:30 -0300 In-Reply-To: <1475885497-6094-9-git-send-email-cpaul@redhat.com> References: <1475885497-6094-1-git-send-email-cpaul@redhat.com> <1475885497-6094-9-git-send-email-cpaul@redhat.com> Content-Type: text/plain; charset="UTF-8" X-Mailer: Evolution 3.20.5 (3.20.5-1.fc24) Mime-Version: 1.0 Content-Transfer-Encoding: 8bit Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Em Sex, 2016-10-07 às 20:11 -0400, Lyude escreveu: > Helper we're going to be using for implementing verification of the > wm > levels in skl_verify_wm_level(). > > Signed-off-by: Lyude Reviewed-by: Paulo Zanoni > Cc: Maarten Lankhorst > Cc: Ville Syrjälä > Cc: Paulo Zanoni > --- >  drivers/gpu/drm/i915/intel_drv.h |  2 ++ >  drivers/gpu/drm/i915/intel_pm.c  | 14 ++++++++++++++ >  2 files changed, 16 insertions(+) > > diff --git a/drivers/gpu/drm/i915/intel_drv.h > b/drivers/gpu/drm/i915/intel_drv.h > index 73a2d16d..3e6e9af 100644 > --- a/drivers/gpu/drm/i915/intel_drv.h > +++ b/drivers/gpu/drm/i915/intel_drv.h > @@ -1761,6 +1761,8 @@ void skl_pipe_wm_get_hw_state(struct drm_crtc > *crtc, >  bool intel_can_enable_sagv(struct drm_atomic_state *state); >  int intel_enable_sagv(struct drm_i915_private *dev_priv); >  int intel_disable_sagv(struct drm_i915_private *dev_priv); > +bool skl_wm_level_equals(const struct skl_wm_level *l1, > +  const struct skl_wm_level *l2); >  bool skl_ddb_allocation_equals(const struct skl_ddb_allocation *old, >          const struct skl_ddb_allocation *new, >          enum pipe pipe); > diff --git a/drivers/gpu/drm/i915/intel_pm.c > b/drivers/gpu/drm/i915/intel_pm.c > index 27a520ce..6af1587 100644 > --- a/drivers/gpu/drm/i915/intel_pm.c > +++ b/drivers/gpu/drm/i915/intel_pm.c > @@ -3853,6 +3853,20 @@ void skl_write_cursor_wm(struct intel_crtc > *intel_crtc, >       &ddb->plane[pipe][PLANE_CURSOR]); >  } >   > +bool skl_wm_level_equals(const struct skl_wm_level *l1, > +  const struct skl_wm_level *l2) > +{ > + if (l1->plane_en != l2->plane_en) > + return false; > + > + /* If both planes aren't enabled, the rest shouldn't matter > */ > + if (!l1->plane_en) > + return true; > + > + return (l1->plane_res_l == l2->plane_res_l && > + l1->plane_res_b == l2->plane_res_b); > +} > + >  static inline bool skl_ddb_entries_overlap(const struct > skl_ddb_entry *a, >      const struct > skl_ddb_entry *b) >  { From mboxrd@z Thu Jan 1 00:00:00 1970 From: Paulo Zanoni Subject: Re: [PATCH 08/10] drm/i915/gen9: Add skl_wm_level_equals() Date: Thu, 13 Oct 2016 17:40:30 -0300 Message-ID: <1476391230.2478.44.camel@intel.com> References: <1475885497-6094-1-git-send-email-cpaul@redhat.com> <1475885497-6094-9-git-send-email-cpaul@redhat.com> Mime-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Return-path: In-Reply-To: <1475885497-6094-9-git-send-email-cpaul@redhat.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" To: Lyude , intel-gfx@lists.freedesktop.org Cc: David Airlie , linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, Daniel Vetter List-Id: dri-devel@lists.freedesktop.org RW0gU2V4LCAyMDE2LTEwLTA3IMOgcyAyMDoxMSAtMDQwMCwgTHl1ZGUgZXNjcmV2ZXU6Cj4gSGVs cGVyIHdlJ3JlIGdvaW5nIHRvIGJlIHVzaW5nIGZvciBpbXBsZW1lbnRpbmcgdmVyaWZpY2F0aW9u IG9mIHRoZQo+IHdtCj4gbGV2ZWxzIGluIHNrbF92ZXJpZnlfd21fbGV2ZWwoKS4KPiAKPiBTaWdu ZWQtb2ZmLWJ5OiBMeXVkZSA8Y3BhdWxAcmVkaGF0LmNvbT4KClJldmlld2VkLWJ5OiBQYXVsbyBa YW5vbmkgPHBhdWxvLnIuemFub25pQGludGVsLmNvbT4KCj4gQ2M6IE1hYXJ0ZW4gTGFua2hvcnN0 IDxtYWFydGVuLmxhbmtob3JzdEBsaW51eC5pbnRlbC5jb20+Cj4gQ2M6IFZpbGxlIFN5cmrDpGzD pCA8dmlsbGUuc3lyamFsYUBsaW51eC5pbnRlbC5jb20+Cj4gQ2M6IFBhdWxvIFphbm9uaSA8cGF1 bG8uci56YW5vbmlAaW50ZWwuY29tPgo+IC0tLQo+IMKgZHJpdmVycy9ncHUvZHJtL2k5MTUvaW50 ZWxfZHJ2LmggfMKgwqAyICsrCj4gwqBkcml2ZXJzL2dwdS9kcm0vaTkxNS9pbnRlbF9wbS5jwqDC oHwgMTQgKysrKysrKysrKysrKysKPiDCoDIgZmlsZXMgY2hhbmdlZCwgMTYgaW5zZXJ0aW9ucygr KQo+IAo+IGRpZmYgLS1naXQgYS9kcml2ZXJzL2dwdS9kcm0vaTkxNS9pbnRlbF9kcnYuaAo+IGIv ZHJpdmVycy9ncHUvZHJtL2k5MTUvaW50ZWxfZHJ2LmgKPiBpbmRleCA3M2EyZDE2ZC4uM2U2ZTlh ZiAxMDA2NDQKPiAtLS0gYS9kcml2ZXJzL2dwdS9kcm0vaTkxNS9pbnRlbF9kcnYuaAo+ICsrKyBi L2RyaXZlcnMvZ3B1L2RybS9pOTE1L2ludGVsX2Rydi5oCj4gQEAgLTE3NjEsNiArMTc2MSw4IEBA IHZvaWQgc2tsX3BpcGVfd21fZ2V0X2h3X3N0YXRlKHN0cnVjdCBkcm1fY3J0Ywo+ICpjcnRjLAo+ IMKgYm9vbCBpbnRlbF9jYW5fZW5hYmxlX3NhZ3Yoc3RydWN0IGRybV9hdG9taWNfc3RhdGUgKnN0 YXRlKTsKPiDCoGludCBpbnRlbF9lbmFibGVfc2FndihzdHJ1Y3QgZHJtX2k5MTVfcHJpdmF0ZSAq ZGV2X3ByaXYpOwo+IMKgaW50IGludGVsX2Rpc2FibGVfc2FndihzdHJ1Y3QgZHJtX2k5MTVfcHJp dmF0ZSAqZGV2X3ByaXYpOwo+ICtib29sIHNrbF93bV9sZXZlbF9lcXVhbHMoY29uc3Qgc3RydWN0 IHNrbF93bV9sZXZlbCAqbDEsCj4gKwkJCcKgY29uc3Qgc3RydWN0IHNrbF93bV9sZXZlbCAqbDIp Owo+IMKgYm9vbCBza2xfZGRiX2FsbG9jYXRpb25fZXF1YWxzKGNvbnN0IHN0cnVjdCBza2xfZGRi X2FsbG9jYXRpb24gKm9sZCwKPiDCoAkJCcKgwqDCoMKgwqDCoMKgY29uc3Qgc3RydWN0IHNrbF9k ZGJfYWxsb2NhdGlvbiAqbmV3LAo+IMKgCQkJwqDCoMKgwqDCoMKgwqBlbnVtIHBpcGUgcGlwZSk7 Cj4gZGlmZiAtLWdpdCBhL2RyaXZlcnMvZ3B1L2RybS9pOTE1L2ludGVsX3BtLmMKPiBiL2RyaXZl cnMvZ3B1L2RybS9pOTE1L2ludGVsX3BtLmMKPiBpbmRleCAyN2E1MjBjZS4uNmFmMTU4NyAxMDA2 NDQKPiAtLS0gYS9kcml2ZXJzL2dwdS9kcm0vaTkxNS9pbnRlbF9wbS5jCj4gKysrIGIvZHJpdmVy cy9ncHUvZHJtL2k5MTUvaW50ZWxfcG0uYwo+IEBAIC0zODUzLDYgKzM4NTMsMjAgQEAgdm9pZCBz a2xfd3JpdGVfY3Vyc29yX3dtKHN0cnVjdCBpbnRlbF9jcnRjCj4gKmludGVsX2NydGMsCj4gwqAJ CQnCoMKgwqDCoCZkZGItPnBsYW5lW3BpcGVdW1BMQU5FX0NVUlNPUl0pOwo+IMKgfQo+IMKgCj4g K2Jvb2wgc2tsX3dtX2xldmVsX2VxdWFscyhjb25zdCBzdHJ1Y3Qgc2tsX3dtX2xldmVsICpsMSwK PiArCQkJwqBjb25zdCBzdHJ1Y3Qgc2tsX3dtX2xldmVsICpsMikKPiArewo+ICsJaWYgKGwxLT5w bGFuZV9lbiAhPSBsMi0+cGxhbmVfZW4pCj4gKwkJcmV0dXJuIGZhbHNlOwo+ICsKPiArCS8qIElm IGJvdGggcGxhbmVzIGFyZW4ndCBlbmFibGVkLCB0aGUgcmVzdCBzaG91bGRuJ3QgbWF0dGVyCj4g Ki8KPiArCWlmICghbDEtPnBsYW5lX2VuKQo+ICsJCXJldHVybiB0cnVlOwo+ICsKPiArCXJldHVy biAobDEtPnBsYW5lX3Jlc19sID09IGwyLT5wbGFuZV9yZXNfbCAmJgo+ICsJCWwxLT5wbGFuZV9y ZXNfYiA9PSBsMi0+cGxhbmVfcmVzX2IpOwo+ICt9Cj4gKwo+IMKgc3RhdGljIGlubGluZSBib29s IHNrbF9kZGJfZW50cmllc19vdmVybGFwKGNvbnN0IHN0cnVjdAo+IHNrbF9kZGJfZW50cnkgKmEs Cj4gwqAJCQkJCcKgwqDCoGNvbnN0IHN0cnVjdAo+IHNrbF9kZGJfZW50cnkgKmIpCj4gwqB7Cl9f X19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fCkludGVsLWdmeCBt YWlsaW5nIGxpc3QKSW50ZWwtZ2Z4QGxpc3RzLmZyZWVkZXNrdG9wLm9yZwpodHRwczovL2xpc3Rz LmZyZWVkZXNrdG9wLm9yZy9tYWlsbWFuL2xpc3RpbmZvL2ludGVsLWdmeAo=