From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:48842) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bvcHf-0003MF-Ql for qemu-devel@nongnu.org; Sat, 15 Oct 2016 23:38:49 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1bvcHe-0005qw-RJ for qemu-devel@nongnu.org; Sat, 15 Oct 2016 23:38:47 -0400 Received: from mail-qk0-x242.google.com ([2607:f8b0:400d:c09::242]:35535) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1bvcHe-0005qm-MZ for qemu-devel@nongnu.org; Sat, 15 Oct 2016 23:38:46 -0400 Received: by mail-qk0-x242.google.com with SMTP id v138so11423747qka.2 for ; Sat, 15 Oct 2016 20:38:46 -0700 (PDT) Received: from bigtime.com ([2607:fb90:848f:44ba:5e51:4fff:fe40:9c64]) by smtp.gmail.com with ESMTPSA id v186sm11672982qkb.23.2016.10.15.20.38.44 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sat, 15 Oct 2016 20:38:45 -0700 (PDT) Sender: Richard Henderson From: Richard Henderson Date: Sat, 15 Oct 2016 20:37:45 -0700 Message-Id: <1476589070-5792-11-git-send-email-rth@twiddle.net> In-Reply-To: <1476589070-5792-1-git-send-email-rth@twiddle.net> References: <1476589070-5792-1-git-send-email-rth@twiddle.net> Subject: [Qemu-devel] [PATCH 10/15] target-alpha: Use deposit and extract ops List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Signed-off-by: Richard Henderson --- target-alpha/translate.c | 67 ++++++++++++++++++++++++++++++------------------ 1 file changed, 42 insertions(+), 25 deletions(-) diff --git a/target-alpha/translate.c b/target-alpha/translate.c index af717ca..a341729 100644 --- a/target-alpha/translate.c +++ b/target-alpha/translate.c @@ -953,7 +953,13 @@ static void gen_ext_h(DisasContext *ctx, TCGv vc, TCGv va, int rb, bool islit, uint8_t lit, uint8_t byte_mask) { if (islit) { - tcg_gen_shli_i64(vc, va, (64 - lit * 8) & 0x3f); + int pos = (64 - lit * 8) & 0x3f; + int len = cto32(byte_mask) * 8; + if (pos < len) { + tcg_gen_deposit_i64(vc, load_zero(ctx), va, pos, len - pos); + } else { + tcg_gen_movi_i64(vc, 0); + } } else { TCGv tmp = tcg_temp_new(); tcg_gen_shli_i64(tmp, load_gpr(ctx, rb), 3); @@ -970,38 +976,44 @@ static void gen_ext_l(DisasContext *ctx, TCGv vc, TCGv va, int rb, bool islit, uint8_t lit, uint8_t byte_mask) { if (islit) { - tcg_gen_shri_i64(vc, va, (lit & 7) * 8); + int pos = (lit & 7) * 8; + int len = cto32(byte_mask) * 8; + if (pos + len >= 64) { + len = 64 - pos; + } + tcg_gen_extract_i64(vc, va, pos, len); } else { TCGv tmp = tcg_temp_new(); tcg_gen_andi_i64(tmp, load_gpr(ctx, rb), 7); tcg_gen_shli_i64(tmp, tmp, 3); tcg_gen_shr_i64(vc, va, tmp); tcg_temp_free(tmp); + gen_zapnoti(vc, vc, byte_mask); } - gen_zapnoti(vc, vc, byte_mask); } /* INSWH, INSLH, INSQH */ static void gen_ins_h(DisasContext *ctx, TCGv vc, TCGv va, int rb, bool islit, uint8_t lit, uint8_t byte_mask) { - TCGv tmp = tcg_temp_new(); - - /* The instruction description has us left-shift the byte mask and extract - bits <15:8> and apply that zap at the end. This is equivalent to simply - performing the zap first and shifting afterward. */ - gen_zapnoti(tmp, va, byte_mask); - if (islit) { - lit &= 7; - if (unlikely(lit == 0)) { - tcg_gen_movi_i64(vc, 0); + int pos = 64 - (lit & 7) * 8; + int len = cto32(byte_mask) * 8; + if (pos < len) { + tcg_gen_extract_i64(vc, va, pos, len - pos); } else { - tcg_gen_shri_i64(vc, tmp, 64 - lit * 8); + tcg_gen_movi_i64(vc, 0); } } else { + TCGv tmp = tcg_temp_new(); TCGv shift = tcg_temp_new(); + /* The instruction description has us left-shift the byte mask + and extract bits <15:8> and apply that zap at the end. This + is equivalent to simply performing the zap first and shifting + afterward. */ + gen_zapnoti(tmp, va, byte_mask); + /* If (B & 7) == 0, we need to shift by 64 and leave a zero. Do this portably by splitting the shift into two parts: shift_count-1 and 1. Arrange for the -1 by using ones-complement instead of @@ -1014,32 +1026,37 @@ static void gen_ins_h(DisasContext *ctx, TCGv vc, TCGv va, int rb, bool islit, tcg_gen_shr_i64(vc, tmp, shift); tcg_gen_shri_i64(vc, vc, 1); tcg_temp_free(shift); + tcg_temp_free(tmp); } - tcg_temp_free(tmp); } /* INSBL, INSWL, INSLL, INSQL */ static void gen_ins_l(DisasContext *ctx, TCGv vc, TCGv va, int rb, bool islit, uint8_t lit, uint8_t byte_mask) { - TCGv tmp = tcg_temp_new(); - - /* The instruction description has us left-shift the byte mask - the same number of byte slots as the data and apply the zap - at the end. This is equivalent to simply performing the zap - first and shifting afterward. */ - gen_zapnoti(tmp, va, byte_mask); - if (islit) { - tcg_gen_shli_i64(vc, tmp, (lit & 7) * 8); + int pos = (lit & 7) * 8; + int len = cto32(byte_mask) * 8; + if (pos + len > 64) { + len = 64 - pos; + } + tcg_gen_deposit_i64(vc, load_zero(ctx), va, pos, len); } else { + TCGv tmp = tcg_temp_new(); TCGv shift = tcg_temp_new(); + + /* The instruction description has us left-shift the byte mask + and extract bits <15:8> and apply that zap at the end. This + is equivalent to simply performing the zap first and shifting + afterward. */ + gen_zapnoti(tmp, va, byte_mask); + tcg_gen_andi_i64(shift, load_gpr(ctx, rb), 7); tcg_gen_shli_i64(shift, shift, 3); tcg_gen_shl_i64(vc, tmp, shift); tcg_temp_free(shift); + tcg_temp_free(tmp); } - tcg_temp_free(tmp); } /* MSKWH, MSKLH, MSKQH */ -- 2.7.4