From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:56906) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bwW2z-000737-M2 for qemu-devel@nongnu.org; Tue, 18 Oct 2016 11:11:25 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1bwW2y-0005BP-QN for qemu-devel@nongnu.org; Tue, 18 Oct 2016 11:11:21 -0400 Received: from mail-it0-x243.google.com ([2607:f8b0:4001:c0b::243]:36563) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1bwW2y-0005B9-Ka for qemu-devel@nongnu.org; Tue, 18 Oct 2016 11:11:20 -0400 Received: by mail-it0-x243.google.com with SMTP id 66so30395itl.3 for ; Tue, 18 Oct 2016 08:11:20 -0700 (PDT) Received: from bigtime.com (174-24-157-40.tukw.qwest.net. [174.24.157.40]) by smtp.gmail.com with ESMTPSA id y189sm10674863ioy.28.2016.10.18.08.11.19 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 18 Oct 2016 08:11:19 -0700 (PDT) Sender: Richard Henderson From: Richard Henderson Date: Tue, 18 Oct 2016 08:10:31 -0700 Message-Id: <1476803431-7208-19-git-send-email-rth@twiddle.net> In-Reply-To: <1476803431-7208-1-git-send-email-rth@twiddle.net> References: <1476803431-7208-1-git-send-email-rth@twiddle.net> Subject: [Qemu-devel] [PATCH v2 18/18] target-s390x: Use the new deposit and extract ops List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Use the new primitives for RISBG. Signed-off-by: Richard Henderson --- target-s390x/translate.c | 34 ++++++++++++++++++++++------------ 1 file changed, 22 insertions(+), 12 deletions(-) diff --git a/target-s390x/translate.c b/target-s390x/translate.c index 02bc705..6cebb7e 100644 --- a/target-s390x/translate.c +++ b/target-s390x/translate.c @@ -3134,20 +3134,26 @@ static ExitStatus op_risbg(DisasContext *s, DisasOps *o) } } - /* In some cases we can implement this with deposit, which can be more - efficient on some hosts. */ - if (~mask == imask && i3 <= i4) { - if (s->fields->op2 == 0x5d) { - i3 += 32, i4 += 32; - } + len = i4 - i3 + 1; + pos = 63 - i4; + rot = i5 & 63; + if (s->fields->op2 == 0x5d) { + pos += 32; + } + + /* In some cases we can implement this with extract. */ + if (imask == 0 && pos == 0 && len > 0 && rot + len <= 64) { + tcg_gen_extract_i64(o->out, o->in2, rot, len); + return NO_EXIT; + } + + /* In some cases we can implement this with deposit. */ + if (len > 0 && (imask == 0 || ~mask == imask)) { /* Note that we rotate the bits to be inserted to the lsb, not to the position as described in the PoO. */ - len = i4 - i3 + 1; - pos = 63 - i4; - rot = (i5 - pos) & 63; + rot = (rot - pos) & 63; } else { - pos = len = -1; - rot = i5 & 63; + pos = -1; } /* Rotate the input as necessary. */ @@ -3155,7 +3161,11 @@ static ExitStatus op_risbg(DisasContext *s, DisasOps *o) /* Insert the selected bits into the output. */ if (pos >= 0) { - tcg_gen_deposit_i64(o->out, o->out, o->in2, pos, len); + if (imask == 0) { + tcg_gen_deposit_z_i64(o->out, o->in2, pos, len); + } else { + tcg_gen_deposit_i64(o->out, o->out, o->in2, pos, len); + } } else if (imask == 0) { tcg_gen_andi_i64(o->out, o->in2, mask); } else { -- 2.7.4