From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:36647) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bxsvY-0006a1-MP for qemu-devel@nongnu.org; Sat, 22 Oct 2016 05:49:21 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1bxsvV-0002ie-Kz for qemu-devel@nongnu.org; Sat, 22 Oct 2016 05:49:20 -0400 Received: from 5.mo69.mail-out.ovh.net ([46.105.43.105]:39749) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1bxsvV-0002iW-F0 for qemu-devel@nongnu.org; Sat, 22 Oct 2016 05:49:17 -0400 Received: from player798.ha.ovh.net (b7.ovh.net [213.186.33.57]) by mo69.mail-out.ovh.net (Postfix) with ESMTP id 7414C6AA9 for ; Sat, 22 Oct 2016 11:49:16 +0200 (CEST) From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Date: Sat, 22 Oct 2016 11:46:46 +0200 Message-Id: <1477129610-31353-14-git-send-email-clg@kaod.org> In-Reply-To: <1477129610-31353-1-git-send-email-clg@kaod.org> References: <1477129610-31353-1-git-send-email-clg@kaod.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Subject: [Qemu-devel] [PATCH v5 13/17] ppc/xics: add a xics_get_cpu_index_by_pir helper List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-ppc@nongnu.org Cc: David Gibson , Benjamin Herrenschmidt , qemu-devel@nongnu.org, Alexander Graf , Cedric Le Goater We will need this helper to translate the server number of the XIVE (which is a PIR) into an ICPState index number (which is a cpu index). Signed-off-by: C=C3=A9dric Le Goater --- hw/intc/xics_native.c | 19 +++++++++++++++++++ include/hw/ppc/xics.h | 1 + 2 files changed, 20 insertions(+) diff --git a/hw/intc/xics_native.c b/hw/intc/xics_native.c index bbdd786aeb50..6318862f53fc 100644 --- a/hw/intc/xics_native.c +++ b/hw/intc/xics_native.c @@ -33,6 +33,25 @@ =20 #include =20 +int xics_get_cpu_index_by_pir(XICSState *xics, int pir) +{ + int i; + + for (i =3D 0; i < xics->nr_servers; i++) { + ICPState *icp =3D &xics->ss[i]; + if (icp->cs) { + PowerPCCPU *cpu =3D POWERPC_CPU(icp->cs); + CPUPPCState *env =3D &cpu->env; + + if (env->spr_cb[SPR_PIR].default_value =3D=3D pir) { + return i; + } + } + } + + return -1; +} + static void xics_native_reset(void *opaque) { device_reset(DEVICE(opaque)); diff --git a/include/hw/ppc/xics.h b/include/hw/ppc/xics.h index 911cdd5e549f..beb232e616c5 100644 --- a/include/hw/ppc/xics.h +++ b/include/hw/ppc/xics.h @@ -214,6 +214,7 @@ void xics_set_nr_servers(XICSState *xics, uint32_t nr= _servers, =20 /* Internal XICS interfaces */ int xics_get_cpu_index_by_dt_id(int cpu_dt_id); +int xics_get_cpu_index_by_pir(XICSState *xics, int pir); =20 void icp_set_cppr(ICPState *icp, uint8_t cppr); void icp_set_mfrr(ICPState *icp, uint8_t mfrr); --=20 2.7.4