From mboxrd@z Thu Jan  1 00:00:00 1970
Received: from eggs.gnu.org ([2001:4830:134:3::10]:36348)
	by lists.gnu.org with esmtp (Exim 4.71)
	(envelope-from <clg@kaod.org>) id 1bxsuc-0005lv-Kw
	for qemu-devel@nongnu.org; Sat, 22 Oct 2016 05:48:25 -0400
Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71)
	(envelope-from <clg@kaod.org>) id 1bxsuZ-0002C0-Hk
	for qemu-devel@nongnu.org; Sat, 22 Oct 2016 05:48:22 -0400
Received: from 3.mo69.mail-out.ovh.net ([188.165.52.203]:60161)
	by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32)
	(Exim 4.71) (envelope-from <clg@kaod.org>) id 1bxsuZ-0002Bg-9Z
	for qemu-devel@nongnu.org; Sat, 22 Oct 2016 05:48:19 -0400
Received: from player798.ha.ovh.net (b7.ovh.net [213.186.33.57])
	by mo69.mail-out.ovh.net (Postfix) with ESMTP id 5950454CA
	for <qemu-devel@nongnu.org>; Sat, 22 Oct 2016 11:48:18 +0200 (CEST)
From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= <clg@kaod.org>
Date: Sat, 22 Oct 2016 11:46:37 +0200
Message-Id: <1477129610-31353-5-git-send-email-clg@kaod.org>
In-Reply-To: <1477129610-31353-1-git-send-email-clg@kaod.org>
References: <1477129610-31353-1-git-send-email-clg@kaod.org>
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: quoted-printable
Subject: [Qemu-devel] [PATCH v5 04/17] ppc/pnv: add a core mask to PnvChip
List-Id: <qemu-devel.nongnu.org>
List-Unsubscribe: <https://lists.nongnu.org/mailman/options/qemu-devel>,
	<mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>
List-Archive: <http://lists.nongnu.org/archive/html/qemu-devel/>
List-Post: <mailto:qemu-devel@nongnu.org>
List-Help: <mailto:qemu-devel-request@nongnu.org?subject=help>
List-Subscribe: <https://lists.nongnu.org/mailman/listinfo/qemu-devel>,
	<mailto:qemu-devel-request@nongnu.org?subject=subscribe>
To: qemu-ppc@nongnu.org
Cc: David Gibson <david@gibson.dropbear.id.au>, Benjamin Herrenschmidt <benh@kernel.crashing.org>, qemu-devel@nongnu.org, Alexander Graf <agraf@suse.de>, Cedric Le Goater <clg@kaod.org>

This will be used to build real HW ids for the cores and enforce some
limits on the available cores per chip.

Signed-off-by: C=C3=A9dric Le Goater <clg@kaod.org>
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
---

 Changes since v4 :

 - removed setting of 'cores-mask' property. -global can be used to
   alter the default setting.

 Changes since v3 :

 - reworked pnv_chip_core_sanitize() to return errors and to check the
   maximum of cores against the instance cores_mask
 =20
 Changes since v2 :

 - added POWER9 support
 - removed cores_max=20
 - introduces a pnv_chip_core_sanitize() helper to check the core
   ids_mask and the maximum number of cores

 hw/ppc/pnv.c         | 73 ++++++++++++++++++++++++++++++++++++++++++++++=
+++++-
 include/hw/ppc/pnv.h |  4 +++
 2 files changed, 76 insertions(+), 1 deletion(-)

diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c
index aeafd7e894d2..1705699ef8a0 100644
--- a/hw/ppc/pnv.c
+++ b/hw/ppc/pnv.c
@@ -238,11 +238,38 @@ static void ppc_powernv_init(MachineState *machine)
         object_property_add_child(OBJECT(pnv), chip_name, chip, &error_f=
atal);
         object_property_set_int(chip, PNV_CHIP_HWID(i), "chip-id",
                                 &error_fatal);
+        object_property_set_int(chip, smp_cores, "nr-cores", &error_fata=
l);
         object_property_set_bool(chip, true, "realized", &error_fatal);
     }
     g_free(chip_typename);
 }
=20
+/* Allowed core identifiers on a POWER8 Processor Chip :
+ *
+ * <EX0 reserved>
+ *  EX1  - Venice only
+ *  EX2  - Venice only
+ *  EX3  - Venice only
+ *  EX4
+ *  EX5
+ *  EX6
+ * <EX7,8 reserved> <reserved>
+ *  EX9  - Venice only
+ *  EX10 - Venice only
+ *  EX11 - Venice only
+ *  EX12
+ *  EX13
+ *  EX14
+ * <EX15 reserved>
+ */
+#define POWER8E_CORE_MASK  (0x7070ull)
+#define POWER8_CORE_MASK   (0x7e7eull)
+
+/*
+ * POWER9 has 24 cores, ids starting at 0x20
+ */
+#define POWER9_CORE_MASK   (0xffffff00000000ull)
+
 static void pnv_chip_power8e_class_init(ObjectClass *klass, void *data)
 {
     DeviceClass *dc =3D DEVICE_CLASS(klass);
@@ -251,6 +278,7 @@ static void pnv_chip_power8e_class_init(ObjectClass *=
klass, void *data)
     k->cpu_model =3D "POWER8E";
     k->chip_type =3D PNV_CHIP_POWER8E;
     k->chip_cfam_id =3D 0x221ef04980000000ull;  /* P8 Murano DD2.1 */
+    k->cores_mask =3D POWER8E_CORE_MASK;
     dc->desc =3D "PowerNV Chip POWER8E";
 }
=20
@@ -269,6 +297,7 @@ static void pnv_chip_power8_class_init(ObjectClass *k=
lass, void *data)
     k->cpu_model =3D "POWER8";
     k->chip_type =3D PNV_CHIP_POWER8;
     k->chip_cfam_id =3D 0x220ea04980000000ull; /* P8 Venice DD2.0 */
+    k->cores_mask =3D POWER8_CORE_MASK;
     dc->desc =3D "PowerNV Chip POWER8";
 }
=20
@@ -287,6 +316,7 @@ static void pnv_chip_power8nvl_class_init(ObjectClass=
 *klass, void *data)
     k->cpu_model =3D "POWER8NVL";
     k->chip_type =3D PNV_CHIP_POWER8NVL;
     k->chip_cfam_id =3D 0x120d304980000000ull;  /* P8 Naples DD1.0 */
+    k->cores_mask =3D POWER8_CORE_MASK;
     dc->desc =3D "PowerNV Chip POWER8NVL";
 }
=20
@@ -305,6 +335,7 @@ static void pnv_chip_power9_class_init(ObjectClass *k=
lass, void *data)
     k->cpu_model =3D "POWER9";
     k->chip_type =3D PNV_CHIP_POWER9;
     k->chip_cfam_id =3D 0x100d104980000000ull; /* P9 Nimbus DD1.0 */
+    k->cores_mask =3D POWER9_CORE_MASK;
     dc->desc =3D "PowerNV Chip POWER9";
 }
=20
@@ -315,15 +346,55 @@ static const TypeInfo pnv_chip_power9_info =3D {
     .class_init    =3D pnv_chip_power9_class_init,
 };
=20
+static void pnv_chip_core_sanitize(PnvChip *chip, Error **errp)
+{
+    PnvChipClass *pcc =3D PNV_CHIP_GET_CLASS(chip);
+    int cores_max;
+
+    /*
+     * No custom mask for this chip, let's use the default one from *
+     * the chip class
+     */
+    if (!chip->cores_mask) {
+        chip->cores_mask =3D pcc->cores_mask;
+    }
+
+    /* filter alien core ids ! some are reserved */
+    if ((chip->cores_mask & pcc->cores_mask) !=3D chip->cores_mask) {
+        error_setg(errp, "warning: invalid core mask for chip Ox%"PRIx64=
" !",
+                   chip->cores_mask);
+        return;
+    }
+    chip->cores_mask &=3D pcc->cores_mask;
+
+    /* now that we have a sane layout, let check the number of cores */
+    cores_max =3D hweight_long(chip->cores_mask);
+    if (chip->nr_cores > cores_max) {
+        error_setg(errp, "warning: too many cores for chip ! Limit is %d=
",
+                   cores_max);
+        return;
+    }
+}
+
 static void pnv_chip_realize(DeviceState *dev, Error **errp)
 {
-    /* left purposely empty */
+    PnvChip *chip =3D PNV_CHIP(dev);
+    Error *error =3D NULL;
+
+    /* Early checks on the core settings */
+    pnv_chip_core_sanitize(chip, &error);
+    if (error) {
+        error_propagate(errp, error);
+        return;
+    }
 }
=20
 static Property pnv_chip_properties[] =3D {
     DEFINE_PROP_UINT32("chip-id", PnvChip, chip_id, 0),
     DEFINE_PROP_UINT64("ram-start", PnvChip, ram_start, 0),
     DEFINE_PROP_UINT64("ram-size", PnvChip, ram_size, 0),
+    DEFINE_PROP_UINT32("nr-cores", PnvChip, nr_cores, 1),
+    DEFINE_PROP_UINT64("cores-mask", PnvChip, cores_mask, 0x0),
     DEFINE_PROP_END_OF_LIST(),
 };
=20
diff --git a/include/hw/ppc/pnv.h b/include/hw/ppc/pnv.h
index 7189961e1f42..e084a8c30359 100644
--- a/include/hw/ppc/pnv.h
+++ b/include/hw/ppc/pnv.h
@@ -44,6 +44,9 @@ typedef struct PnvChip {
     uint32_t     chip_id;
     uint64_t     ram_start;
     uint64_t     ram_size;
+
+    uint32_t     nr_cores;
+    uint64_t     cores_mask;
 } PnvChip;
=20
 typedef struct PnvChipClass {
@@ -54,6 +57,7 @@ typedef struct PnvChipClass {
     const char *cpu_model;
     PnvChipType  chip_type;
     uint64_t     chip_cfam_id;
+    uint64_t     cores_mask;
 } PnvChipClass;
=20
 #define TYPE_PNV_CHIP_POWER8E TYPE_PNV_CHIP "-POWER8E"
--=20
2.7.4