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From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= <clg@kaod.org>
Date: Sat, 22 Oct 2016 11:46:38 +0200
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Subject: [Qemu-devel] [PATCH v5 05/17] ppc/pnv: add a PIR handler to PnvChip
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To: qemu-ppc@nongnu.org
Cc: David Gibson <david@gibson.dropbear.id.au>, Benjamin Herrenschmidt <benh@kernel.crashing.org>, qemu-devel@nongnu.org, Alexander Graf <agraf@suse.de>, Cedric Le Goater <clg@kaod.org>

The Processor Identification Register (PIR) is a register that holds a
processor identifier which is used for bus transactions (XSCOM) and
for processor differentiation in multiprocessor systems. It also used
in the interrupt vector entries (IVE) to identify the thread serving
the interrupts.

P9 and P8 have some differences in the CPU PIR encoding.

Signed-off-by: C=C3=A9dric Le Goater <clg@kaod.org>
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
---

 Changes since v3 :

 - added a couple more comments on the bits definition
 =20
 hw/ppc/pnv.c         | 30 ++++++++++++++++++++++++++++++
 include/hw/ppc/pnv.h |  2 ++
 2 files changed, 32 insertions(+)

diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c
index 1705699ef8a0..825d28ca75b1 100644
--- a/hw/ppc/pnv.c
+++ b/hw/ppc/pnv.c
@@ -244,6 +244,32 @@ static void ppc_powernv_init(MachineState *machine)
     g_free(chip_typename);
 }
=20
+/*
+ *    0:21  Reserved - Read as zeros
+ *   22:24  Chip ID
+ *   25:28  Core number
+ *   29:31  Thread ID
+ */
+static uint32_t pnv_chip_core_pir_p8(PnvChip *chip, uint32_t core_id)
+{
+    return (chip->chip_id << 7) | (core_id << 3);
+}
+
+/*
+ *    0:48  Reserved - Read as zeroes
+ *   49:52  Node ID
+ *   53:55  Chip ID
+ *   56     Reserved - Read as zero
+ *   57:61  Core number
+ *   62:63  Thread ID
+ *
+ * We only care about the lower bits. uint32_t is fine for the moment.
+ */
+static uint32_t pnv_chip_core_pir_p9(PnvChip *chip, uint32_t core_id)
+{
+    return (chip->chip_id << 8) | (core_id << 2);
+}
+
 /* Allowed core identifiers on a POWER8 Processor Chip :
  *
  * <EX0 reserved>
@@ -279,6 +305,7 @@ static void pnv_chip_power8e_class_init(ObjectClass *=
klass, void *data)
     k->chip_type =3D PNV_CHIP_POWER8E;
     k->chip_cfam_id =3D 0x221ef04980000000ull;  /* P8 Murano DD2.1 */
     k->cores_mask =3D POWER8E_CORE_MASK;
+    k->core_pir =3D pnv_chip_core_pir_p8;
     dc->desc =3D "PowerNV Chip POWER8E";
 }
=20
@@ -298,6 +325,7 @@ static void pnv_chip_power8_class_init(ObjectClass *k=
lass, void *data)
     k->chip_type =3D PNV_CHIP_POWER8;
     k->chip_cfam_id =3D 0x220ea04980000000ull; /* P8 Venice DD2.0 */
     k->cores_mask =3D POWER8_CORE_MASK;
+    k->core_pir =3D pnv_chip_core_pir_p8;
     dc->desc =3D "PowerNV Chip POWER8";
 }
=20
@@ -317,6 +345,7 @@ static void pnv_chip_power8nvl_class_init(ObjectClass=
 *klass, void *data)
     k->chip_type =3D PNV_CHIP_POWER8NVL;
     k->chip_cfam_id =3D 0x120d304980000000ull;  /* P8 Naples DD1.0 */
     k->cores_mask =3D POWER8_CORE_MASK;
+    k->core_pir =3D pnv_chip_core_pir_p8;
     dc->desc =3D "PowerNV Chip POWER8NVL";
 }
=20
@@ -336,6 +365,7 @@ static void pnv_chip_power9_class_init(ObjectClass *k=
lass, void *data)
     k->chip_type =3D PNV_CHIP_POWER9;
     k->chip_cfam_id =3D 0x100d104980000000ull; /* P9 Nimbus DD1.0 */
     k->cores_mask =3D POWER9_CORE_MASK;
+    k->core_pir =3D pnv_chip_core_pir_p9;
     dc->desc =3D "PowerNV Chip POWER9";
 }
=20
diff --git a/include/hw/ppc/pnv.h b/include/hw/ppc/pnv.h
index e084a8c30359..b7987f8208b8 100644
--- a/include/hw/ppc/pnv.h
+++ b/include/hw/ppc/pnv.h
@@ -58,6 +58,8 @@ typedef struct PnvChipClass {
     PnvChipType  chip_type;
     uint64_t     chip_cfam_id;
     uint64_t     cores_mask;
+
+    uint32_t (*core_pir)(PnvChip *chip, uint32_t core_id);
 } PnvChipClass;
=20
 #define TYPE_PNV_CHIP_POWER8E TYPE_PNV_CHIP "-POWER8E"
--=20
2.7.4