From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1756517AbcJWMNb (ORCPT ); Sun, 23 Oct 2016 08:13:31 -0400 Received: from mail-db5eur01on0071.outbound.protection.outlook.com ([104.47.2.71]:62166 "EHLO EUR01-DB5-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1754033AbcJWMN1 (ORCPT ); Sun, 23 Oct 2016 08:13:27 -0400 Authentication-Results: spf=pass (sender IP is 193.47.165.134) smtp.mailfrom=mellanox.com; vger.kernel.org; dkim=none (message not signed) header.d=none;vger.kernel.org; dmarc=pass action=none header.from=mellanox.com; From: Noam Camus To: , , CC: , , , Noam Camus Subject: [PATCH v2 0/3] Add clockevet for timer-nps driver to NPS400 SoC Date: Sun, 23 Oct 2016 15:12:25 +0300 Message-ID: <1477224748-25223-1-git-send-email-noamca@mellanox.com> X-Mailer: git-send-email 1.7.1 MIME-Version: 1.0 Content-Type: text/plain X-TM-AS-Product-Ver: SMEX-11.0.0.1191-8.000.1202-22520.000 X-TM-AS-Result: No--10.093800-8.000000-31 X-TM-AS-User-Approved-Sender: No X-TM-AS-User-Blocked-Sender: No X-EOPAttributedMessage: 0 X-MS-Office365-Filtering-HT: Tenant X-Forefront-Antispam-Report: CIP:193.47.165.134;IPV:NLI;CTRY:IL;EFV:NLI;SFV:NSPM;SFS:(10009020)(6009001)(7916002)(2980300002)(438002)(189002)(54534003)(199003)(189998001)(107886002)(229853001)(36756003)(626004)(92566002)(5660300001)(50986999)(106466001)(11100500001)(19580405001)(48376002)(7846002)(356003)(305945005)(81156014)(8676002)(81166006)(33646002)(4001430100002)(5001770100001)(77096005)(19580395003)(47776003)(50466002)(5003940100001)(50226002)(49486002)(4326007)(87936001)(86362001)(8936002)(2906002)(586003);DIR:OUT;SFP:1101;SCL:1;SRVR:AM4PR0501MB2355;H:mtlcas13.mtl.com;FPR:;SPF:Pass;PTR:mail13.mellanox.com;MX:1;A:1;LANG:en; X-Microsoft-Exchange-Diagnostics: 1;DB3FFO11FD014;1:4VS6dQZbNqM1/jvtLTE0/vz9TlGXqNZfznOkDfMbzCybr7an/RXLpmLPONp1WU2e76RHKckWUVloPAgFO8sun8HMSb98Vn1E3cHrKCTVfbjFp2I1xVFN29ZHFRAzAKkcIJlTROOBRzWJJa6mNGRN+MgtNg2t2VM9nPEwgrKwsTfV97TnDQKOE9oqF+8u1pkVp1BbidgVyOVtZwTBLdARsTd+su1E8dsRXgfb5wHyfXFWmHoDeBRhMpg9cLgkiFjQnnBycRsj4J3X5ktglfPcp2CL+sF6dXGwLJUhnbJmJgxAaWOJ7Aq7EJEp8fzSMjcOS6sNsE/uCaHo5ERMlAhaODoL3us4N3w2M0Y6hNv6Ay5dqS6/RtIHxMy+DQYLbam12EwDXhHfAugvND1nQVQrO76tArJSTl81VUOPbYFozOkBHnxRI90QmbnLbkfQKwTDlix7xIzv8B/vorPL3zzEdW9iSyfO34nt4yMEQnMCeSetVU7bOuMG2Jj74I1OCAfD6zhhlgFP0MOUMrY5JK0g3mR+oZ3oxVz3G62DxHw8y3xdDdZCGPjJs6QSvSdPPxZnU2fUKMbDGp+WvOin1wsYjA== X-MS-Office365-Filtering-Correlation-Id: 75e437ed-2f2c-43e8-edd5-08d3fb3dfca1 X-Microsoft-Exchange-Diagnostics: 1;AM4PR0501MB2355;2:QRpO/AWZaMvDOjYIBR4dhe7oa6pugShhbaB8zdQyMSDXdbP2+QLLS3kgXYegEQEJGG011yzwvIqhOXc+TTT5O26ykUgueRp823WUMDwoq08ZeI+2DxrYIi8RMKqDjyBw2dVNcNmq95SwIdqPqrtUNaZpbJno/rvfSvD8AyXSWcuWyrNvLv1Zz6bUab44Ck1n1j+QGlrLbJ+EsQxhI4wESg==;3:vO2GhOdxkqJlqrVU6psWL0x4GoEl2u4X195+h4+o56TM6KhAqzGmKujqzc6Y4UrHINSZPJsMdIIHywwreDgU8uJq58s7LrjDT8iEws5Y9aU5B9aFrw2Y5Cy7uDe0X+5bIub5lZjha4SZ85gXJboGWhbcwJXrX5GaO7Ooq07KkylJmPc+s+pxOXhAj3E5fdOgJE8ZplBJBBO8LoAw4KGLcW/sS4cTyyjGs7W4Drzz9lthSNDeC/65MQKxGui4YSBT2fci6cc156b2ONIyiTXdw19QYQ1rFYpb6+8mThfpPww= X-Microsoft-Antispam: UriScan:;BCL:0;PCL:0;RULEID:(8251501002);SRVR:AM4PR0501MB2355; X-Microsoft-Exchange-Diagnostics: 1;AM4PR0501MB2355;25:0qTYRQlxdHl0RcgENE4/g7PoahfS4wb+1GiID6D7RjL3exz/KlvKqH1OglrP90nBjdIf9q+Lud9Oti50CfRJYLybH42wzU3PUKg3fWoOyIldNayvbatkTZM/X2EOA4OXdIb/4D6lzSu9t65SXVtU7Armax/pCxVNURl+tgVO09QZBdE6JP66qhygLb0bOkW0rVvRGxJbZsjsAELhS7dBdTiJPA4Ft7kEOckf0sEii97+gLQyNzQ4xypaVigXEvPD8RWmKrojMYbKYmmyVhlTW6L8xacKDb5TCPd0L05tPZnO1n1jQ7pWWfa9IDG28HRC6IZZUvyj8CuiqFWAfXC/XR+JaO3mU/P43xH6s+tL6xH3xH2HPaOG+1M4bPlSU1JGB4AoD3WXye6M5HMJfFDIREEKniN1w+7cfa8+NcapZh8vfM+9EFLxr7UshFl+oewIoGlyJVZ9TtQ1diywzjeORhRepflHHg0NBkP4gfJcq798+K1ggyHuRRgMab/k4kntmLm6gtiKf9upg9zlLqnTq9vtwkAMuwksuqUG5nObrlZ83UUQCAOIGiWoUr2W+RieZa7KkLPVvWW+/cztCzh2KsmwEo/mf3nO4u4EGQKMvYcFD2RfU8M3FnY7jYboQzXoFBh5A8QTmr5oVFRhS4gW57+VK2L6VPS8j+VugTtKueHwGVOnrzwvBgh1Xrk3Cm3SPWUpDPFEJ4+X29nHqb81lIBimpqjHc1/2Ui8b0+JvMzYkEawn3DAWxFDwbxEYI15rJSrAZ2sYHrjmQHG/V9ej3Oi8hPLF1NnJcuQBEzgg4o= X-Microsoft-Exchange-Diagnostics: 1;AM4PR0501MB2355;31:r2yCpJni8CbSB9YiSOIQ2tdljw9VG9+VcSYYlPSt5Fl4/3vMjIgzH3R6keT8p4fdZzgSmeyZa4y1rjYKzE07Jf9lgp82A5KftdBeO3CWoWSd0/CrQww2mGAM90zDl8XfK5KGcguVnn+1fGe0SbQkQEqPPn4OoQ2SLAa5ytAP6hSfr9f28jSlJwH6IWPCcGW1VBZiSLRODwjjvhnJjVD98PACq66qj+2Y4yTBZXIG4OO5Cghjq7AJcL05kSJNq+tl;20:4y17DvkEdwEQZRW6Czy5051mPUDXoC+KKxVBNU/dHD0/wm2afQ6VYvJB3v6cfjroG6A7R7QHqL80RjX3rI2+cubCoV8aamNDK25Jt86mOWQSG3d3Hlm8crL4UOMijU9M6qMByTJhwF9nFY58vKtDIkFzW6ZJe22z+3hQB5zkw4nlNiUNJ4NIlasmyvg0yrkkB+aMpMEyumMFHy2GTirhg+SwutrTZIWyGDJxiVxH3jqn0dCciBqGD+13mqqQJUi45hSr4wmgoPeFxHPEKHxnkq6DkCnGFnueiWMsmE3bQPP0idevJbMFaSSIF4fNyeK3T6f1m5iO5VUn6ehPkPG9k5+CPvo1KUCWR11N0yUejVz64k0Pt1cQ2whewlGP+yrFvEHRRBv7pcYfQWYhYEp0K6ahNhHVrPeWkuVS16y+1KWl/YMmhlzNNOhsKcLJZzBjY6Mp9lg/nhIBVlfC6nw4Enyo0nt2VSc3i5nClYLbwoF+bDPhwe3EuG6LRv3Ju7zM X-Microsoft-Antispam-PRVS: X-Exchange-Antispam-Report-Test: UriScan:; X-Exchange-Antispam-Report-CFA-Test: BCL:0;PCL:0;RULEID:(6040176)(601004)(2401047)(5005006)(8121501046)(13016025)(13018025)(10201501046)(3002001)(6055026);SRVR:AM4PR0501MB2355;BCL:0;PCL:0;RULEID:;SRVR:AM4PR0501MB2355; X-Microsoft-Exchange-Diagnostics: 1;AM4PR0501MB2355;4:H9POBc21qYch6esnqnrigKSnkoZUxWhExWToC6UQRI7FKtDGABTLOHlOaE0QtnUpLn5uOwBjPEKBvA1QIYGdbJhsdvrbRclaLJcJ1NtvaugJ95AAFb1B0GdUnGhkXeMkbNlhpW0rTjlp6/7swTq/f5kqQpY1eLF/VNwKA/CW26yhhv/XdjACaJJNrwcLpp6C1F+8Dw1u9a5A7va4/3OjHJM0t3TLSzdDaWKACz3EE5orjQJMGj0XUU5dW5faY6wiFtEr4U/wunPzxTphtYecA6ejLXyLPAlM6z1o0YlNk5Ui/0yuiDsLF48MA1r5D3dwk7qZFPtb148BnuO/pz7yLxA25c+cSWlemqGQp0nAYXknlY3ukvrBmAG0vY0ZUJJhrl521It7XPWyZln89LE8e9M0asUEHKKkDIw/hvB9z2esdzRTF9DfiSJkUG+tWkl4D4xd8T4SY/C2D9jv2J85NQ== X-Forefront-PRVS: 0104247462 X-Microsoft-Exchange-Diagnostics: =?us-ascii?Q?1;AM4PR0501MB2355;23:Wqh0S0eCexDHKN8/I/ozvEmJpC7H5zFGwTzcYWq?= =?us-ascii?Q?wfpoGhCqD7MjvC2Tv8yUi06+fX1ZAkHAs3Han5r53AYEt5S2VPmRfAyyUtFP?= =?us-ascii?Q?lNTBG/UG6ljMLUxJqxlYsMODz0t8bYlTnRHZflu2rAB4jUXHHstXS8ZpnTlj?= =?us-ascii?Q?XFcaIN5Te9GR/W0mbzKookFKnhlwrizCeU8adUbqeK5Xg184bn8qdtJfb+Qc?= =?us-ascii?Q?2ggXW95EU9uhVj+maF+Cf0SvxRXt7XpoK99JLIzY12Dd9FheHj2Ph0gFiCPf?= =?us-ascii?Q?nRHQOwJLY4G0sXgA8eMSct7eMhI1gm7REp/qCQtZrpdMn9mA6NHwFDwkSaNF?= =?us-ascii?Q?QFq5drU0mMnH7OhzA7NzAE+ZJtmlTSXh4W6nG9oHF6/cjhmLzB3Wj6e9u4wn?= =?us-ascii?Q?iBY76+DQIJDWaC+tcrPrwjs6AN6M6ZBXsf7DL8wh6SuWTLFyt7xK9LjD7r0y?= =?us-ascii?Q?Lfjqc7oPiKx/j8h2lNwCaLLctTQx1RjymANCNJXxd+0nCKj1oCH3tK1euobf?= =?us-ascii?Q?ZFbzSOksKwSyQWBtXGJn0ojKropPmdM9+XarIlV2nsSWb40grad3Y5spTrXX?= =?us-ascii?Q?PouTiLpBLgf830aOSfQ0m6plErWXDGSVuwrhcoPMOA/uErTiEW/JB7kZLJi1?= =?us-ascii?Q?ihcX4h6kkzdreb+qSTwJkRa/Jlgj2J7pRX5MQTTUXpJP0OeLT6SHdGIUZzoN?= =?us-ascii?Q?MNtxzkRfoU5/io06k1YXpiPGaYT3l+gVoNUnL/GbU1vuDR34URw5smOOsApm?= =?us-ascii?Q?InU+tcGiUfnlzaG5Iw/ILRPf0mOEfWZ/2211AyF9tgTcwLr5zkKI3aoNiWGf?= =?us-ascii?Q?MDo8uawJsIP+2zG5arsWo1MOX1QWiS0FsSowc/qKfLOSDCcsY64PpcRfnMx2?= =?us-ascii?Q?g7bG8vKt7b0cD/4WBmGAyPtB9bg+fztAkZFBABPFLA/15sPGviEI582AE6SY?= =?us-ascii?Q?W9xxnsJyqeVVgmJ3bgzy3emYThmG4zXoJQwXWKIGEmISPn3KMhSi1fnQQphN?= =?us-ascii?Q?ZzL7y+7MsyjTa21EYThJWZzhKvXdBqXdrb3QepbJTtaUGFddvEx316Ox8KHN?= =?us-ascii?Q?5Vcd08RBRTRGdcqUS2EjI9NnmYTXM?= X-Microsoft-Exchange-Diagnostics: 1;AM4PR0501MB2355;6:2FCCTxWVO/BXXt4wFhRpskU0WSORLLHb1pqwHmk7iTytJhwL54OBIpPfQWnnUjY7jXxKF7HCBXg79XaoqaNGlZjurjNB6+Wq/gthCETCvC133hPrg+zhezdBB1Nyf2j23GqIEHNurOnE4eTHwoS26OQDUPTFp2JzXiUaFHlfJkXkeiaKQ74kI5sQqwVauq++FpNPML+RiZToPTTDmXBkUEvtyDx/+xSkHioiG6MDxrpNJgu4o70Ewke0QBqch8fYnFMXCnjhcWz/zzTADj/OzivQqk92fGrnNi/9hN0p6veUdbN+0F7aVxRBaNEssptLjoT1UaKDXddIirCSiK9BZaKivzGYB9vaWhIEDC6AgpA=;5:wJFx/13e0XBTh/1xX4QZex/pp8Y+qh2SXB98D6ItSFKa5cvk3uRJH5w8dcLwvAA0d5lKWptpkN+AGZgS+nZzJIsHgGZOrTnOcwiCLMunXHBwISNDm87SIvaP7PxO08jLoISnFahbr1aXyVKgriD9IA==;24:gGTZvFv6uQaxGPxohxf8RpaP+sSD31o7+nWb5BoVJVx7RtjgigaT6LP++feZHGYhlDsmlqESdM8OLJ7QhzKzYPESWCPSA8SnzKzXxoSzw7c= SpamDiagnosticOutput: 1:99 SpamDiagnosticMetadata: NSPM X-Microsoft-Exchange-Diagnostics: 1;AM4PR0501MB2355;7:rMf1qufvdFYYU7PX7BBRvxjiT5Garv6gErDLzcvNoAJd/EGDqU4s2sJXAV0PzCv5uoVBw9JAjijFECzSEWvOLJDEG1hSkZ0lwj19Gl5vQ92deNQAigBRHKwGhOxclN8+bkeubqa4Zb+bQG8g0iwFyUEMXwI9+YFxrpKr8UAvVBcdoeGyjZHuEz0st67gHtFNYopyOjFu+PSm/+jM6WqvZbEm4SEx/Tgou/tuDXJWwYtHp7IbrmkDhXiL8xFSGQ7N0YMEl02h19PCBzznOcYUi23NTaqlewuWeXeDInweoW6BIOmsUPy8+sE6XiX8tmUnoluyYMCpP6mqAKNP1L3M5xa0WcDfRudPqlAzqqh7LXQ= X-OriginatorOrg: Mellanox.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 23 Oct 2016 12:13:23.7391 (UTC) X-MS-Exchange-CrossTenant-Id: a652971c-7d2e-4d9b-a6a4-d149256f461b X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=a652971c-7d2e-4d9b-a6a4-d149256f461b;Ip=[193.47.165.134];Helo=[mtlcas13.mtl.com] X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM4PR0501MB2355 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Noam Camus Change log --- V1 --> V2 Apply Daniel Lezcano comments: CLOCKSOURCE_OF_DECLARE return value update hotplug callbacks usage squash of 2 first commits. In this version I created new commit to serve as preperation for adding clockevents. This way the last patch is more readable with clockevent content. --- In first version of this driver we supported clocksource for the NPS400. The support for clockevent was taken from Synopsys ARC timer driver. This was good for working with our simulator of NPS400. However in NPS400 ASIC the timers behave differently than simulation. The timers in ASIC are shared between all threads whithin a core and hence need different driver to support this behaviour. The idea of this design is that we got 16 HW threads per core each represented at bimask in a shared register in this core. So when thread wants that next clockevent expiration will produce timer interrupt to itself the correspondance bit in this register should be set. So theoretically if all 16 bits are set then all HW threads will get timer interrupt on next expiration of timer 0. Note that we use Synopsys ARC design naming convention for the timers where: timer0 is used for clockevents timer1 is used for clocksource. Noam Camus (3): soc: Support for NPS HW scheduling clocksource: update "fn" at CLOCKSOURCE_OF_DECLARE() of nps400 timer clocksource: Add clockevent support to NPS400 driver .../bindings/timer/ezchip,nps400-timer.txt | 15 -- .../bindings/timer/ezchip,nps400-timer0.txt | 17 ++ .../bindings/timer/ezchip,nps400-timer1.txt | 15 ++ arch/arc/plat-eznps/include/plat/ctop.h | 2 - drivers/clocksource/timer-nps.c | 253 ++++++++++++++++++-- include/linux/cpuhotplug.h | 1 + include/soc/nps/mtm.h | 59 +++++ 7 files changed, 325 insertions(+), 37 deletions(-) delete mode 100644 Documentation/devicetree/bindings/timer/ezchip,nps400-timer.txt create mode 100644 Documentation/devicetree/bindings/timer/ezchip,nps400-timer0.txt create mode 100644 Documentation/devicetree/bindings/timer/ezchip,nps400-timer1.txt create mode 100644 include/soc/nps/mtm.h From mboxrd@z Thu Jan 1 00:00:00 1970 From: Noam Camus Subject: [PATCH v2 0/3] Add clockevet for timer-nps driver to NPS400 SoC Date: Sun, 23 Oct 2016 15:12:25 +0300 Message-ID: <1477224748-25223-1-git-send-email-noamca@mellanox.com> Mime-Version: 1.0 Content-Type: text/plain Return-path: Sender: linux-kernel-owner@vger.kernel.org To: robh+dt@kernel.org, mark.rutland@arm.com, daniel.lezcano@linaro.org Cc: tglx@linutronix.de, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Noam Camus List-Id: devicetree@vger.kernel.org From: Noam Camus Change log --- V1 --> V2 Apply Daniel Lezcano comments: CLOCKSOURCE_OF_DECLARE return value update hotplug callbacks usage squash of 2 first commits. In this version I created new commit to serve as preperation for adding clockevents. This way the last patch is more readable with clockevent content. --- In first version of this driver we supported clocksource for the NPS400. The support for clockevent was taken from Synopsys ARC timer driver. This was good for working with our simulator of NPS400. However in NPS400 ASIC the timers behave differently than simulation. The timers in ASIC are shared between all threads whithin a core and hence need different driver to support this behaviour. The idea of this design is that we got 16 HW threads per core each represented at bimask in a shared register in this core. So when thread wants that next clockevent expiration will produce timer interrupt to itself the correspondance bit in this register should be set. So theoretically if all 16 bits are set then all HW threads will get timer interrupt on next expiration of timer 0. Note that we use Synopsys ARC design naming convention for the timers where: timer0 is used for clockevents timer1 is used for clocksource. Noam Camus (3): soc: Support for NPS HW scheduling clocksource: update "fn" at CLOCKSOURCE_OF_DECLARE() of nps400 timer clocksource: Add clockevent support to NPS400 driver .../bindings/timer/ezchip,nps400-timer.txt | 15 -- .../bindings/timer/ezchip,nps400-timer0.txt | 17 ++ .../bindings/timer/ezchip,nps400-timer1.txt | 15 ++ arch/arc/plat-eznps/include/plat/ctop.h | 2 - drivers/clocksource/timer-nps.c | 253 ++++++++++++++++++-- include/linux/cpuhotplug.h | 1 + include/soc/nps/mtm.h | 59 +++++ 7 files changed, 325 insertions(+), 37 deletions(-) delete mode 100644 Documentation/devicetree/bindings/timer/ezchip,nps400-timer.txt create mode 100644 Documentation/devicetree/bindings/timer/ezchip,nps400-timer0.txt create mode 100644 Documentation/devicetree/bindings/timer/ezchip,nps400-timer1.txt create mode 100644 include/soc/nps/mtm.h