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From: Jose Ricardo Ziviani <joserz@linux.vnet.ibm.com>
To: qemu-ppc@nongnu.org
Cc: qemu-devel@nongnu.org, david@gibson.dropbear.id.au,
	nikunj@linux.vnet.ibm.com, bharata@linux.vnet.ibm.com
Subject: [Qemu-devel] [PATCH v2 2/4] target-ppc: Implement bcdctn. instruction
Date: Fri, 28 Oct 2016 15:18:02 -0200	[thread overview]
Message-ID: <1477675084-7713-3-git-send-email-joserz@linux.vnet.ibm.com> (raw)
In-Reply-To: <1477675084-7713-1-git-send-email-joserz@linux.vnet.ibm.com>

bcdctn. converts from BCD to National numeric format. National format
uses a byte to represent a digit where the most significant nibble is
always 0x3 and the least sign. nibbles is the digit itself.

Signed-off-by: Jose Ricardo Ziviani <joserz@linux.vnet.ibm.com>
---
 target-ppc/helper.h                 |  1 +
 target-ppc/int_helper.c             | 48 +++++++++++++++++++++++++++++++++++++
 target-ppc/translate/vmx-impl.inc.c | 24 ++++++++++++++++++-
 3 files changed, 72 insertions(+), 1 deletion(-)

diff --git a/target-ppc/helper.h b/target-ppc/helper.h
index 3b23eed..53d1e7a 100644
--- a/target-ppc/helper.h
+++ b/target-ppc/helper.h
@@ -372,6 +372,7 @@ DEF_HELPER_4(vpermxor, void, avr, avr, avr, avr)
 DEF_HELPER_4(bcdadd, i32, avr, avr, avr, i32)
 DEF_HELPER_4(bcdsub, i32, avr, avr, avr, i32)
 DEF_HELPER_3(bcdcfn, i32, avr, avr, i32)
+DEF_HELPER_2(bcdctn, i32, avr, avr)
 
 DEF_HELPER_2(xsadddp, void, env, i32)
 DEF_HELPER_2(xssubdp, void, env, i32)
diff --git a/target-ppc/int_helper.c b/target-ppc/int_helper.c
index 9d620a6..a58ed30 100644
--- a/target-ppc/int_helper.c
+++ b/target-ppc/int_helper.c
@@ -2506,6 +2506,15 @@ static uint8_t get_national_digit(ppc_avr_t *reg, int n)
 #endif
 }
 
+static void set_national_digit(ppc_avr_t *reg, uint8_t val, int n)
+{
+#if defined(HOST_WORDS_BIGENDIAN)
+    reg->u16[8 - n] = val;
+#else
+    reg->u16[n] = val;
+#endif
+}
+
 static int bcd_cmp_mag(ppc_avr_t *a, ppc_avr_t *b)
 {
     int i;
@@ -2679,6 +2688,45 @@ uint32_t helper_bcdcfn(ppc_avr_t *r, ppc_avr_t *b, uint32_t ps)
     return cr;
 }
 
+uint32_t helper_bcdctn(ppc_avr_t *r, ppc_avr_t *b)
+{
+    int i;
+    int cr = 0;
+    int sgnb = bcd_get_sgn(b);
+    int invalid = (sgnb == 0);
+    ppc_avr_t ret = { .u64 = { 0, 0 } };
+
+    int eq_flag = (b->u64[HI_IDX] == 0) && ((b->u64[LO_IDX] >> 4) == 0);
+    int ox_flag = (b->u64[HI_IDX] != 0) || ((b->u64[LO_IDX] >> 32) != 0);
+
+    for (i = 1; i < 8; i++) {
+        set_national_digit(&ret, 0x30 + bcd_get_digit(b, i, &invalid), i);
+
+        if (unlikely(invalid)) {
+            break;
+        }
+    }
+    set_national_digit(&ret, (sgnb == -1) ? NATIONAL_NEG : NATIONAL_PLUS, 0);
+
+    if (!eq_flag) {
+        cr = (sgnb == -1) ? 1 << CRF_LT : 1 << CRF_GT;
+    } else {
+        cr = 1 << CRF_EQ;
+    }
+
+    if (ox_flag) {
+        cr |= 1 << CRF_SO;
+    }
+
+    if (unlikely(invalid)) {
+        cr = 1 << CRF_SO;
+    }
+
+    *r = ret;
+
+    return cr;
+}
+
 void helper_vsbox(ppc_avr_t *r, ppc_avr_t *a)
 {
     int i;
diff --git a/target-ppc/translate/vmx-impl.inc.c b/target-ppc/translate/vmx-impl.inc.c
index 06d28f2..e37fc11 100644
--- a/target-ppc/translate/vmx-impl.inc.c
+++ b/target-ppc/translate/vmx-impl.inc.c
@@ -968,9 +968,29 @@ static void gen_##op(DisasContext *ctx)             \
     tcg_temp_free_i32(ps);                          \
 }
 
+#define GEN_BCD3(op)                                \
+static void gen_##op(DisasContext *ctx)             \
+{                                                   \
+    TCGv_ptr rb, rd;                                \
+                                                    \
+    if (unlikely(!ctx->altivec_enabled)) {          \
+        gen_exception(ctx, POWERPC_EXCP_VPU);       \
+        return;                                     \
+    }                                               \
+                                                    \
+    rb = gen_avr_ptr(rB(ctx->opcode));              \
+    rd = gen_avr_ptr(rD(ctx->opcode));              \
+                                                    \
+    gen_helper_##op(cpu_crf[6], rd, rb);            \
+                                                    \
+    tcg_temp_free_ptr(rb);                          \
+    tcg_temp_free_ptr(rd);                          \
+}
+
 GEN_BCD(bcdadd)
 GEN_BCD(bcdsub)
 GEN_BCD2(bcdcfn)
+GEN_BCD3(bcdctn)
 
 static void gen_xpnd04_1(DisasContext *ctx)
 {
@@ -982,7 +1002,8 @@ static void gen_xpnd04_1(DisasContext *ctx)
     case 4:
         break; /* bcdctz. */
     case 5:
-        break; /* bcdctn. */
+        gen_bcdctn(ctx);
+        break;
     case 6:
         break; /* bcdcfz. */
     case 7:
@@ -1098,3 +1119,4 @@ GEN_VXFORM_DUAL(vsldoi, PPC_ALTIVEC, PPC_NONE,
 #undef GEN_VAFORM_PAIRED
 
 #undef GEN_BCD2
+#undef GEN_BCD3
-- 
2.7.4

  parent reply	other threads:[~2016-10-28 17:18 UTC|newest]

Thread overview: 11+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2016-10-28 17:18 [Qemu-devel] [PATCH v2 0/4] POWER9 TCG enablements - BCD functions part I Jose Ricardo Ziviani
2016-10-28 17:18 ` [Qemu-devel] [PATCH v2 1/4] target-ppc: Implement bcdcfn. instruction Jose Ricardo Ziviani
2016-10-31  0:02   ` David Gibson
2016-10-28 17:18 ` Jose Ricardo Ziviani [this message]
2016-10-31  0:15   ` [Qemu-devel] [PATCH v2 2/4] target-ppc: Implement bcdctn. instruction David Gibson
2016-10-28 17:18 ` [Qemu-devel] [PATCH v2 3/4] target-ppc: Implement bcdcfz. instruction Jose Ricardo Ziviani
2016-10-31  2:28   ` David Gibson
2016-10-28 17:18 ` [Qemu-devel] [PATCH v2 4/4] target-ppc: Implement bcdctz. instruction Jose Ricardo Ziviani
2016-10-31  2:34   ` David Gibson
2016-10-31  2:37 ` [Qemu-devel] [PATCH v2 0/4] POWER9 TCG enablements - BCD functions part I David Gibson
2016-10-31 17:34   ` joserz

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