From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-pf0-x241.google.com (mail-pf0-x241.google.com [IPv6:2607:f8b0:400e:c00::241]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 3t7JTm2mm1zDsrd for ; Tue, 1 Nov 2016 15:41:32 +1100 (AEDT) Received: by mail-pf0-x241.google.com with SMTP id n85so10535607pfi.3 for ; Mon, 31 Oct 2016 21:41:32 -0700 (PDT) From: Suraj Jitindar Singh To: linuxppc-dev@lists.ozlabs.org Cc: kvm-ppc@vger.kernel.org, mpe@ellerman.id.au, benh@kernel.crashing.org, paulus@samba.org, agraf@suse.com, Suraj Jitindar Singh Subject: [PATCH V3 1/2] powerpc: Define new ISA v3.00 logical PVR value and PCR register value Date: Tue, 1 Nov 2016 15:41:02 +1100 Message-Id: <1477975263-29045-2-git-send-email-sjitindarsingh@gmail.com> In-Reply-To: <1477975263-29045-1-git-send-email-sjitindarsingh@gmail.com> References: <1477975263-29045-1-git-send-email-sjitindarsingh@gmail.com> List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , ISA 3.00 adds the logical PVR value 0x0f000005, so add a definition for this. Define PCR_ARCH_207 to reflect ISA 2.07 compatibility mode in the processor compatibility register (PCR). Also define a dummy ISA 3.00 compatibility mode PCR_ARCH_300 to be used in the next patch to help with determining the PCR value. Signed-off-by: Suraj Jitindar Singh --- arch/powerpc/include/asm/reg.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/powerpc/include/asm/reg.h b/arch/powerpc/include/asm/reg.h index 9cd4e8c..3fb6192 100644 --- a/arch/powerpc/include/asm/reg.h +++ b/arch/powerpc/include/asm/reg.h @@ -377,6 +377,8 @@ #define PCR_VEC_DIS (1ul << (63-0)) /* Vec. disable (bit NA since POWER8) */ #define PCR_VSX_DIS (1ul << (63-1)) /* VSX disable (bit NA since POWER8) */ #define PCR_TM_DIS (1ul << (63-2)) /* Trans. memory disable (POWER8) */ +#define PCR_ARCH_300 0x10 /* Dummy Architecture 3.00 */ +#define PCR_ARCH_207 0x8 /* Architecture 2.07 */ #define PCR_ARCH_206 0x4 /* Architecture 2.06 */ #define PCR_ARCH_205 0x2 /* Architecture 2.05 */ #define SPRN_HEIR 0x153 /* Hypervisor Emulated Instruction Register */ @@ -1218,6 +1220,7 @@ #define PVR_ARCH_206 0x0f000003 #define PVR_ARCH_206p 0x0f100003 #define PVR_ARCH_207 0x0f000004 +#define PVR_ARCH_300 0x0f000005 /* Macros for setting and retrieving special purpose registers */ #ifndef __ASSEMBLY__ -- 2.5.5 From mboxrd@z Thu Jan 1 00:00:00 1970 From: Suraj Jitindar Singh Date: Tue, 01 Nov 2016 04:41:02 +0000 Subject: [PATCH V3 1/2] powerpc: Define new ISA v3.00 logical PVR value and PCR register value Message-Id: <1477975263-29045-2-git-send-email-sjitindarsingh@gmail.com> List-Id: References: <1477975263-29045-1-git-send-email-sjitindarsingh@gmail.com> In-Reply-To: <1477975263-29045-1-git-send-email-sjitindarsingh@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: linuxppc-dev@lists.ozlabs.org Cc: kvm-ppc@vger.kernel.org, mpe@ellerman.id.au, benh@kernel.crashing.org, paulus@samba.org, agraf@suse.com, Suraj Jitindar Singh ISA 3.00 adds the logical PVR value 0x0f000005, so add a definition for this. Define PCR_ARCH_207 to reflect ISA 2.07 compatibility mode in the processor compatibility register (PCR). Also define a dummy ISA 3.00 compatibility mode PCR_ARCH_300 to be used in the next patch to help with determining the PCR value. Signed-off-by: Suraj Jitindar Singh --- arch/powerpc/include/asm/reg.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/powerpc/include/asm/reg.h b/arch/powerpc/include/asm/reg.h index 9cd4e8c..3fb6192 100644 --- a/arch/powerpc/include/asm/reg.h +++ b/arch/powerpc/include/asm/reg.h @@ -377,6 +377,8 @@ #define PCR_VEC_DIS (1ul << (63-0)) /* Vec. disable (bit NA since POWER8) */ #define PCR_VSX_DIS (1ul << (63-1)) /* VSX disable (bit NA since POWER8) */ #define PCR_TM_DIS (1ul << (63-2)) /* Trans. memory disable (POWER8) */ +#define PCR_ARCH_300 0x10 /* Dummy Architecture 3.00 */ +#define PCR_ARCH_207 0x8 /* Architecture 2.07 */ #define PCR_ARCH_206 0x4 /* Architecture 2.06 */ #define PCR_ARCH_205 0x2 /* Architecture 2.05 */ #define SPRN_HEIR 0x153 /* Hypervisor Emulated Instruction Register */ @@ -1218,6 +1220,7 @@ #define PVR_ARCH_206 0x0f000003 #define PVR_ARCH_206p 0x0f100003 #define PVR_ARCH_207 0x0f000004 +#define PVR_ARCH_300 0x0f000005 /* Macros for setting and retrieving special purpose registers */ #ifndef __ASSEMBLY__ -- 2.5.5