From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:58336) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1c2EJb-0003na-Ba for qemu-devel@nongnu.org; Thu, 03 Nov 2016 05:28:08 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1c2EJa-0001tz-Ga for qemu-devel@nongnu.org; Thu, 03 Nov 2016 05:28:07 -0400 Received: from mx1.redhat.com ([209.132.183.28]:43380) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1c2EJa-0001td-Az for qemu-devel@nongnu.org; Thu, 03 Nov 2016 05:28:06 -0400 From: Jason Wang Date: Thu, 3 Nov 2016 17:27:20 +0800 Message-Id: <1478165243-4767-9-git-send-email-jasowang@redhat.com> In-Reply-To: <1478165243-4767-1-git-send-email-jasowang@redhat.com> References: <1478165243-4767-1-git-send-email-jasowang@redhat.com> Subject: [Qemu-devel] [PATCH V2 08/11] acpi: add ATSR for q35 List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: mst@redhat.com, peterx@redhat.com, wexu@redhat.com, qemu-devel@nongnu.org Cc: vkaplans@redhat.com, pbonzini@redhat.com, cornelia.huck@de.ibm.com, Jason Wang This patch provides ATSR which was a requirement for software that wants to enable ATS on endpoint devices behind a Root Port. This is done simply by setting ALL_PORTS which indicates all PCI-Express Root Ports support ATS transactions. Signed-off-by: Jason Wang --- hw/i386/acpi-build.c | 9 +++++++++ include/hw/acpi/acpi-defs.h | 12 ++++++++++++ 2 files changed, 21 insertions(+) diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c index 5cd1da9..2d10b0f 100644 --- a/hw/i386/acpi-build.c +++ b/hw/i386/acpi-build.c @@ -2568,6 +2568,7 @@ build_dmar_q35(GArray *table_data, BIOSLinker *linker) AcpiTableDmar *dmar; AcpiDmarHardwareUnit *drhd; + AcpiDmarRootPortATS *atsr; uint8_t dmar_flags = 0; X86IOMMUState *iommu = x86_iommu_get_default(); AcpiDmarDeviceScope *scope = NULL; @@ -2600,6 +2601,14 @@ build_dmar_q35(GArray *table_data, BIOSLinker *linker) scope->bus = Q35_PSEUDO_BUS_PLATFORM; scope->path[0] = cpu_to_le16(Q35_PSEUDO_DEVFN_IOAPIC); + if (iommu->dt_supported) { + atsr = acpi_data_push(table_data, sizeof(*atsr)); + atsr->type = cpu_to_le16(ACPI_DMAR_TYPE_ATSR); + atsr->length = cpu_to_le16(sizeof(*atsr)); + atsr->flags = ACPI_DMAR_ATSR_ALL_PORTS; + atsr->pci_segment = cpu_to_le16(0); + } + build_header(linker, table_data, (void *)(table_data->data + dmar_start), "DMAR", table_data->len - dmar_start, 1, NULL, NULL); } diff --git a/include/hw/acpi/acpi-defs.h b/include/hw/acpi/acpi-defs.h index d1d1d61..420ea36 100644 --- a/include/hw/acpi/acpi-defs.h +++ b/include/hw/acpi/acpi-defs.h @@ -635,8 +635,20 @@ struct AcpiDmarHardwareUnit { } QEMU_PACKED; typedef struct AcpiDmarHardwareUnit AcpiDmarHardwareUnit; +/* Type 2: Root Port ATS Capability Reporting Structure */ +struct AcpiDmarRootPortATS { + uint16_t type; + uint16_t length; + uint8_t flags; + uint8_t reserved; + uint16_t pci_segment; + AcpiDmarDeviceScope scope[0]; +} QEMU_PACKED; +typedef struct AcpiDmarRootPortATS AcpiDmarRootPortATS; + /* Masks for Flags field above */ #define ACPI_DMAR_INCLUDE_PCI_ALL 1 +#define ACPI_DMAR_ATSR_ALL_PORTS 1 /* * Input Output Remapping Table (IORT) -- 2.7.4