From mboxrd@z Thu Jan 1 00:00:00 1970 From: Priyanka Jain Date: Thu, 3 Nov 2016 16:32:24 +0530 Subject: [U-Boot] [PATCH 0/6][v3] Update LS2080A SoC code to support LS2088A SoC Message-ID: <1478170950-16083-1-git-send-email-priyanka.jain@nxp.com> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de LS2088A is similar to LS2080A SoC with some differences like 1)Timer controller offset is different 2)It has A72 cores 3)Process to release secondary cores is different 4)LS2088A SoC has TZASC controller In preparation of using same binary for LS2088A and LS2080A as both are using same development boards. code is update to detect difference based on SVR at runtime Priyanka Jain (6): armv8: lsch3: Add generic get_svr() in assembly armv8: lsch3: Use SVR based timer base address detection armv8: fsl-layerscape: Update TZASC registers type armv8: fsl-layerscape : Check SVR for initializing TZASC armv8: fsl-layerscape: Add NXP LS2088A SoC support armv8/fsl-lsch3: Update code to release secondary cores arch/arm/cpu/armv8/fsl-layerscape/cpu.c | 18 +++-- arch/arm/cpu/armv8/fsl-layerscape/cpu.h | 1 + arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc | 58 +++++++++++++++++ arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S | 50 ++++++++++---- arch/arm/cpu/armv8/fsl-layerscape/mp.c | 68 ++++++++++++++++++- arch/arm/cpu/armv8/fsl-layerscape/soc.c | 6 +- arch/arm/include/asm/arch-fsl-layerscape/config.h | 1 + arch/arm/include/asm/arch-fsl-layerscape/cpu.h | 4 + .../include/asm/arch-fsl-layerscape/immap_lsch3.h | 9 ++- arch/arm/include/asm/arch-fsl-layerscape/soc.h | 12 +++- board/freescale/ls2080a/MAINTAINERS | 2 +- board/freescale/ls2080aqds/MAINTAINERS | 2 +- board/freescale/ls2080aqds/README | 12 ++-- board/freescale/ls2080ardb/MAINTAINERS | 2 +- board/freescale/ls2080ardb/README | 8 +- 15 files changed, 205 insertions(+), 48 deletions(-) -- Changes for v3: Add patch for implementing get_svr in assembly Update checks in code where svr is compared Add comments related to scratchrw[6] register in code Changes for v2: Rename LS2080A_LS2085A_TIMER_ADDR to SYS_FSL_LS2080A_LS2085A_TIMER_ADDR in first patch 1.7.4.1