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From: Priyanka Jain <priyanka.jain@nxp.com>
To: u-boot@lists.denx.de
Subject: [U-Boot] [PATCH 3/6][v3] armv8: fsl-layerscape: Update TZASC registers type
Date: Thu, 3 Nov 2016 16:32:27 +0530	[thread overview]
Message-ID: <1478170950-16083-4-git-send-email-priyanka.jain@nxp.com> (raw)
In-Reply-To: <1478170950-16083-1-git-send-email-priyanka.jain@nxp.com>

TZASC registers like TZASC_GATE_KEEPER, TZASC_REGION_ATTRIBUTES
are 32-bit regsiters.
So while doing register load-store operations, 32-bit intermediate
register, w0 should be used.
Update x0 register to w0 register type.

Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
---
 arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S |   28 +++++++++++++-------------
 1 files changed, 14 insertions(+), 14 deletions(-)

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S
index ee20c27..75b9878 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S
+++ b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S
@@ -148,26 +148,26 @@ ENTRY(lowlevel_init)
 	 * 	 placeholders.
 	 */
 	ldr	x1, =TZASC_GATE_KEEPER(0)
-	ldr	x0, [x1]		/* Filter 0 Gate Keeper Register */
-	orr	x0, x0, #1 << 0		/* Set open_request for Filter 0 */
-	str	x0, [x1]
+	ldr	w0, [x1]		/* Filter 0 Gate Keeper Register */
+	orr	w0, w0, #1 << 0		/* Set open_request for Filter 0 */
+	str	w0, [x1]
 
 	ldr	x1, =TZASC_GATE_KEEPER(1)
-	ldr	x0, [x1]		/* Filter 0 Gate Keeper Register */
-	orr	x0, x0, #1 << 0		/* Set open_request for Filter 0 */
-	str	x0, [x1]
+	ldr	w0, [x1]		/* Filter 0 Gate Keeper Register */
+	orr	w0, w0, #1 << 0		/* Set open_request for Filter 0 */
+	str	w0, [x1]
 
 	ldr	x1, =TZASC_REGION_ATTRIBUTES_0(0)
-	ldr	x0, [x1]		/* Region-0 Attributes Register */
-	orr	x0, x0, #1 << 31	/* Set Sec global write en, Bit[31] */
-	orr	x0, x0, #1 << 30	/* Set Sec global read en, Bit[30] */
-	str	x0, [x1]
+	ldr	w0, [x1]		/* Region-0 Attributes Register */
+	orr	w0, w0, #1 << 31	/* Set Sec global write en, Bit[31] */
+	orr	w0, w0, #1 << 30	/* Set Sec global read en, Bit[30] */
+	str	w0, [x1]
 
 	ldr	x1, =TZASC_REGION_ATTRIBUTES_0(1)
-	ldr	x0, [x1]		/* Region-1 Attributes Register */
-	orr	x0, x0, #1 << 31	/* Set Sec global write en, Bit[31] */
-	orr	x0, x0, #1 << 30	/* Set Sec global read en, Bit[30] */
-	str	x0, [x1]
+	ldr	w0, [x1]		/* Region-1 Attributes Register */
+	orr	w0, w0, #1 << 31	/* Set Sec global write en, Bit[31] */
+	orr	w0, w0, #1 << 30	/* Set Sec global read en, Bit[30] */
+	str	w0, [x1]
 
 	ldr	x1, =TZASC_REGION_ID_ACCESS_0(0)
 	ldr	w0, [x1]		/* Region-0 Access Register */
-- 
1.7.4.1

  parent reply	other threads:[~2016-11-03 11:02 UTC|newest]

Thread overview: 9+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2016-11-03 11:02 [U-Boot] [PATCH 0/6][v3] Update LS2080A SoC code to support LS2088A SoC Priyanka Jain
2016-11-03 11:02 ` [U-Boot] [PATCH 1/6][v3] armv8: lsch3: Add generic get_svr() in assembly Priyanka Jain
2016-11-14 16:50   ` york sun
2016-11-15 10:39     ` Priyanka Jain
2016-11-03 11:02 ` [U-Boot] [PATCH 2/6][v3] armv8: lsch3: Use SVR based timer base address detection Priyanka Jain
2016-11-03 11:02 ` Priyanka Jain [this message]
2016-11-03 11:02 ` [U-Boot] [PATCH 4/6][v3] armv8: fsl-layerscape : Check SVR for initializing TZASC Priyanka Jain
2016-11-03 11:02 ` [U-Boot] [PATCH 5/6][v3] armv8: fsl-layerscape: Add NXP LS2088A SoC support Priyanka Jain
2016-11-03 11:02 ` [U-Boot] [PATCH 6/6][v3] armv8/fsl-lsch3: Update code to release secondary cores Priyanka Jain

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