From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:45482) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1c75qd-0004EV-0D for qemu-devel@nongnu.org; Wed, 16 Nov 2016 14:26:21 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1c75qb-0005xA-MG for qemu-devel@nongnu.org; Wed, 16 Nov 2016 14:26:18 -0500 Received: from mail-wm0-x243.google.com ([2a00:1450:400c:c09::243]:36650) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1c75qb-0005wz-GA for qemu-devel@nongnu.org; Wed, 16 Nov 2016 14:26:17 -0500 Received: by mail-wm0-x243.google.com with SMTP id m203so14289629wma.3 for ; Wed, 16 Nov 2016 11:26:17 -0800 (PST) Sender: Richard Henderson From: Richard Henderson Date: Wed, 16 Nov 2016 20:25:28 +0100 Message-Id: <1479324335-2074-19-git-send-email-rth@twiddle.net> In-Reply-To: <1479324335-2074-1-git-send-email-rth@twiddle.net> References: <1479324335-2074-1-git-send-email-rth@twiddle.net> Subject: [Qemu-devel] [PATCH 18/25] tcg/aarch64: Handle ctz and clz opcodes List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: Claudio Fontana Cc: Claudio Fontana Signed-off-by: Richard Henderson --- tcg/aarch64/tcg-target.h | 8 ++++---- tcg/aarch64/tcg-target.inc.c | 47 ++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 51 insertions(+), 4 deletions(-) diff --git a/tcg/aarch64/tcg-target.h b/tcg/aarch64/tcg-target.h index 976f493..9d6b00f 100644 --- a/tcg/aarch64/tcg-target.h +++ b/tcg/aarch64/tcg-target.h @@ -62,8 +62,8 @@ typedef enum { #define TCG_TARGET_HAS_eqv_i32 1 #define TCG_TARGET_HAS_nand_i32 0 #define TCG_TARGET_HAS_nor_i32 0 -#define TCG_TARGET_HAS_clz_i32 0 -#define TCG_TARGET_HAS_ctz_i32 0 +#define TCG_TARGET_HAS_clz_i32 1 +#define TCG_TARGET_HAS_ctz_i32 1 #define TCG_TARGET_HAS_deposit_i32 1 #define TCG_TARGET_HAS_extract_i32 1 #define TCG_TARGET_HAS_sextract_i32 1 @@ -96,8 +96,8 @@ typedef enum { #define TCG_TARGET_HAS_eqv_i64 1 #define TCG_TARGET_HAS_nand_i64 0 #define TCG_TARGET_HAS_nor_i64 0 -#define TCG_TARGET_HAS_clz_i64 0 -#define TCG_TARGET_HAS_ctz_i64 0 +#define TCG_TARGET_HAS_clz_i64 1 +#define TCG_TARGET_HAS_ctz_i64 1 #define TCG_TARGET_HAS_deposit_i64 1 #define TCG_TARGET_HAS_extract_i64 1 #define TCG_TARGET_HAS_sextract_i64 1 diff --git a/tcg/aarch64/tcg-target.inc.c b/tcg/aarch64/tcg-target.inc.c index c0e9890..51abc1b 100644 --- a/tcg/aarch64/tcg-target.inc.c +++ b/tcg/aarch64/tcg-target.inc.c @@ -206,6 +206,9 @@ static int tcg_target_const_match(tcg_target_long val, TCGType type, if ((ct & TCG_CT_CONST_MONE) && val == -1) { return 1; } + if ((ct & TCG_CT_CONST_WSZ) && val == (type ? 64 : 32)) { + return 1; + } return 0; } @@ -344,8 +347,12 @@ typedef enum { /* Conditional select instructions. */ I3506_CSEL = 0x1a800000, I3506_CSINC = 0x1a800400, + I3506_CSINV = 0x5a800000, + I3506_CSNEG = 0x5a800400, /* Data-processing (1 source) instructions. */ + I3507_CLZ = 0x5ac01000, + I3507_RBIT = 0x5ac00000, I3507_REV16 = 0x5ac00400, I3507_REV32 = 0x5ac00800, I3507_REV64 = 0x5ac00c00, @@ -998,6 +1005,32 @@ static inline void tcg_out_mb(TCGContext *s, TCGArg a0) tcg_out32(s, sync[a0 & TCG_MO_ALL]); } +static void tcg_out_clz(TCGContext *s, TCGType ext, TCGReg d, + TCGReg a, TCGArg b, bool const_b) +{ + if (const_b && b == (ext ? 64 : 32)) { + tcg_out_insn(s, 3507, CLZ, ext, d, a); + } else { + AArch64Insn sel = I3506_CSEL; + + tcg_out_cmp(s, ext, a, 0, 1); + tcg_out_insn(s, 3507, CLZ, ext, TCG_REG_TMP, a); + + if (const_b) { + if (b == -1) { + b = TCG_REG_XZR; + sel = I3506_CSINV; + } else if (b == 0) { + b = TCG_REG_XZR; + } else { + tcg_out_movi(s, ext, d, b); + b = d; + } + } + tcg_out_insn_3506(s, sel, ext, d, TCG_REG_TMP, b, TCG_COND_NE); + } +} + #ifdef CONFIG_SOFTMMU /* helper signature: helper_ret_ld_mmu(CPUState *env, target_ulong addr, * TCGMemOpIdx oi, uintptr_t ra) @@ -1564,6 +1597,16 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, } break; + case INDEX_op_clz_i64: + case INDEX_op_clz_i32: + tcg_out_clz(s, ext, a0, a1, a2, c2); + break; + case INDEX_op_ctz_i64: + case INDEX_op_ctz_i32: + tcg_out_insn(s, 3507, RBIT, ext, TCG_REG_TMP, a1); + tcg_out_clz(s, ext, a0, TCG_REG_TMP, a2, c2); + break; + case INDEX_op_brcond_i32: a1 = (int32_t)a1; /* FALLTHRU */ @@ -1755,11 +1798,15 @@ static const TCGTargetOpDef aarch64_op_defs[] = { { INDEX_op_sar_i32, { "r", "r", "ri" } }, { INDEX_op_rotl_i32, { "r", "r", "ri" } }, { INDEX_op_rotr_i32, { "r", "r", "ri" } }, + { INDEX_op_clz_i32, { "r", "r", "rAL" } }, + { INDEX_op_ctz_i32, { "r", "r", "rAL" } }, { INDEX_op_shl_i64, { "r", "r", "ri" } }, { INDEX_op_shr_i64, { "r", "r", "ri" } }, { INDEX_op_sar_i64, { "r", "r", "ri" } }, { INDEX_op_rotl_i64, { "r", "r", "ri" } }, { INDEX_op_rotr_i64, { "r", "r", "ri" } }, + { INDEX_op_clz_i64, { "r", "r", "rAL" } }, + { INDEX_op_ctz_i64, { "r", "r", "rAL" } }, { INDEX_op_brcond_i32, { "r", "rA" } }, { INDEX_op_brcond_i64, { "r", "rA" } }, -- 2.7.4