From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:45630) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1c75qh-0004Jv-Nj for qemu-devel@nongnu.org; Wed, 16 Nov 2016 14:26:27 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1c75qg-00061F-25 for qemu-devel@nongnu.org; Wed, 16 Nov 2016 14:26:23 -0500 Received: from mail-wm0-x243.google.com ([2a00:1450:400c:c09::243]:32797) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1c75qf-00060g-PY for qemu-devel@nongnu.org; Wed, 16 Nov 2016 14:26:21 -0500 Received: by mail-wm0-x243.google.com with SMTP id u144so14304387wmu.0 for ; Wed, 16 Nov 2016 11:26:21 -0800 (PST) Received: from bigtime.twiddle.net ([87.111.149.139]) by smtp.gmail.com with ESMTPSA id 197sm686930wmy.16.2016.11.16.11.26.19 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 16 Nov 2016 11:26:19 -0800 (PST) Sender: Richard Henderson From: Richard Henderson Date: Wed, 16 Nov 2016 20:25:31 +0100 Message-Id: <1479324335-2074-22-git-send-email-rth@twiddle.net> In-Reply-To: <1479324335-2074-1-git-send-email-rth@twiddle.net> References: <1479324335-2074-1-git-send-email-rth@twiddle.net> Subject: [Qemu-devel] [PATCH 21/25] tcg/s390: Handle clz opcode List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Signed-off-by: Richard Henderson --- tcg/s390/tcg-target.h | 2 +- tcg/s390/tcg-target.inc.c | 36 +++++++++++++++++++++++++++++++++++- 2 files changed, 36 insertions(+), 2 deletions(-) diff --git a/tcg/s390/tcg-target.h b/tcg/s390/tcg-target.h index 3ac2dc9..22500ba 100644 --- a/tcg/s390/tcg-target.h +++ b/tcg/s390/tcg-target.h @@ -110,7 +110,7 @@ extern uint64_t s390_facilities; #define TCG_TARGET_HAS_eqv_i64 0 #define TCG_TARGET_HAS_nand_i64 0 #define TCG_TARGET_HAS_nor_i64 0 -#define TCG_TARGET_HAS_clz_i64 0 +#define TCG_TARGET_HAS_clz_i64 (s390_facilities & FACILITY_EXT_IMM) #define TCG_TARGET_HAS_ctz_i64 0 #define TCG_TARGET_HAS_deposit_i64 (s390_facilities & FACILITY_GEN_INST_EXT) #define TCG_TARGET_HAS_extract_i64 (s390_facilities & FACILITY_GEN_INST_EXT) diff --git a/tcg/s390/tcg-target.inc.c b/tcg/s390/tcg-target.inc.c index f4c510e..81d9563 100644 --- a/tcg/s390/tcg-target.inc.c +++ b/tcg/s390/tcg-target.inc.c @@ -50,7 +50,7 @@ #define TCG_REG_NONE 0 /* A scratch register that may be be used throughout the backend. */ -#define TCG_TMP0 TCG_REG_R14 +#define TCG_TMP0 TCG_REG_R1 #ifndef CONFIG_SOFTMMU #define TCG_GUEST_BASE_REG TCG_REG_R13 @@ -133,6 +133,7 @@ typedef enum S390Opcode { RRE_DLR = 0xb997, RRE_DSGFR = 0xb91d, RRE_DSGR = 0xb90d, + RRE_FLOGR = 0xb983, RRE_LGBR = 0xb906, RRE_LCGR = 0xb903, RRE_LGFR = 0xb914, @@ -1245,6 +1246,33 @@ static void tgen_movcond(TCGContext *s, TCGType type, TCGCond c, TCGReg dest, } } +static void tgen_clz(TCGContext *s, TCGReg dest, TCGReg a1, + TCGArg a2, int a2const) +{ + /* Since this sets both R and R+1, we have no choice but to store the + result into R0, allowing R1 == TCG_TMP0 to be clobbered as well. */ + QEMU_BUILD_BUG_ON(TCG_TMP0 != TCG_REG_R1); + tcg_out_insn(s, RRE, FLOGR, TCG_REG_R0, a1); + + if (a2const && a2 == 64) { + tcg_out_mov(s, TCG_TYPE_I64, dest, TCG_REG_R0); + } else { + if (a2const) { + tcg_out_movi(s, TCG_TYPE_I64, dest, a2); + } else { + tcg_out_mov(s, TCG_TYPE_I64, dest, a2); + } + if (s390_facilities & FACILITY_LOAD_ON_COND) { + /* Emit: if (one bit found) dest = r0. */ + tcg_out_insn(s, RRF, LOCGR, dest, TCG_REG_R0, 2); + } else { + /* Emit: if (no one bit found) goto over; dest = r0; over: */ + tcg_out_insn(s, RI, BRC, 8, (4 + 4) >> 1); + tcg_out_insn(s, RRE, LGR, dest, TCG_REG_R0); + } + } +} + static void tgen_deposit(TCGContext *s, TCGReg dest, TCGReg src, int ofs, int len, int z) { @@ -2185,6 +2213,10 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, tgen_extract(s, args[0], args[1], args[2], args[3]); break; + case INDEX_op_clz_i64: + tgen_clz(s, args[0], args[1], args[2], const_args[2]); + break; + case INDEX_op_mb: /* The host memory model is quite strong, we simply need to serialize the instruction stream. */ @@ -2308,6 +2340,8 @@ static const TCGTargetOpDef s390_op_defs[] = { { INDEX_op_bswap32_i64, { "r", "r" } }, { INDEX_op_bswap64_i64, { "r", "r" } }, + { INDEX_op_clz_i64, { "r", "r", "ri" } }, + { INDEX_op_add2_i64, { "r", "r", "0", "1", "rA", "r" } }, { INDEX_op_sub2_i64, { "r", "r", "0", "1", "rA", "r" } }, -- 2.7.4