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From: Richard Henderson <rth@twiddle.net>
To: qemu-devel@nongnu.org
Subject: [Qemu-devel] [PATCH 22/25] tcg: Add helpers for clrsb
Date: Wed, 16 Nov 2016 20:25:32 +0100	[thread overview]
Message-ID: <1479324335-2074-23-git-send-email-rth@twiddle.net> (raw)
In-Reply-To: <1479324335-2074-1-git-send-email-rth@twiddle.net>

The number of actual invocations does not warrent an opcode,
and the backends generating it.  But at least we can eliminate
redundant helpers.

Signed-off-by: Richard Henderson <rth@twiddle.net>
---
 tcg-runtime.c     | 10 ++++++++++
 tcg/tcg-op.c      | 28 ++++++++++++++++++++++++++++
 tcg/tcg-op.h      |  4 ++++
 tcg/tcg-runtime.h |  2 ++
 4 files changed, 44 insertions(+)

diff --git a/tcg-runtime.c b/tcg-runtime.c
index eb3bade..c8b98df 100644
--- a/tcg-runtime.c
+++ b/tcg-runtime.c
@@ -121,6 +121,16 @@ uint64_t HELPER(ctz_i64)(uint64_t arg, uint64_t zero_val)
     return arg ? ctz64(arg) : zero_val;
 }
 
+uint32_t HELPER(clrsb_i32)(uint32_t arg)
+{
+    return clrsb32(arg);
+}
+
+uint64_t HELPER(clrsb_i64)(uint64_t arg)
+{
+    return clrsb64(arg);
+}
+
 void HELPER(exit_atomic)(CPUArchState *env)
 {
     cpu_loop_exit_atomic(ENV_GET_CPU(env), GETPC());
diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c
index b45095c..728c4b3 100644
--- a/tcg/tcg-op.c
+++ b/tcg/tcg-op.c
@@ -489,6 +489,20 @@ void tcg_gen_ctzi_i32(TCGv_i32 ret, TCGv_i32 arg1, uint32_t arg2)
     tcg_temp_free_i32(t);
 }
 
+void tcg_gen_clrsb_i32(TCGv_i32 ret, TCGv_i32 arg)
+{
+    if (TCG_TARGET_HAS_clz_i32) {
+        TCGv_i32 t = tcg_temp_new_i32();
+        tcg_gen_sari_i32(t, arg, 31);
+        tcg_gen_xor_i32(t, t, arg);
+        tcg_gen_clzi_i32(t, t, 32);
+        tcg_gen_subi_i32(ret, t, 1);
+        tcg_temp_free_i32(t);
+    } else {
+        gen_helper_clrsb_i32(ret, arg);
+    }
+}
+
 void tcg_gen_rotl_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
 {
     if (TCG_TARGET_HAS_rot_i32) {
@@ -1789,6 +1803,20 @@ void tcg_gen_ctzi_i64(TCGv_i64 ret, TCGv_i64 arg1, uint64_t arg2)
     }
 }
 
+void tcg_gen_clrsb_i64(TCGv_i64 ret, TCGv_i64 arg)
+{
+    if (TCG_TARGET_HAS_clz_i64 || TCG_TARGET_HAS_clz_i32) {
+        TCGv_i64 t = tcg_temp_new_i64();
+        tcg_gen_sari_i64(t, arg, 63);
+        tcg_gen_xor_i64(t, t, arg);
+        tcg_gen_clzi_i64(t, t, 64);
+        tcg_gen_subi_i64(ret, t, 1);
+        tcg_temp_free_i64(t);
+    } else {
+        gen_helper_clrsb_i64(ret, arg);
+    }
+}
+
 void tcg_gen_rotl_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
 {
     if (TCG_TARGET_HAS_rot_i64) {
diff --git a/tcg/tcg-op.h b/tcg/tcg-op.h
index 7a24e84..c2f3db9 100644
--- a/tcg/tcg-op.h
+++ b/tcg/tcg-op.h
@@ -290,6 +290,7 @@ void tcg_gen_clz_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2);
 void tcg_gen_ctz_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2);
 void tcg_gen_clzi_i32(TCGv_i32 ret, TCGv_i32 arg1, uint32_t arg2);
 void tcg_gen_ctzi_i32(TCGv_i32 ret, TCGv_i32 arg1, uint32_t arg2);
+void tcg_gen_clrsb_i32(TCGv_i32 ret, TCGv_i32 arg);
 void tcg_gen_rotl_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2);
 void tcg_gen_rotli_i32(TCGv_i32 ret, TCGv_i32 arg1, unsigned arg2);
 void tcg_gen_rotr_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2);
@@ -477,6 +478,7 @@ void tcg_gen_clz_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2);
 void tcg_gen_ctz_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2);
 void tcg_gen_clzi_i64(TCGv_i64 ret, TCGv_i64 arg1, uint64_t arg2);
 void tcg_gen_ctzi_i64(TCGv_i64 ret, TCGv_i64 arg1, uint64_t arg2);
+void tcg_gen_clrsb_i64(TCGv_i64 ret, TCGv_i64 arg);
 void tcg_gen_rotl_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2);
 void tcg_gen_rotli_i64(TCGv_i64 ret, TCGv_i64 arg1, unsigned arg2);
 void tcg_gen_rotr_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2);
@@ -970,6 +972,7 @@ void tcg_gen_atomic_xor_fetch_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, TCGMemOp);
 #define tcg_gen_ctz_tl tcg_gen_ctz_i64
 #define tcg_gen_clzi_tl tcg_gen_clzi_i64
 #define tcg_gen_ctzi_tl tcg_gen_ctzi_i64
+#define tcg_gen_clrsb_tl tcg_gen_clrsb_i64
 #define tcg_gen_rotl_tl tcg_gen_rotl_i64
 #define tcg_gen_rotli_tl tcg_gen_rotli_i64
 #define tcg_gen_rotr_tl tcg_gen_rotr_i64
@@ -1065,6 +1068,7 @@ void tcg_gen_atomic_xor_fetch_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, TCGMemOp);
 #define tcg_gen_ctz_tl tcg_gen_ctz_i32
 #define tcg_gen_clzi_tl tcg_gen_clzi_i32
 #define tcg_gen_ctzi_tl tcg_gen_ctzi_i32
+#define tcg_gen_clrsb_tl tcg_gen_clrsb_i32
 #define tcg_gen_rotl_tl tcg_gen_rotl_i32
 #define tcg_gen_rotli_tl tcg_gen_rotli_i32
 #define tcg_gen_rotr_tl tcg_gen_rotr_i32
diff --git a/tcg/tcg-runtime.h b/tcg/tcg-runtime.h
index eb1cd76..0d30f1a 100644
--- a/tcg/tcg-runtime.h
+++ b/tcg/tcg-runtime.h
@@ -19,6 +19,8 @@ DEF_HELPER_FLAGS_2(clz_i32, TCG_CALL_NO_RWG_SE, i32, i32, i32)
 DEF_HELPER_FLAGS_2(ctz_i32, TCG_CALL_NO_RWG_SE, i32, i32, i32)
 DEF_HELPER_FLAGS_2(clz_i64, TCG_CALL_NO_RWG_SE, i64, i64, i64)
 DEF_HELPER_FLAGS_2(ctz_i64, TCG_CALL_NO_RWG_SE, i64, i64, i64)
+DEF_HELPER_FLAGS_1(clrsb_i32, TCG_CALL_NO_RWG_SE, i32, i32)
+DEF_HELPER_FLAGS_1(clrsb_i64, TCG_CALL_NO_RWG_SE, i64, i64)
 
 DEF_HELPER_FLAGS_1(exit_atomic, TCG_CALL_NO_WG, noreturn, env)
 
-- 
2.7.4

  parent reply	other threads:[~2016-11-16 19:26 UTC|newest]

Thread overview: 40+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2016-11-16 19:25 [Qemu-devel] [PATCH 00/25] tcg: Handle clz, ctz, and clrsb generically Richard Henderson
2016-11-16 19:25 ` [Qemu-devel] [PATCH 01/25] tcg: Add clz and ctz opcodes Richard Henderson
2016-11-21 15:11   ` Alex Bennée
2016-11-21 16:05     ` Richard Henderson
2016-11-16 19:25 ` [Qemu-devel] [PATCH 02/25] target-alpha: Use the ctz and clz opcodes Richard Henderson
2016-11-16 19:25 ` [Qemu-devel] [PATCH 03/25] target-cris: Use clz opcode Richard Henderson
2016-11-16 19:25 ` [Qemu-devel] [PATCH 04/25] target-microblaze: " Richard Henderson
2016-11-16 19:25 ` [Qemu-devel] [PATCH 05/25] target-mips: " Richard Henderson
2016-11-16 19:25 ` [Qemu-devel] [PATCH 06/25] target-openrisc: Use clz and ctz opcodes Richard Henderson
2016-11-16 19:25 ` [Qemu-devel] [PATCH 07/25] target-ppc: " Richard Henderson
2016-11-17  3:09   ` David Gibson
2016-11-16 19:25 ` [Qemu-devel] [PATCH 08/25] target-s390x: Use clz opcode Richard Henderson
2016-11-16 19:25 ` [Qemu-devel] [PATCH 09/25] target-tilegx: Use clz and ctz opcodes Richard Henderson
2016-11-16 19:25 ` [Qemu-devel] [PATCH 10/25] target-tricore: Use clz opcode Richard Henderson
2016-11-17 14:42   ` Bastian Koppelmann
2016-11-17 15:47     ` Bastian Koppelmann
2016-11-16 19:25 ` [Qemu-devel] [PATCH 11/25] target-unicore32: " Richard Henderson
2016-11-16 19:25 ` [Qemu-devel] [PATCH 12/25] target-xtensa: " Richard Henderson
2016-11-16 19:25 ` [Qemu-devel] [PATCH 13/25] target-arm: " Richard Henderson
2016-11-16 19:25 ` [Qemu-devel] [PATCH 14/25] target-i386: Use clz and ctz opcodes Richard Henderson
2016-11-16 19:25 ` [Qemu-devel] [PATCH 15/25] disas/i386.c: Handle tzcnt Richard Henderson
2016-11-16 19:25 ` [Qemu-devel] [PATCH 16/25] tcg/i386: Handle ctz and clz opcodes Richard Henderson
2016-11-17 16:50   ` Bastian Koppelmann
2016-11-17 19:53     ` Richard Henderson
2016-11-17 19:59       ` Richard Henderson
2016-11-17 22:09         ` Bastian Koppelmann
2016-11-17 23:03           ` Richard Henderson
2016-11-18 12:48             ` Bastian Koppelmann
2016-11-21 10:37               ` Richard Henderson
2016-11-16 19:25 ` [Qemu-devel] [PATCH 17/25] tcg/ppc: " Richard Henderson
2016-11-16 19:25 ` [Qemu-devel] [PATCH 18/25] tcg/aarch64: " Richard Henderson
2016-11-17 11:53   ` Richard Henderson
2016-11-22 10:41     ` Alex Bennée
2016-11-16 19:25 ` [Qemu-devel] [PATCH 19/25] tcg/arm: " Richard Henderson
2016-11-16 19:25 ` [Qemu-devel] [PATCH 20/25] tcg/mips: Handle clz opcode Richard Henderson
2016-11-16 19:25 ` [Qemu-devel] [PATCH 21/25] tcg/s390: " Richard Henderson
2016-11-16 19:25 ` Richard Henderson [this message]
2016-11-16 19:25 ` [Qemu-devel] [PATCH 23/25] target-arm: Use clrsb helper Richard Henderson
2016-11-16 19:25 ` [Qemu-devel] [PATCH 24/25] target-tricore: " Richard Henderson
2016-11-16 19:25 ` [Qemu-devel] [PATCH 25/25] target-xtensa: " Richard Henderson

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