From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:45230) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1c75qM-0003x7-Jr for qemu-devel@nongnu.org; Wed, 16 Nov 2016 14:26:06 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1c75qL-0005qL-LX for qemu-devel@nongnu.org; Wed, 16 Nov 2016 14:26:02 -0500 Received: from mail-wm0-x244.google.com ([2a00:1450:400c:c09::244]:35600) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1c75qL-0005q8-FH for qemu-devel@nongnu.org; Wed, 16 Nov 2016 14:26:01 -0500 Received: by mail-wm0-x244.google.com with SMTP id a20so14358740wme.2 for ; Wed, 16 Nov 2016 11:26:01 -0800 (PST) Sender: Richard Henderson From: Richard Henderson Date: Wed, 16 Nov 2016 20:25:16 +0100 Message-Id: <1479324335-2074-7-git-send-email-rth@twiddle.net> In-Reply-To: <1479324335-2074-1-git-send-email-rth@twiddle.net> References: <1479324335-2074-1-git-send-email-rth@twiddle.net> Subject: [Qemu-devel] [PATCH 06/25] target-openrisc: Use clz and ctz opcodes List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: Jia Liu Cc: Jia Liu Signed-off-by: Richard Henderson --- target-openrisc/helper.h | 2 -- target-openrisc/int_helper.c | 19 ------------------- target-openrisc/translate.c | 6 ++++-- 3 files changed, 4 insertions(+), 23 deletions(-) diff --git a/target-openrisc/helper.h b/target-openrisc/helper.h index f53fa21..bcc7245 100644 --- a/target-openrisc/helper.h +++ b/target-openrisc/helper.h @@ -54,8 +54,6 @@ FOP_CMP(ge) #undef FOP_CMP /* int */ -DEF_HELPER_FLAGS_1(ff1, 0, tl, tl) -DEF_HELPER_FLAGS_1(fl1, 0, tl, tl) DEF_HELPER_FLAGS_3(mul32, 0, i32, env, i32, i32) /* interrupt */ diff --git a/target-openrisc/int_helper.c b/target-openrisc/int_helper.c index 4d1f958..ba0fd27 100644 --- a/target-openrisc/int_helper.c +++ b/target-openrisc/int_helper.c @@ -24,25 +24,6 @@ #include "exception.h" #include "qemu/host-utils.h" -target_ulong HELPER(ff1)(target_ulong x) -{ -/*#ifdef TARGET_OPENRISC64 - return x ? ctz64(x) + 1 : 0; -#else*/ - return x ? ctz32(x) + 1 : 0; -/*#endif*/ -} - -target_ulong HELPER(fl1)(target_ulong x) -{ -/* not used yet, open it when we need or64. */ -/*#ifdef TARGET_OPENRISC64 - return 64 - clz64(x); -#else*/ - return 32 - clz32(x); -/*#endif*/ -} - uint32_t HELPER(mul32)(CPUOpenRISCState *env, uint32_t ra, uint32_t rb) { diff --git a/target-openrisc/translate.c b/target-openrisc/translate.c index 229361a..03fa7db 100644 --- a/target-openrisc/translate.c +++ b/target-openrisc/translate.c @@ -602,11 +602,13 @@ static void dec_calc(DisasContext *dc, uint32_t insn) switch (op1) { case 0x00: /* l.ff1 */ LOG_DIS("l.ff1 r%d, r%d, r%d\n", rd, ra, rb); - gen_helper_ff1(cpu_R[rd], cpu_R[ra]); + tcg_gen_ctzi_tl(cpu_R[rd], cpu_R[ra], -1); + tcg_gen_addi_tl(cpu_R[rd], cpu_R[rd], 1); break; case 0x01: /* l.fl1 */ LOG_DIS("l.fl1 r%d, r%d, r%d\n", rd, ra, rb); - gen_helper_fl1(cpu_R[rd], cpu_R[ra]); + tcg_gen_clzi_tl(cpu_R[rd], cpu_R[ra], TARGET_LONG_BITS); + tcg_gen_subfi_tl(cpu_R[rd], TARGET_LONG_BITS, cpu_R[rd]); break; default: -- 2.7.4