From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:57209) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1c76V3-0006Cc-6n for qemu-devel@nongnu.org; Wed, 16 Nov 2016 15:08:06 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1c76V0-0003na-0H for qemu-devel@nongnu.org; Wed, 16 Nov 2016 15:08:05 -0500 Received: from mx0b-001b2d01.pphosted.com ([148.163.158.5]:41922 helo=mx0a-001b2d01.pphosted.com) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1c76Uz-0003nW-RI for qemu-devel@nongnu.org; Wed, 16 Nov 2016 15:08:01 -0500 Received: from pps.filterd (m0098420.ppops.net [127.0.0.1]) by mx0b-001b2d01.pphosted.com (8.16.0.17/8.16.0.17) with SMTP id uAGK4AtG088323 for ; Wed, 16 Nov 2016 15:08:01 -0500 Received: from e24smtp03.br.ibm.com (e24smtp03.br.ibm.com [32.104.18.24]) by mx0b-001b2d01.pphosted.com with ESMTP id 26rx5w05p1-1 (version=TLSv1.2 cipher=AES256-SHA bits=256 verify=NOT) for ; Wed, 16 Nov 2016 15:08:01 -0500 Received: from localhost by e24smtp03.br.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! Violators will be prosecuted for from ; Wed, 16 Nov 2016 18:07:59 -0200 From: Jose Ricardo Ziviani Date: Wed, 16 Nov 2016 18:07:28 -0200 In-Reply-To: <1479326850-8369-1-git-send-email-joserz@linux.vnet.ibm.com> References: <1479326850-8369-1-git-send-email-joserz@linux.vnet.ibm.com> Message-Id: <1479326850-8369-3-git-send-email-joserz@linux.vnet.ibm.com> Subject: [Qemu-devel] [PATCH 2/4] target-ppc: Implement bcdctsq. instruction List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-ppc@nongnu.org Cc: qemu-devel@nongnu.org, david@gibson.dropbear.id.au, nikunj@linux.vnet.ibm.com, bharata@linux.vnet.ibm.com bcdctsq.: Decimal convert to signed quadword. It is possible to convert packed decimal values to signed quadwords. Signed-off-by: Jose Ricardo Ziviani --- target-ppc/helper.h | 1 + target-ppc/int_helper.c | 39 +++++++++++++++++++++++++++++++++++++ target-ppc/translate/vmx-impl.inc.c | 7 +++++++ 3 files changed, 47 insertions(+) diff --git a/target-ppc/helper.h b/target-ppc/helper.h index 87f533c..503f257 100644 --- a/target-ppc/helper.h +++ b/target-ppc/helper.h @@ -383,6 +383,7 @@ DEF_HELPER_3(bcdctn, i32, avr, avr, i32) DEF_HELPER_3(bcdcfz, i32, avr, avr, i32) DEF_HELPER_3(bcdctz, i32, avr, avr, i32) DEF_HELPER_3(bcdcfsq, i32, avr, avr, i32) +DEF_HELPER_3(bcdctsq, i32, avr, avr, i32) DEF_HELPER_2(xsadddp, void, env, i32) DEF_HELPER_2(xssubdp, void, env, i32) diff --git a/target-ppc/int_helper.c b/target-ppc/int_helper.c index db65a51..1025438 100644 --- a/target-ppc/int_helper.c +++ b/target-ppc/int_helper.c @@ -2922,6 +2922,45 @@ uint32_t helper_bcdcfsq(ppc_avr_t *r, ppc_avr_t *b, uint32_t ps) return cr; } +uint32_t helper_bcdctsq(ppc_avr_t *r, ppc_avr_t *b, uint32_t ps) +{ + uint8_t i; + int cr = 0; + uint64_t hi = 0; + int sgnb = bcd_get_sgn(b); + int invalid = (sgnb == 0); + ppc_avr_t ret = { .u64 = { 0, 0 } }; + + ret.u64[LO_IDX] = bcd_get_digit(b, 31, &invalid); + for (i = 30; i > 0; i--) { + mulu64(&ret.u64[LO_IDX], &hi, + ret.u64[LO_IDX], 10ULL); + + ret.u64[HI_IDX] = (ret.u64[HI_IDX]) ? ret.u64[HI_IDX] * 10 + hi : hi; + ret.u64[LO_IDX] += bcd_get_digit(b, i, &invalid); + + if (unlikely(invalid)) { + break; + } + } + + if (sgnb == -1) { + if (ret.s64[HI_IDX] > 0) { + ret.s64[HI_IDX] = -ret.s64[HI_IDX]; + } else { + ret.s64[LO_IDX] = -ret.s64[LO_IDX]; + } + } + + cr = bcd_cmp_zero(b); + + if (unlikely(invalid)) { + cr = 1 << CRF_SO; + } + + return cr; +} + void helper_vsbox(ppc_avr_t *r, ppc_avr_t *a) { int i; diff --git a/target-ppc/translate/vmx-impl.inc.c b/target-ppc/translate/vmx-impl.inc.c index 36141e5..1579b58 100644 --- a/target-ppc/translate/vmx-impl.inc.c +++ b/target-ppc/translate/vmx-impl.inc.c @@ -990,10 +990,14 @@ GEN_BCD2(bcdctn) GEN_BCD2(bcdcfz) GEN_BCD2(bcdctz) GEN_BCD2(bcdcfsq) +GEN_BCD2(bcdctsq) static void gen_xpnd04_1(DisasContext *ctx) { switch (opc4(ctx->opcode)) { + case 0: + gen_bcdctsq(ctx); + break; case 2: gen_bcdcfsq(ctx); break; @@ -1018,6 +1022,9 @@ static void gen_xpnd04_1(DisasContext *ctx) static void gen_xpnd04_2(DisasContext *ctx) { switch (opc4(ctx->opcode)) { + case 0: + gen_bcdctsq(ctx); + break; case 2: gen_bcdcfsq(ctx); break; -- 2.7.4