[PATCH] drm/i915/bxt: Use smaller 8/3X MIPI clock divider value for dual link.

[PATCH] drm/i915/bxt: Use smaller 8/3X MIPI clock divider value for dual link.

[Bob Paauwe]

For a single link (channel) DSI panel we want to use a larger divider
and keep the clock rate down to save power when in DPI/video mode. However
when using a dual-link DSI panel this may reduce the clock below what's
needed to get a stable display.

Use the smaller divider (faster clock) for either DBI/command mode or
when using dual link.

Signed-off-by: Bob Paauwe <bob.j.paauwe@intel.com>
---
 drivers/gpu/drm/i915/intel_dsi_pll.c | 9 +++++++--
 1 file changed, 7 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_dsi_pll.c b/drivers/gpu/drm/i915/intel_dsi_pll.c
index 56eff60..9edc57e 100644
--- a/drivers/gpu/drm/i915/intel_dsi_pll.c
+++ b/drivers/gpu/drm/i915/intel_dsi_pll.c
@@ -414,8 +414,13 @@ static void bxt_dsi_program_clocks(struct drm_device *dev, enum port port,
 	rx_div_lower = rx_div & RX_DIVIDER_BIT_1_2;
 	rx_div_upper = (rx_div & RX_DIVIDER_BIT_3_4) >> 2;
 
-	/* As per bpsec program the 8/3X clock divider to the below value */
-	if (dev_priv->vbt.dsi.config->is_cmd_mode)
+	/*
+	 * Set the 8/3X clock to divide by 3 for DBI mode as it needs a
+	 * faster clock than DPI mode. However, dual link panels also
+	 * need the faster clock, even when in DPI mode.
+	 */
+	if (dev_priv->vbt.dsi.config->is_cmd_mode ||
+	    dev_priv->vbt.dsi.config->dual_link)
 		mipi_8by3_divider = 0x2;
 	else
 		mipi_8by3_divider = 0x3;
-- 
2.7.4

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✗ Fi.CI.BAT: warning for drm/i915/bxt: Use smaller 8/3X MIPI clock divider value for dual link.

[Patchwork]

== Series Details ==

Series: drm/i915/bxt: Use smaller 8/3X MIPI clock divider value for dual link.
URL   : https://patchwork.freedesktop.org/series/15573/
State : warning

== Summary ==

Series 15573v1 drm/i915/bxt: Use smaller 8/3X MIPI clock divider value for dual link.
https://patchwork.freedesktop.org/api/1.0/series/15573/revisions/1/mbox/

Test kms_pipe_crc_basic:
        Subgroup suspend-read-crc-pipe-c:
                pass       -> DMESG-WARN (fi-skl-6770hq)

fi-bdw-5557u     total:244  pass:229  dwarn:0   dfail:0   fail:0   skip:15 
fi-bsw-n3050     total:244  pass:204  dwarn:0   dfail:0   fail:0   skip:40 
fi-bxt-t5700     total:244  pass:216  dwarn:0   dfail:0   fail:0   skip:28 
fi-byt-j1900     total:244  pass:216  dwarn:0   dfail:0   fail:0   skip:28 
fi-byt-n2820     total:244  pass:212  dwarn:0   dfail:0   fail:0   skip:32 
fi-hsw-4770      total:244  pass:224  dwarn:0   dfail:0   fail:0   skip:20 
fi-hsw-4770r     total:244  pass:224  dwarn:0   dfail:0   fail:0   skip:20 
fi-ilk-650       total:244  pass:191  dwarn:0   dfail:0   fail:0   skip:53 
fi-ivb-3520m     total:244  pass:222  dwarn:0   dfail:0   fail:0   skip:22 
fi-ivb-3770      total:244  pass:222  dwarn:0   dfail:0   fail:0   skip:22 
fi-kbl-7200u     total:244  pass:222  dwarn:0   dfail:0   fail:0   skip:22 
fi-skl-6260u     total:244  pass:230  dwarn:0   dfail:0   fail:0   skip:14 
fi-skl-6700hq    total:244  pass:223  dwarn:0   dfail:0   fail:0   skip:21 
fi-skl-6700k     total:244  pass:222  dwarn:1   dfail:0   fail:0   skip:21 
fi-skl-6770hq    total:244  pass:229  dwarn:1   dfail:0   fail:0   skip:14 
fi-snb-2520m     total:244  pass:212  dwarn:0   dfail:0   fail:0   skip:32 
fi-snb-2600      total:244  pass:211  dwarn:0   dfail:0   fail:0   skip:33 

67029cdb14b252079153fc53eedf9bd9274acfe1 drm-intel-nightly: 2016y-11m-18d-20h-52m-35s UTC integration manifest
2a1e0ad drm/i915/bxt: Use smaller 8/3X MIPI clock divider value for dual link.

== Logs ==

For more details see: https://intel-gfx-ci.01.org/CI/Patchwork_3061/
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Re: [PATCH] drm/i915/bxt: Use smaller 8/3X MIPI clock divider value for dual link.

[David Weinehall]

On Fri, Nov 18, 2016 at 02:11:56PM -0800, Bob Paauwe wrote:
> For a single link (channel) DSI panel we want to use a larger divider
> and keep the clock rate down to save power when in DPI/video mode. However
> when using a dual-link DSI panel this may reduce the clock below what's
> needed to get a stable display.
> 
> Use the smaller divider (faster clock) for either DBI/command mode or
> when using dual link.
> 
> Signed-off-by: Bob Paauwe <bob.j.paauwe@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_dsi_pll.c | 9 +++++++--
>  1 file changed, 7 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_dsi_pll.c b/drivers/gpu/drm/i915/intel_dsi_pll.c
> index 56eff60..9edc57e 100644
> --- a/drivers/gpu/drm/i915/intel_dsi_pll.c
> +++ b/drivers/gpu/drm/i915/intel_dsi_pll.c
> @@ -414,8 +414,13 @@ static void bxt_dsi_program_clocks(struct drm_device *dev, enum port port,
>  	rx_div_lower = rx_div & RX_DIVIDER_BIT_1_2;
>  	rx_div_upper = (rx_div & RX_DIVIDER_BIT_3_4) >> 2;
>  
> -	/* As per bpsec program the 8/3X clock divider to the below value */
> -	if (dev_priv->vbt.dsi.config->is_cmd_mode)
> +	/*
> +	 * Set the 8/3X clock to divide by 3 for DBI mode as it needs a

Shouldn't this be "divide by 2", to be consistent with the code
and the commit message?

> +	 * faster clock than DPI mode. However, dual link panels also
> +	 * need the faster clock, even when in DPI mode.
> +	 */
> +	if (dev_priv->vbt.dsi.config->is_cmd_mode ||
> +	    dev_priv->vbt.dsi.config->dual_link)
>  		mipi_8by3_divider = 0x2;
>  	else
>  		mipi_8by3_divider = 0x3;


Kind regards, David Weinehall
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Re: [PATCH] drm/i915/bxt: Use smaller 8/3X MIPI clock divider value for dual link.

[Bob Paauwe]

On Sat, 19 Nov 2016 11:20:56 +0100
David Weinehall <tao@kernel.org> wrote:

> On Fri, Nov 18, 2016 at 02:11:56PM -0800, Bob Paauwe wrote:
> > For a single link (channel) DSI panel we want to use a larger divider
> > and keep the clock rate down to save power when in DPI/video mode. However
> > when using a dual-link DSI panel this may reduce the clock below what's
> > needed to get a stable display.
> > 
> > Use the smaller divider (faster clock) for either DBI/command mode or
> > when using dual link.
> > 
> > Signed-off-by: Bob Paauwe <bob.j.paauwe@intel.com>
> > ---
> >  drivers/gpu/drm/i915/intel_dsi_pll.c | 9 +++++++--
> >  1 file changed, 7 insertions(+), 2 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/intel_dsi_pll.c b/drivers/gpu/drm/i915/intel_dsi_pll.c
> > index 56eff60..9edc57e 100644
> > --- a/drivers/gpu/drm/i915/intel_dsi_pll.c
> > +++ b/drivers/gpu/drm/i915/intel_dsi_pll.c
> > @@ -414,8 +414,13 @@ static void bxt_dsi_program_clocks(struct drm_device *dev, enum port port,
> >  	rx_div_lower = rx_div & RX_DIVIDER_BIT_1_2;
> >  	rx_div_upper = (rx_div & RX_DIVIDER_BIT_3_4) >> 2;
> >  
> > -	/* As per bpsec program the 8/3X clock divider to the below value */
> > -	if (dev_priv->vbt.dsi.config->is_cmd_mode)
> > +	/*
> > +	 * Set the 8/3X clock to divide by 3 for DBI mode as it needs a  
> 
> Shouldn't this be "divide by 2", to be consistent with the code
> and the commit message?

The value programmed into the bits isn't the same as the what the value
represents.  In this case we program the bits to 10b to use the by 3
divider and 11b to use the by 4 divider. 

It can also be programmed with 01b for a by 2 divider but that's not
used.

The 0x2 and 0x3 would probably be better represented by defines to
make that clear, but I'd think would be a separate patch.

> 
> > +	 * faster clock than DPI mode. However, dual link panels also
> > +	 * need the faster clock, even when in DPI mode.
> > +	 */
> > +	if (dev_priv->vbt.dsi.config->is_cmd_mode ||
> > +	    dev_priv->vbt.dsi.config->dual_link)
> >  		mipi_8by3_divider = 0x2;
> >  	else
> >  		mipi_8by3_divider = 0x3;  
> 
> 
> Kind regards, David Weinehall



-- 
--
Bob Paauwe                  
Bob.J.Paauwe@intel.com
IOTG / PED Software Organization
Intel Corp.  Folsom, CA
(916) 356-6193    

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