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From: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com>
To: qemu-ppc@nongnu.org, david@gibson.dropbear.id.au, rth@twiddle.net
Cc: qemu-devel@nongnu.org, nikunj@linux.vnet.ibm.com,
	bharata@linux.vnet.ibm.com
Subject: [Qemu-devel] [PATCH v1 ppc-for-2.9 00/10] POWER9 TCG enablements - part8
Date: Wed, 23 Nov 2016 17:07:09 +0530	[thread overview]
Message-ID: <1479901039-7113-1-git-send-email-nikunj@linux.vnet.ibm.com> (raw)

This series contains 18 new instructions for POWER9 ISA3.0
    Vector Extract Left/Right Indexed
    VSX Scalar Compare Exponents
    VSX Scalar Compare Quad-Precision
    Load/Store VSX Vector 
    Load/Store VSX Scalar

Changelog:
v0:
* Change dq/ds-form decoding for primary opcode 0x3D
* Rename CR Field defines, as at every place it was
  using bit shifts.
* Use symbolic constants in xscmp*
* Fix bug in exception handling for QNaN
* Define EXTRACT128 within CONFIG_INT128

Patches
=======
01-03: Consolidation/Fixes
   04: 
      xscmpexpdp: VSX Scalar Compare Exponents Double-Precision
      xscmpexpqp: VSX Scalar Compare Exponents Quad-Precision
   05:
      xscmpoqp: VSX Scalar Compare Ordered Quad-Precision
      xscmpuqp: VSX Scalar Compare Unordered Quad-Precision
   06:
      lxsd:  Load VSX Scalar Dword
      lxssp: Load VSX Scalar Single Precision
   07:
      stxsd:  Store VSX Scalar Dword
      stxssp: Store VSX Scalar Single Precision
   08:
      lxv:   Load VSX Vector
      lxvx:  Load VSX Vector Indexed
      stxv:  Store VSX Vector
      stxvx: Store VSX Vector Indexed
   09: 
      vextublx:  Vector Extract Unsigned Byte Left
      vextuhlx:  Vector Extract Unsigned Halfword Left
      vextuwlx:  Vector Extract Unsigned Word Left
   10: 
      vextubrx: Vector Extract Unsigned Byte Right-Indexed
      vextuhrx: Vector Extract Unsigned  Halfword Right-Indexed
      vextuwrx: Vector Extract Unsigned Word Right-Indexed

Avinesh Kumar (1):
  target-ppc: add vextu[bhw]lx instructions

Bharata B Rao (4):
  target-ppc: Consolidate instruction decode helpers
  target-ppc: Fix xscmpodp and xscmpudp instructions
  target-ppc: Add xscmpexp[dp,qp] instructions
  target-ppc: Add xscmpoqp and xscmpuqp instructions

Hariharan T.S (1):
  target-ppc: add vextu[bhw]rx instructions

Nikunj A Dadhania (4):
  target-ppc: rename CRF_* defines as CRF_*_BIT
  target-ppc: implement lxsd and lxssp instructions
  target-ppc: implement stxsd and stxssp
  target-ppc: implement lxv/lxvx and stxv/stxvx

 target-ppc/cpu.h                    |  21 ++--
 target-ppc/fpu_helper.c             | 169 ++++++++++++++++++++++----
 target-ppc/helper.h                 |  10 ++
 target-ppc/int_helper.c             | 155 +++++++++++++++++++++---
 target-ppc/internal.h               | 152 ++++++++++++++++++++++++
 target-ppc/translate.c              | 230 +++++++++++-------------------------
 target-ppc/translate/fp-ops.inc.c   |   2 -
 target-ppc/translate/vmx-impl.inc.c |  23 ++++
 target-ppc/translate/vmx-ops.inc.c  |   8 +-
 target-ppc/translate/vsx-impl.inc.c |  96 +++++++++++++++
 target-ppc/translate/vsx-ops.inc.c  |  10 ++
 11 files changed, 666 insertions(+), 210 deletions(-)

-- 
2.7.4

             reply	other threads:[~2016-11-23 11:37 UTC|newest]

Thread overview: 17+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2016-11-23 11:37 Nikunj A Dadhania [this message]
2016-11-23 11:37 ` [Qemu-devel] [PATCH v1 01/10] target-ppc: Consolidate instruction decode helpers Nikunj A Dadhania
2016-11-23 11:37 ` [Qemu-devel] [PATCH v1 02/10] target-ppc: rename CRF_* defines as CRF_*_BIT Nikunj A Dadhania
2016-11-24  0:23   ` David Gibson
2016-11-23 11:37 ` [Qemu-devel] [PATCH v1 03/10] target-ppc: Fix xscmpodp and xscmpudp instructions Nikunj A Dadhania
2016-11-23 11:37 ` [Qemu-devel] [PATCH v1 04/10] target-ppc: Add xscmpexp[dp, qp] instructions Nikunj A Dadhania
2016-11-23 11:37 ` [Qemu-devel] [PATCH v1 05/10] target-ppc: Add xscmpoqp and xscmpuqp instructions Nikunj A Dadhania
2016-11-23 11:37 ` [Qemu-devel] [PATCH v1 06/10] target-ppc: implement lxsd and lxssp instructions Nikunj A Dadhania
2016-11-23 11:37 ` [Qemu-devel] [PATCH v1 07/10] target-ppc: implement stxsd and stxssp Nikunj A Dadhania
2016-11-23 11:37 ` [Qemu-devel] [PATCH v1 08/10] target-ppc: implement lxv/lxvx and stxv/stxvx Nikunj A Dadhania
2016-11-23 11:37 ` [Qemu-devel] [PATCH v1 09/10] target-ppc: add vextu[bhw]lx instructions Nikunj A Dadhania
2016-11-24  1:02   ` David Gibson
2016-11-24  5:53     ` Nikunj A Dadhania
2016-11-24  8:14       ` Richard Henderson
2016-11-24  8:22         ` Nikunj A Dadhania
2016-11-23 11:37 ` [Qemu-devel] [PATCH v1 10/10] target-ppc: add vextu[bhw]rx instructions Nikunj A Dadhania
2016-11-24  0:56 ` [Qemu-devel] [PATCH v1 ppc-for-2.9 00/10] POWER9 TCG enablements - part8 David Gibson

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