From mboxrd@z Thu Jan  1 00:00:00 1970
From: Dario Faggioli <dario.faggioli@citrix.com>
Subject: Re: [PATCH v3 01/15] docs: L2 Cache Allocation
 Technology (CAT) feature document.
Date: Tue, 29 Nov 2016 13:25:22 +0100
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To: Yi Sun <yi.y.sun@linux.intel.com>
Cc: wei.liu2@citrix.com, he.chen@linux.intel.com, andrew.cooper3@citrix.com, ian.jackson@eu.citrix.com, jbeulich@suse.com, chao.p.peng@linux.intel.com, xen-devel@lists.xenproject.org
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On Tue, 2016-11-29 at 13:20 +0800, Yi Sun wrote:
> On 16-11-25 18:19:17, Dario Faggioli wrote:
> > On Fri, 2016-11-11 at 16:33 -0500, Konrad Rzeszutek Wilk wrote:
> > > Intel Problem Solver Resolver (PSR)
> > >=20
> > Wasn't it the 'Intel Probabilistic Silicon Reorganizer' ? :-D :-D
> >=20
> It is 'Intel Platform Shared Resource' indeed. :-)
>=20
Well, that's sad to hear. I'd love Inter to introduce something like a
Probabilistic Silicon Reorganizer... That would be a lot of fun! :-)

> > Also, it would be really good to have similar documents for the
> > other
> > PSR features we have upstream already (perhaps finding a way for
> > not
> > duplicating all the common information).
> >=20
> Besides L2 CAT, there are L3 CAT and CDP features for allocation
> tech.
> Also, there are CMT/MBM features for monitoring tech.=20
>
Yep, I know them.

> We will discuss
> these to check if we can add these feature documents step by step.
>=20
That would be awesome!

Regards,
Dario
--=20
<<This happens because I choose it to happen!>> (Raistlin Majere)
-----------------------------------------------------------------
Dario Faggioli, Ph.D, http://about.me/dario.faggioli
Senior Software Engineer, Citrix Systems R&D Ltd., Cambridge (UK)
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