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From: York Sun <york.sun@nxp.com>
To: u-boot@lists.denx.de
Subject: [U-Boot] [PATCH 02/11] powerpc: mpc85xx: Convert CONFIG_SYS_CCSRBAR_DEFAULT to Kconfig option
Date: Fri, 2 Dec 2016 13:37:43 -0800	[thread overview]
Message-ID: <1480714672-21632-3-git-send-email-york.sun@nxp.com> (raw)
In-Reply-To: <1480714672-21632-1-git-send-email-york.sun@nxp.com>

Move default value definitions to to Kconfig SYS_CCSRBAR_DEFAULT.

Signed-off-by: York Sun <york.sun@nxp.com>
---

 arch/powerpc/cpu/mpc85xx/Kconfig          | 50 +++++++++++++++++++++++++++++++
 arch/powerpc/include/asm/config_mpc85xx.h | 41 -------------------------
 doc/README.ramboot-ppc85xx                |  4 +--
 3 files changed, 52 insertions(+), 43 deletions(-)

diff --git a/arch/powerpc/cpu/mpc85xx/Kconfig b/arch/powerpc/cpu/mpc85xx/Kconfig
index 9a5cd85..1d2e027 100644
--- a/arch/powerpc/cpu/mpc85xx/Kconfig
+++ b/arch/powerpc/cpu/mpc85xx/Kconfig
@@ -471,6 +471,56 @@ config MAX_CPUS
 	  cores, count the reserved ports. This will allocate enough memory
 	  in spin table to properly handle all cores.
 
+config SYS_CCSRBAR_DEFAULT
+	hex "Default CCSRBAR address"
+	default	0xff700000 if	ARCH_BSC9131	|| \
+				ARCH_BSC9132	|| \
+				ARCH_C29X	|| \
+				ARCH_MPC8536	|| \
+				ARCH_MPC8540	|| \
+				ARCH_MPC8541	|| \
+				ARCH_MPC8544	|| \
+				ARCH_MPC8548	|| \
+				ARCH_MPC8555	|| \
+				ARCH_MPC8560	|| \
+				ARCH_MPC8568	|| \
+				ARCH_MPC8569	|| \
+				ARCH_MPC8572	|| \
+				ARCH_P1010	|| \
+				ARCH_P1011	|| \
+				ARCH_P1020	|| \
+				ARCH_P1021	|| \
+				ARCH_P1022	|| \
+				ARCH_P1024	|| \
+				ARCH_P1025	|| \
+				ARCH_P2020
+	default 0xff600000 if	ARCH_P1023
+	default 0xfe000000 if	ARCH_B4420	|| \
+				ARCH_B4860	|| \
+				ARCH_P2041	|| \
+				ARCH_P3041	|| \
+				ARCH_P4080	|| \
+				ARCH_P5020	|| \
+				ARCH_P5040	|| \
+				ARCH_T1013	|| \
+				ARCH_T1014	|| \
+				ARCH_T1020	|| \
+				ARCH_T1022	|| \
+				ARCH_T1023	|| \
+				ARCH_T1024	|| \
+				ARCH_T1040	|| \
+				ARCH_T1042	|| \
+				ARCH_T2080	|| \
+				ARCH_T2081	|| \
+				ARCH_T4160	|| \
+				ARCH_T4240
+	default 0xe0000000 if ARCH_QEMU_E500
+	help
+		Default value of CCSRBAR comes from power-on-reset. It
+		is fixed on each SoC. Some SoCs can have different value
+		if changed by pre-boot regime. The value here must match
+		the current value in SoC. If not sure, do not change.
+
 source "board/freescale/b4860qds/Kconfig"
 source "board/freescale/bsc9131rdb/Kconfig"
 source "board/freescale/bsc9132qds/Kconfig"
diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h
index c92bc1e..474fd1a 100644
--- a/arch/powerpc/include/asm/config_mpc85xx.h
+++ b/arch/powerpc/include/asm/config_mpc85xx.h
@@ -9,10 +9,6 @@
 
 /* SoC specific defines for Freescale MPC85xx (PQ3) and QorIQ processors */
 
-#ifdef CONFIG_SYS_CCSRBAR_DEFAULT
-#error "Do not define CONFIG_SYS_CCSRBAR_DEFAULT in the board header file."
-#endif
-
 /*
  * This macro should be removed when we no longer care about backwards
  * compatibility with older operating systems.
@@ -39,27 +35,23 @@
 #define CONFIG_SYS_FSL_NUM_LAWS		12
 #define CONFIG_SYS_PPC_E500_DEBUG_TLB	1
 #define CONFIG_SYS_FSL_SEC_COMPAT	2
-#define CONFIG_SYS_CCSRBAR_DEFAULT	0xff700000
 #define CONFIG_SYS_FSL_ERRATUM_A004508
 #define CONFIG_SYS_FSL_ERRATUM_A005125
 
 #elif defined(CONFIG_ARCH_MPC8540)
 #define CONFIG_SYS_FSL_NUM_LAWS		8
 #define CONFIG_SYS_FSL_DDRC_GEN1
-#define CONFIG_SYS_CCSRBAR_DEFAULT	0xff700000
 
 #elif defined(CONFIG_ARCH_MPC8541)
 #define CONFIG_SYS_FSL_NUM_LAWS		8
 #define CONFIG_SYS_FSL_DDRC_GEN1
 #define CONFIG_SYS_FSL_SEC_COMPAT	2
-#define CONFIG_SYS_CCSRBAR_DEFAULT	0xff700000
 
 #elif defined(CONFIG_ARCH_MPC8544)
 #define CONFIG_SYS_FSL_NUM_LAWS		10
 #define CONFIG_SYS_FSL_DDRC_GEN2
 #define CONFIG_SYS_PPC_E500_DEBUG_TLB	0
 #define CONFIG_SYS_FSL_SEC_COMPAT	2
-#define CONFIG_SYS_CCSRBAR_DEFAULT	0xff700000
 #define CONFIG_SYS_FSL_ERRATUM_A005125
 
 #elif defined(CONFIG_ARCH_MPC8548)
@@ -67,7 +59,6 @@
 #define CONFIG_SYS_FSL_DDRC_GEN2
 #define CONFIG_SYS_PPC_E500_DEBUG_TLB	0
 #define CONFIG_SYS_FSL_SEC_COMPAT	2
-#define CONFIG_SYS_CCSRBAR_DEFAULT	0xff700000
 #define CONFIG_SYS_FSL_ERRATUM_NMG_DDR120
 #define CONFIG_SYS_FSL_ERRATUM_NMG_LBC103
 #define CONFIG_SYS_FSL_ERRATUM_NMG_ETSEC129
@@ -84,12 +75,10 @@
 #define CONFIG_SYS_FSL_NUM_LAWS		8
 #define CONFIG_SYS_FSL_DDRC_GEN1
 #define CONFIG_SYS_FSL_SEC_COMPAT	2
-#define CONFIG_SYS_CCSRBAR_DEFAULT	0xff700000
 
 #elif defined(CONFIG_ARCH_MPC8560)
 #define CONFIG_SYS_FSL_NUM_LAWS		8
 #define CONFIG_SYS_FSL_DDRC_GEN1
-#define CONFIG_SYS_CCSRBAR_DEFAULT	0xff700000
 
 #elif defined(CONFIG_ARCH_MPC8568)
 #define CONFIG_SYS_FSL_NUM_LAWS		10
@@ -98,7 +87,6 @@
 #define QE_MURAM_SIZE			0x10000UL
 #define MAX_QE_RISC			2
 #define QE_NUM_OF_SNUM			28
-#define CONFIG_SYS_CCSRBAR_DEFAULT	0xff700000
 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS	1
 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM	9
 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM	5
@@ -111,7 +99,6 @@
 #define QE_MURAM_SIZE			0x20000UL
 #define MAX_QE_RISC			4
 #define QE_NUM_OF_SNUM			46
-#define CONFIG_SYS_CCSRBAR_DEFAULT	0xff700000
 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS	1
 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM	9
 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM	5
@@ -124,7 +111,6 @@
 #define CONFIG_SYS_FSL_NUM_LAWS		12
 #define CONFIG_SYS_PPC_E500_DEBUG_TLB	2
 #define CONFIG_SYS_FSL_SEC_COMPAT	2
-#define CONFIG_SYS_CCSRBAR_DEFAULT	0xff700000
 #define CONFIG_SYS_FSL_ERRATUM_DDR_115
 #define CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134
 #define CONFIG_SYS_FSL_ERRATUM_A004508
@@ -140,7 +126,6 @@
 #define CONFIG_NUM_DDR_CONTROLLERS	1
 #define CONFIG_USB_MAX_CONTROLLER_COUNT	1
 #define CONFIG_SYS_FSL_IFC_BANK_COUNT	4
-#define CONFIG_SYS_CCSRBAR_DEFAULT	0xff700000
 #define CONFIG_SYS_FSL_PCIE_COMPAT	"fsl,qoriq-pcie-v2.2"
 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
 #define CONFIG_SYS_FSL_ERRATUM_IFC_A002769
@@ -165,7 +150,6 @@
 #define CONFIG_FSL_PCIE_DISABLE_ASPM
 #define CONFIG_SYS_FSL_SEC_COMPAT	2
 #define CONFIG_USB_MAX_CONTROLLER_COUNT	2
-#define CONFIG_SYS_CCSRBAR_DEFAULT	0xff700000
 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
 #define CONFIG_SYS_FSL_ERRATUM_A004508
@@ -177,7 +161,6 @@
 #define CONFIG_TSECV2
 #define CONFIG_FSL_PCIE_DISABLE_ASPM
 #define CONFIG_SYS_FSL_SEC_COMPAT	2
-#define CONFIG_SYS_CCSRBAR_DEFAULT	0xff700000
 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
 #define CONFIG_SYS_FSL_ERRATUM_A004508
@@ -192,7 +175,6 @@
 #define CONFIG_TSECV2
 #define CONFIG_FSL_PCIE_DISABLE_ASPM
 #define CONFIG_SYS_FSL_SEC_COMPAT	2
-#define CONFIG_SYS_CCSRBAR_DEFAULT	0xff700000
 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
 #define QE_MURAM_SIZE			0x6000UL
@@ -208,7 +190,6 @@
 #define CONFIG_TSECV2
 #define CONFIG_SYS_FSL_SEC_COMPAT	2
 #define CONFIG_USB_MAX_CONTROLLER_COUNT	1
-#define CONFIG_SYS_CCSRBAR_DEFAULT	0xff700000
 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
 #define CONFIG_FSL_SATA_ERRATUM_A001
@@ -227,7 +208,6 @@
 #define CONFIG_SYS_BMAN_NUM_PORTALS	3
 #define CONFIG_SYS_FM_MURAM_SIZE	0x10000
 #define CONFIG_SYS_FSL_PCIE_COMPAT	"fsl,qoriq-pcie-v2.2"
-#define CONFIG_SYS_CCSRBAR_DEFAULT	0xff600000
 #define CONFIG_SYS_FSL_ERRATUM_A004508
 #define CONFIG_SYS_FSL_ERRATUM_A005125
 #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447
@@ -241,7 +221,6 @@
 #define CONFIG_FSL_PCIE_DISABLE_ASPM
 #define CONFIG_SYS_FSL_SEC_COMPAT	2
 #define CONFIG_USB_MAX_CONTROLLER_COUNT	2
-#define CONFIG_SYS_CCSRBAR_DEFAULT	0xff700000
 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
 #define CONFIG_SYS_FSL_ERRATUM_A004508
@@ -255,7 +234,6 @@
 #define CONFIG_TSECV2
 #define CONFIG_FSL_PCIE_DISABLE_ASPM
 #define CONFIG_SYS_FSL_SEC_COMPAT	2
-#define CONFIG_SYS_CCSRBAR_DEFAULT	0xff700000
 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
 #define QE_MURAM_SIZE			0x6000UL
@@ -268,7 +246,6 @@
 #define CONFIG_SYS_FSL_NUM_LAWS		12
 #define CONFIG_SYS_PPC_E500_DEBUG_TLB	2
 #define CONFIG_SYS_FSL_SEC_COMPAT	2
-#define CONFIG_SYS_CCSRBAR_DEFAULT	0xff700000
 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
 #define CONFIG_SYS_FSL_ERRATUM_ESDHC_A001
 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS	2
@@ -295,7 +272,6 @@
 #define CONFIG_SYS_FM_MURAM_SIZE	0x28000
 #define CONFIG_SYS_FSL_TBCLK_DIV	32
 #define CONFIG_SYS_FSL_PCIE_COMPAT	"fsl,qoriq-pcie-v2.2"
-#define CONFIG_SYS_CCSRBAR_DEFAULT	0xfe000000
 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE
 #define CONFIG_SYS_FSL_USB2_PHY_ENABLE
 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
@@ -332,7 +308,6 @@
 #define CONFIG_SYS_FM_MURAM_SIZE	0x28000
 #define CONFIG_SYS_FSL_TBCLK_DIV	32
 #define CONFIG_SYS_FSL_PCIE_COMPAT	"fsl,qoriq-pcie-v2.2"
-#define CONFIG_SYS_CCSRBAR_DEFAULT	0xfe000000
 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE
 #define CONFIG_SYS_FSL_USB2_PHY_ENABLE
 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
@@ -374,7 +349,6 @@
 #define CONFIG_SYS_FM_MURAM_SIZE	0x28000
 #define CONFIG_SYS_FSL_TBCLK_DIV	16
 #define CONFIG_SYS_FSL_PCIE_COMPAT	"fsl,p4080-pcie"
-#define CONFIG_SYS_CCSRBAR_DEFAULT	0xfe000000
 #define CONFIG_SYS_FSL_ERRATUM_CPC_A002
 #define CONFIG_SYS_FSL_ERRATUM_CPC_A003
 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003
@@ -423,7 +397,6 @@
 #define CONFIG_SYS_FM_MURAM_SIZE	0x28000
 #define CONFIG_SYS_FSL_TBCLK_DIV	32
 #define CONFIG_SYS_FSL_PCIE_COMPAT	"fsl,qoriq-pcie-v2.2"
-#define CONFIG_SYS_CCSRBAR_DEFAULT	0xfe000000
 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE
 #define CONFIG_SYS_FSL_USB2_PHY_ENABLE
 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
@@ -460,7 +433,6 @@
 #define CONFIG_SYS_FM_MURAM_SIZE	0x28000
 #define CONFIG_SYS_FSL_TBCLK_DIV	16
 #define CONFIG_SYS_FSL_PCIE_COMPAT	"fsl,qoriq-pcie-v2.4"
-#define CONFIG_SYS_CCSRBAR_DEFAULT	0xfe000000
 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE
 #define CONFIG_SYS_FSL_USB2_PHY_ENABLE
 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
@@ -486,7 +458,6 @@
 #define CONFIG_SYS_FSL_DSP_M2_RAM_ADDR	0xb0000000
 #define CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT	0xff600000
 #define CONFIG_SYS_FSL_IFC_BANK_COUNT	3
-#define CONFIG_SYS_CCSRBAR_DEFAULT	0xff700000
 #define CONFIG_NAND_FSL_IFC
 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
 #define CONFIG_SYS_FSL_ERRATUM_A005125
@@ -507,7 +478,6 @@
 #define CONFIG_SYS_FSL_DSP_M3_RAM_ADDR	0xc0000000
 #define CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT	0xff600000
 #define CONFIG_SYS_FSL_IFC_BANK_COUNT	3
-#define CONFIG_SYS_CCSRBAR_DEFAULT	0xff700000
 #define CONFIG_NAND_FSL_IFC
 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
 #define CONFIG_SYS_FSL_ESDHC_P1010_BROKEN_SDCLK
@@ -575,7 +545,6 @@
 #define CONFIG_SYS_FSL_ERRATUM_A007186
 #define CONFIG_SYS_FSL_ERRATUM_A006593
 #define CONFIG_SYS_FSL_ERRATUM_A007798
-#define CONFIG_SYS_CCSRBAR_DEFAULT	0xfe000000
 #define CONFIG_SYS_FSL_SFP_VER_3_0
 #define CONFIG_SYS_FSL_PCI_VER_3_X
 
@@ -618,7 +587,6 @@
 #define CONFIG_SYS_FSL_ERRATUM_A006384
 #define CONFIG_SYS_FSL_ERRATUM_A007212
 #define CONFIG_SYS_FSL_ERRATUM_A004477
-#define CONFIG_SYS_CCSRBAR_DEFAULT	0xfe000000
 #define CONFIG_SYS_FSL_SFP_VER_3_0
 
 #ifdef CONFIG_ARCH_B4860
@@ -681,7 +649,6 @@ defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022)
 #define CONFIG_SYS_FSL_PCIE_COMPAT	"fsl,qoriq-pcie-v2.4"
 #define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE
 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
-#define CONFIG_SYS_CCSRBAR_DEFAULT	0xfe000000
 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
 #define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE
 #define QE_MURAM_SIZE			0x6000UL
@@ -725,7 +692,6 @@ defined(CONFIG_PPC_T1014) || defined(CONFIG_PPC_T1013)
 #define CONFIG_SYS_FSL_PCIE_COMPAT	"fsl,qoriq-pcie-v2.4"
 #define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE
 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
-#define CONFIG_SYS_CCSRBAR_DEFAULT	0xfe000000
 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
 #define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE
 #define QE_MURAM_SIZE			0x6000UL
@@ -778,7 +744,6 @@ defined(CONFIG_PPC_T1014) || defined(CONFIG_PPC_T1013)
 #define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE
 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
 #define CONFIG_SYS_FSL_ERRATUM_A007212
-#define CONFIG_SYS_CCSRBAR_DEFAULT	0xfe000000
 #define CONFIG_SYS_FSL_SFP_VER_3_0
 #define CONFIG_SYS_FSL_ISBC_VER		2
 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
@@ -799,22 +764,16 @@ defined(CONFIG_PPC_T1014) || defined(CONFIG_PPC_T1013)
 #define CONFIG_NUM_DDR_CONTROLLERS	1
 #define CONFIG_SYS_FSL_DDR_VER		FSL_DDR_VER_4_6
 #define CONFIG_SYS_FSL_IFC_BANK_COUNT	8
-#define CONFIG_SYS_CCSRBAR_DEFAULT	0xff700000
 #define CONFIG_SYS_FSL_ERRATUM_A005125
 #define CONFIG_SYS_FSL_MAX_NUM_OF_SEC	3
 #define CONFIG_SYS_FSL_SEC_IDX_OFFSET	0x20000
 
 #elif defined(CONFIG_ARCH_QEMU_E500)
-#define CONFIG_SYS_CCSRBAR_DEFAULT	0xe0000000
 
 #else
 #error Processor type not defined for this platform
 #endif
 
-#ifndef CONFIG_SYS_CCSRBAR_DEFAULT
-#error "CONFIG_SYS_CCSRBAR_DEFAULT is not defined for this platform."
-#endif
-
 #ifdef CONFIG_E6500
 #define CONFIG_SYS_FSL_THREADS_PER_CORE 2
 #else
diff --git a/doc/README.ramboot-ppc85xx b/doc/README.ramboot-ppc85xx
index 5cc546a..c9fef53 100644
--- a/doc/README.ramboot-ppc85xx
+++ b/doc/README.ramboot-ppc85xx
@@ -90,8 +90,8 @@ In the 2nd case bootloader has already re-located CCSRBAR to 0xffe00000
 
    This will finally use the CONFIG_SYS_RAMBOOT.
 
-3. File name-> arch/powerpc/include/asm/config_mpc85xx.h
-   In the section of the particular SOC, for example P1020,
+3. Change CONFIG_SYS_CCSRBAR_DEFAULT in menuconfig accordingly.
+   In the section of the particular SOC, for example P1020, pseudo code
 
    #if defined(CONFIG_GO)
    #define CONFIG_SYS_CCSRBAR_DEFAULT	0xffe00000
-- 
2.7.4

  parent reply	other threads:[~2016-12-02 21:37 UTC|newest]

Thread overview: 13+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2016-12-02 21:37 [U-Boot] [PATCH 00/11] Convert several macros to Kconfig York Sun
2016-12-02 21:37 ` [U-Boot] [PATCH 01/11] powerpc: cyrus: Separate P5020/P5040 config options York Sun
2016-12-02 21:37 ` York Sun [this message]
2016-12-02 21:37 ` [U-Boot] [PATCH 03/11] powerpc: mpc86xx: Convert CONFIG_SYS_CCSRBAR_DEFAULT to Kconfig option York Sun
2016-12-02 21:37 ` [U-Boot] [PATCH 04/11] script: remove CONFIG_SYS_CCSRBAR_DEFAULT from white list York Sun
2016-12-02 21:37 ` [U-Boot] [PATCH 05/11] armv7: ls1021a: Move SECURE_BOOT option to Kconfig York Sun
2016-12-02 21:37 ` [U-Boot] [PATCH 06/11] armv8: fsl-layerscape: Move SECURE_BOOT " York Sun
2016-12-02 21:37 ` [U-Boot] [PATCH 07/11] powerpc: mpc85xx: " York Sun
2016-12-02 21:37 ` [U-Boot] [PATCH 08/11] powerpc: mpc85xx: Move CONFIG_FSL_LAW " York Sun
2016-12-02 21:37 ` [U-Boot] [PATCH 09/11] powerpc: mpc86xx: " York Sun
2016-12-02 21:37 ` [U-Boot] [PATCH 10/11] powerpc: mpc85xx: Convert CONFIG_SYS_FSL_NUM_LAWS to Kconfig option York Sun
2016-12-02 21:37 ` [U-Boot] [PATCH 11/11] powerpc: mpc86xx: " York Sun
2016-12-04  1:38 ` [U-Boot] [PATCH 00/11] Convert several macros to Kconfig Tom Rini

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