From: Hemant Agrawal <hemant.agrawal@nxp.com>
To: <dev@dpdk.org>
Cc: <thomas.monjalon@6wind.com>, <bruce.richardson@intel.com>,
<shreyansh.jain@nxp.com>,
Alex Marginean <alexandru.marginean@nxp.com>,
Hemant Agrawal <hemant.agrawal@nxp.com>
Subject: [PATCH 03/32] drivers/common/dpaa2: add mc dpni object support
Date: Sun, 4 Dec 2016 23:46:58 +0530 [thread overview]
Message-ID: <1480875447-23680-4-git-send-email-hemant.agrawal@nxp.com> (raw)
In-Reply-To: <1480875447-23680-1-git-send-email-hemant.agrawal@nxp.com>
This patch add support for dpni object support in MC
driver.
DPNI represent a network interface object in DPAA2.
Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com>
[Hemant: rebase and user space lib]
Signed-off-by: Hemant Agrawal <hemant.agrawal@nxp.com>
---
drivers/common/dpaa2/mc/Makefile | 1 +
drivers/common/dpaa2/mc/dpni.c | 667 ++++++++++++++++++++
drivers/common/dpaa2/mc/fsl_dpkg.h | 177 ++++++
drivers/common/dpaa2/mc/fsl_dpni.h | 1076 ++++++++++++++++++++++++++++++++
drivers/common/dpaa2/mc/fsl_dpni_cmd.h | 301 +++++++++
drivers/common/dpaa2/mc/fsl_net.h | 480 ++++++++++++++
6 files changed, 2702 insertions(+)
create mode 100644 drivers/common/dpaa2/mc/dpni.c
create mode 100644 drivers/common/dpaa2/mc/fsl_dpkg.h
create mode 100644 drivers/common/dpaa2/mc/fsl_dpni.h
create mode 100644 drivers/common/dpaa2/mc/fsl_dpni_cmd.h
create mode 100644 drivers/common/dpaa2/mc/fsl_net.h
diff --git a/drivers/common/dpaa2/mc/Makefile b/drivers/common/dpaa2/mc/Makefile
index 9632168..c7a149b 100644
--- a/drivers/common/dpaa2/mc/Makefile
+++ b/drivers/common/dpaa2/mc/Makefile
@@ -47,6 +47,7 @@ EXPORT_MAP := dpaa2_mc_version.map
LIBABIVER := 1
SRCS-y += \
+ dpni.c \
mc_sys.c
diff --git a/drivers/common/dpaa2/mc/dpni.c b/drivers/common/dpaa2/mc/dpni.c
new file mode 100644
index 0000000..c38c4ec
--- /dev/null
+++ b/drivers/common/dpaa2/mc/dpni.c
@@ -0,0 +1,667 @@
+/* Copyright 2013-2016 Freescale Semiconductor Inc.
+ * Copyright (c) 2016 NXP.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of the above-listed copyright holders nor the
+ * names of any contributors may be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License ("GPL") as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+#include <fsl_mc_sys.h>
+#include <fsl_mc_cmd.h>
+#include <fsl_dpni.h>
+#include <fsl_dpni_cmd.h>
+
+int dpni_prepare_key_cfg(const struct dpkg_profile_cfg *cfg,
+ uint8_t *key_cfg_buf)
+{
+ int i, j;
+ int offset = 0;
+ int param = 1;
+ uint64_t *params = (uint64_t *)key_cfg_buf;
+
+ if (!key_cfg_buf || !cfg)
+ return -EINVAL;
+
+ params[0] |= mc_enc(0, 8, cfg->num_extracts);
+ params[0] = cpu_to_le64(params[0]);
+
+ if (cfg->num_extracts >= DPKG_MAX_NUM_OF_EXTRACTS)
+ return -EINVAL;
+
+ for (i = 0; i < cfg->num_extracts; i++) {
+ switch (cfg->extracts[i].type) {
+ case DPKG_EXTRACT_FROM_HDR:
+ params[param] |= mc_enc(0, 8,
+ cfg->extracts[i].extract.from_hdr.prot);
+ params[param] |= mc_enc(8, 4,
+ cfg->extracts[i].extract.from_hdr.type);
+ params[param] |= mc_enc(16, 8,
+ cfg->extracts[i].extract.from_hdr.size);
+ params[param] |= mc_enc(24, 8,
+ cfg->extracts[i].extract.
+ from_hdr.offset);
+ params[param] |= mc_enc(32, 32,
+ cfg->extracts[i].extract.
+ from_hdr.field);
+ params[param] = cpu_to_le64(params[param]);
+ param++;
+ params[param] |= mc_enc(0, 8,
+ cfg->extracts[i].extract.
+ from_hdr.hdr_index);
+ break;
+ case DPKG_EXTRACT_FROM_DATA:
+ params[param] |= mc_enc(16, 8,
+ cfg->extracts[i].extract.
+ from_data.size);
+ params[param] |= mc_enc(24, 8,
+ cfg->extracts[i].extract.
+ from_data.offset);
+ params[param] = cpu_to_le64(params[param]);
+ param++;
+ break;
+ case DPKG_EXTRACT_FROM_PARSE:
+ params[param] |= mc_enc(16, 8,
+ cfg->extracts[i].extract.
+ from_parse.size);
+ params[param] |= mc_enc(24, 8,
+ cfg->extracts[i].extract.
+ from_parse.offset);
+ params[param] = cpu_to_le64(params[param]);
+ param++;
+ break;
+ default:
+ return -EINVAL;
+ }
+ params[param] |= mc_enc(
+ 24, 8, cfg->extracts[i].num_of_byte_masks);
+ params[param] |= mc_enc(32, 4, cfg->extracts[i].type);
+ params[param] = cpu_to_le64(params[param]);
+ param++;
+ for (offset = 0, j = 0;
+ j < DPKG_NUM_OF_MASKS;
+ offset += 16, j++) {
+ params[param] |= mc_enc(
+ (offset), 8, cfg->extracts[i].masks[j].mask);
+ params[param] |= mc_enc(
+ (offset + 8), 8,
+ cfg->extracts[i].masks[j].offset);
+ }
+ params[param] = cpu_to_le64(params[param]);
+ param++;
+ }
+ return 0;
+}
+
+int dpni_open(struct fsl_mc_io *mc_io,
+ uint32_t cmd_flags,
+ int dpni_id,
+ uint16_t *token)
+{
+ struct mc_command cmd = { 0 };
+ int err;
+
+ /* prepare command */
+ cmd.header = mc_encode_cmd_header(DPNI_CMDID_OPEN,
+ cmd_flags,
+ 0);
+ DPNI_CMD_OPEN(cmd, dpni_id);
+
+ /* send command to mc*/
+ err = mc_send_command(mc_io, &cmd);
+ if (err)
+ return err;
+
+ /* retrieve response parameters */
+ *token = MC_CMD_HDR_READ_TOKEN(cmd.header);
+
+ return 0;
+}
+
+int dpni_close(struct fsl_mc_io *mc_io,
+ uint32_t cmd_flags,
+ uint16_t token)
+{
+ struct mc_command cmd = { 0 };
+
+ /* prepare command */
+ cmd.header = mc_encode_cmd_header(DPNI_CMDID_CLOSE,
+ cmd_flags,
+ token);
+
+ /* send command to mc*/
+ return mc_send_command(mc_io, &cmd);
+}
+
+int dpni_create(struct fsl_mc_io *mc_io,
+ uint16_t dprc_token,
+ uint32_t cmd_flags,
+ const struct dpni_cfg *cfg,
+ uint32_t *obj_id)
+{
+ struct mc_command cmd = { 0 };
+ int err;
+
+ /* prepare command */
+ cmd.header = mc_encode_cmd_header(DPNI_CMDID_CREATE,
+ cmd_flags,
+ dprc_token);
+ DPNI_CMD_CREATE(cmd, cfg);
+
+ /* send command to mc*/
+ err = mc_send_command(mc_io, &cmd);
+ if (err)
+ return err;
+
+ /* retrieve response parameters */
+ CMD_CREATE_RSP_GET_OBJ_ID_PARAM0(cmd, *obj_id);
+
+ return 0;
+}
+
+int dpni_destroy(struct fsl_mc_io *mc_io,
+ uint16_t dprc_token,
+ uint32_t cmd_flags,
+ uint32_t object_id)
+{
+ struct mc_command cmd = { 0 };
+
+ /* prepare command */
+ cmd.header = mc_encode_cmd_header(DPNI_CMDID_DESTROY,
+ cmd_flags,
+ dprc_token);
+ /* set object id to destroy */
+ CMD_DESTROY_SET_OBJ_ID_PARAM0(cmd, object_id);
+ /* send command to mc*/
+ return mc_send_command(mc_io, &cmd);
+}
+
+int dpni_set_pools(struct fsl_mc_io *mc_io,
+ uint32_t cmd_flags,
+ uint16_t token,
+ const struct dpni_pools_cfg *cfg)
+{
+ struct mc_command cmd = { 0 };
+
+ /* prepare command */
+ cmd.header = mc_encode_cmd_header(DPNI_CMDID_SET_POOLS,
+ cmd_flags,
+ token);
+ DPNI_CMD_SET_POOLS(cmd, cfg);
+
+ /* send command to mc*/
+ return mc_send_command(mc_io, &cmd);
+}
+
+int dpni_enable(struct fsl_mc_io *mc_io,
+ uint32_t cmd_flags,
+ uint16_t token)
+{
+ struct mc_command cmd = { 0 };
+
+ /* prepare command */
+ cmd.header = mc_encode_cmd_header(DPNI_CMDID_ENABLE,
+ cmd_flags,
+ token);
+
+ /* send command to mc*/
+ return mc_send_command(mc_io, &cmd);
+}
+
+int dpni_disable(struct fsl_mc_io *mc_io,
+ uint32_t cmd_flags,
+ uint16_t token)
+{
+ struct mc_command cmd = { 0 };
+
+ /* prepare command */
+ cmd.header = mc_encode_cmd_header(DPNI_CMDID_DISABLE,
+ cmd_flags,
+ token);
+
+ /* send command to mc*/
+ return mc_send_command(mc_io, &cmd);
+}
+
+int dpni_is_enabled(struct fsl_mc_io *mc_io,
+ uint32_t cmd_flags,
+ uint16_t token,
+ int *en)
+{
+ struct mc_command cmd = { 0 };
+ int err;
+ /* prepare command */
+ cmd.header = mc_encode_cmd_header(DPNI_CMDID_IS_ENABLED, cmd_flags,
+ token);
+
+ /* send command to mc*/
+ err = mc_send_command(mc_io, &cmd);
+ if (err)
+ return err;
+
+ /* retrieve response parameters */
+ DPNI_RSP_IS_ENABLED(cmd, *en);
+
+ return 0;
+}
+
+int dpni_reset(struct fsl_mc_io *mc_io,
+ uint32_t cmd_flags,
+ uint16_t token)
+{
+ struct mc_command cmd = { 0 };
+
+ /* prepare command */
+ cmd.header = mc_encode_cmd_header(DPNI_CMDID_RESET,
+ cmd_flags,
+ token);
+
+ /* send command to mc*/
+ return mc_send_command(mc_io, &cmd);
+}
+
+int dpni_get_attributes(struct fsl_mc_io *mc_io,
+ uint32_t cmd_flags,
+ uint16_t token,
+ struct dpni_attr *attr)
+{
+ struct mc_command cmd = { 0 };
+ int err;
+
+ /* prepare command */
+ cmd.header = mc_encode_cmd_header(DPNI_CMDID_GET_ATTR,
+ cmd_flags,
+ token);
+
+ /* send command to mc*/
+ err = mc_send_command(mc_io, &cmd);
+ if (err)
+ return err;
+
+ /* retrieve response parameters */
+ DPNI_RSP_GET_ATTR(cmd, attr);
+
+ return 0;
+}
+
+int dpni_set_errors_behavior(struct fsl_mc_io *mc_io,
+ uint32_t cmd_flags,
+ uint16_t token,
+ struct dpni_error_cfg *cfg)
+{
+ struct mc_command cmd = { 0 };
+
+ /* prepare command */
+ cmd.header = mc_encode_cmd_header(DPNI_CMDID_SET_ERRORS_BEHAVIOR,
+ cmd_flags,
+ token);
+ DPNI_CMD_SET_ERRORS_BEHAVIOR(cmd, cfg);
+
+ /* send command to mc*/
+ return mc_send_command(mc_io, &cmd);
+}
+
+int dpni_get_buffer_layout(struct fsl_mc_io *mc_io,
+ uint32_t cmd_flags,
+ uint16_t token,
+ enum dpni_queue_type qtype,
+ struct dpni_buffer_layout *layout)
+{
+ struct mc_command cmd = { 0 };
+ int err;
+
+ /* prepare command */
+ cmd.header = mc_encode_cmd_header(DPNI_CMDID_GET_BUFFER_LAYOUT,
+ cmd_flags,
+ token);
+ DPNI_CMD_GET_BUFFER_LAYOUT(cmd, qtype);
+
+ /* send command to mc*/
+ err = mc_send_command(mc_io, &cmd);
+ if (err)
+ return err;
+
+ /* retrieve response parameters */
+ DPNI_RSP_GET_BUFFER_LAYOUT(cmd, layout);
+
+ return 0;
+}
+
+int dpni_set_buffer_layout(struct fsl_mc_io *mc_io,
+ uint32_t cmd_flags,
+ uint16_t token,
+ enum dpni_queue_type qtype,
+ const struct dpni_buffer_layout *layout)
+{
+ struct mc_command cmd = { 0 };
+
+ /* prepare command */
+ cmd.header = mc_encode_cmd_header(DPNI_CMDID_SET_BUFFER_LAYOUT,
+ cmd_flags,
+ token);
+ DPNI_CMD_SET_BUFFER_LAYOUT(cmd, qtype, layout);
+
+ /* send command to mc*/
+ return mc_send_command(mc_io, &cmd);
+}
+
+int dpni_set_offload(struct fsl_mc_io *mc_io,
+ uint32_t cmd_flags,
+ uint16_t token,
+ enum dpni_offload type,
+ uint32_t config)
+{
+ struct mc_command cmd = { 0 };
+
+ /* prepare command */
+ cmd.header = mc_encode_cmd_header(DPNI_CMDID_SET_OFFLOAD,
+ cmd_flags,
+ token);
+ DPNI_CMD_SET_OFFLOAD(cmd, type, config);
+
+ /* send command to mc*/
+ return mc_send_command(mc_io, &cmd);
+}
+
+int dpni_get_offload(struct fsl_mc_io *mc_io,
+ uint32_t cmd_flags,
+ uint16_t token,
+ enum dpni_offload type,
+ uint32_t *config)
+{
+ struct mc_command cmd = { 0 };
+ int err;
+
+ /* prepare command */
+ cmd.header = mc_encode_cmd_header(DPNI_CMDID_GET_OFFLOAD,
+ cmd_flags,
+ token);
+ DPNI_CMD_GET_OFFLOAD(cmd, type);
+
+ /* send command to mc*/
+ err = mc_send_command(mc_io, &cmd);
+ if (err)
+ return err;
+
+ /* retrieve response parameters */
+ DPNI_RSP_GET_OFFLOAD(cmd, *config);
+
+ return 0;
+}
+
+int dpni_get_qdid(struct fsl_mc_io *mc_io,
+ uint32_t cmd_flags,
+ uint16_t token,
+ enum dpni_queue_type qtype,
+ uint16_t *qdid)
+{
+ struct mc_command cmd = { 0 };
+ int err;
+
+ /* prepare command */
+ cmd.header = mc_encode_cmd_header(DPNI_CMDID_GET_QDID,
+ cmd_flags,
+ token);
+ DPNI_CMD_GET_QDID(cmd, qtype);
+
+ /* send command to mc*/
+ err = mc_send_command(mc_io, &cmd);
+ if (err)
+ return err;
+
+ /* retrieve response parameters */
+ DPNI_RSP_GET_QDID(cmd, *qdid);
+
+ return 0;
+}
+int dpni_set_max_frame_length(struct fsl_mc_io *mc_io,
+ uint32_t cmd_flags,
+ uint16_t token,
+ uint16_t max_frame_length)
+{
+ struct mc_command cmd = { 0 };
+
+ /* prepare command */
+ cmd.header = mc_encode_cmd_header(DPNI_CMDID_SET_MAX_FRAME_LENGTH,
+ cmd_flags,
+ token);
+ DPNI_CMD_SET_MAX_FRAME_LENGTH(cmd, max_frame_length);
+
+ /* send command to mc*/
+ return mc_send_command(mc_io, &cmd);
+}
+
+int dpni_get_max_frame_length(struct fsl_mc_io *mc_io,
+ uint32_t cmd_flags,
+ uint16_t token,
+ uint16_t *max_frame_length)
+{
+ struct mc_command cmd = { 0 };
+ int err;
+
+ /* prepare command */
+ cmd.header = mc_encode_cmd_header(DPNI_CMDID_GET_MAX_FRAME_LENGTH,
+ cmd_flags,
+ token);
+
+ /* send command to mc*/
+ err = mc_send_command(mc_io, &cmd);
+ if (err)
+ return err;
+
+ /* retrieve response parameters */
+ DPNI_RSP_GET_MAX_FRAME_LENGTH(cmd, *max_frame_length);
+
+ return 0;
+}
+
+int dpni_set_unicast_promisc(struct fsl_mc_io *mc_io,
+ uint32_t cmd_flags,
+ uint16_t token,
+ int en)
+{
+ struct mc_command cmd = { 0 };
+
+ /* prepare command */
+ cmd.header = mc_encode_cmd_header(DPNI_CMDID_SET_UNICAST_PROMISC,
+ cmd_flags,
+ token);
+ DPNI_CMD_SET_UNICAST_PROMISC(cmd, en);
+
+ /* send command to mc*/
+ return mc_send_command(mc_io, &cmd);
+}
+
+int dpni_get_unicast_promisc(struct fsl_mc_io *mc_io,
+ uint32_t cmd_flags,
+ uint16_t token,
+ int *en)
+{
+ struct mc_command cmd = { 0 };
+ int err;
+
+ /* prepare command */
+ cmd.header = mc_encode_cmd_header(DPNI_CMDID_GET_UNICAST_PROMISC,
+ cmd_flags,
+ token);
+
+ /* send command to mc*/
+ err = mc_send_command(mc_io, &cmd);
+ if (err)
+ return err;
+
+ /* retrieve response parameters */
+ DPNI_RSP_GET_UNICAST_PROMISC(cmd, *en);
+
+ return 0;
+}
+
+int dpni_set_primary_mac_addr(struct fsl_mc_io *mc_io,
+ uint32_t cmd_flags,
+ uint16_t token,
+ const uint8_t mac_addr[6])
+{
+ struct mc_command cmd = { 0 };
+
+ /* prepare command */
+ cmd.header = mc_encode_cmd_header(DPNI_CMDID_SET_PRIM_MAC,
+ cmd_flags,
+ token);
+ DPNI_CMD_SET_PRIMARY_MAC_ADDR(cmd, mac_addr);
+
+ /* send command to mc*/
+ return mc_send_command(mc_io, &cmd);
+}
+
+int dpni_get_primary_mac_addr(struct fsl_mc_io *mc_io,
+ uint32_t cmd_flags,
+ uint16_t token,
+ uint8_t mac_addr[6])
+{
+ struct mc_command cmd = { 0 };
+ int err;
+
+ /* prepare command */
+ cmd.header = mc_encode_cmd_header(DPNI_CMDID_GET_PRIM_MAC,
+ cmd_flags,
+ token);
+
+ /* send command to mc*/
+ err = mc_send_command(mc_io, &cmd);
+ if (err)
+ return err;
+
+ /* retrieve response parameters */
+ DPNI_RSP_GET_PRIMARY_MAC_ADDR(cmd, mac_addr);
+
+ return 0;
+}
+
+int dpni_set_rx_tc_dist(struct fsl_mc_io *mc_io,
+ uint32_t cmd_flags,
+ uint16_t token,
+ uint8_t tc_id,
+ const struct dpni_rx_tc_dist_cfg *cfg)
+{
+ struct mc_command cmd = { 0 };
+
+ /* prepare command */
+ cmd.header = mc_encode_cmd_header(DPNI_CMDID_SET_RX_TC_DIST,
+ cmd_flags,
+ token);
+ DPNI_CMD_SET_RX_TC_DIST(cmd, tc_id, cfg);
+
+ /* send command to mc*/
+ return mc_send_command(mc_io, &cmd);
+}
+
+int dpni_set_tx_confirmation_mode(struct fsl_mc_io *mc_io,
+ uint32_t cmd_flags,
+ uint16_t token,
+ enum dpni_confirmation_mode mode)
+{
+ struct mc_command cmd = { 0 };
+
+ /* prepare command */
+ cmd.header = mc_encode_cmd_header(DPNI_CMDID_SET_TX_CONFIRMATION_MODE,
+ cmd_flags,
+ token);
+ DPNI_CMD_SET_TX_CONFIRMATION_MODE(cmd, mode);
+
+ /* send command to mc*/
+ return mc_send_command(mc_io, &cmd);
+}
+
+int dpni_get_api_version(struct fsl_mc_io *mc_io,
+ uint32_t cmd_flags,
+ uint16_t *major_ver,
+ uint16_t *minor_ver)
+{
+ struct mc_command cmd = { 0 };
+ int err;
+
+ cmd.header = mc_encode_cmd_header(DPNI_CMDID_GET_API_VERSION,
+ cmd_flags,
+ 0);
+
+ err = mc_send_command(mc_io, &cmd);
+ if (err)
+ return err;
+
+ DPNI_RSP_GET_API_VERSION(cmd, *major_ver, *minor_ver);
+
+ return 0;
+}
+
+int dpni_set_queue(struct fsl_mc_io *mc_io,
+ uint32_t cmd_flags,
+ uint16_t token,
+ enum dpni_queue_type qtype,
+ uint8_t tc,
+ uint8_t index,
+ uint8_t options,
+ const struct dpni_queue *queue)
+{
+ struct mc_command cmd = { 0 };
+
+ /* prepare command */
+ cmd.header = mc_encode_cmd_header(DPNI_CMDID_SET_QUEUE,
+ cmd_flags,
+ token);
+ DPNI_CMD_SET_QUEUE(cmd, qtype, tc, index, options, queue);
+
+ /* send command to mc*/
+ return mc_send_command(mc_io, &cmd);
+}
+
+int dpni_get_queue(struct fsl_mc_io *mc_io,
+ uint32_t cmd_flags,
+ uint16_t token,
+ enum dpni_queue_type qtype,
+ uint8_t tc,
+ uint8_t index,
+ struct dpni_queue *queue,
+ struct dpni_queue_id *qid)
+{
+ struct mc_command cmd = { 0 };
+ int err;
+
+ /* prepare command */
+ cmd.header = mc_encode_cmd_header(DPNI_CMDID_GET_QUEUE,
+ cmd_flags,
+ token);
+ DPNI_CMD_GET_QUEUE(cmd, qtype, tc, index);
+
+ /* send command to mc*/
+ err = mc_send_command(mc_io, &cmd);
+ if (err)
+ return err;
+
+ /* retrieve response parameters */
+ DPNI_RSP_GET_QUEUE(cmd, queue, qid);
+
+ return 0;
+}
diff --git a/drivers/common/dpaa2/mc/fsl_dpkg.h b/drivers/common/dpaa2/mc/fsl_dpkg.h
new file mode 100644
index 0000000..8cabaaf
--- /dev/null
+++ b/drivers/common/dpaa2/mc/fsl_dpkg.h
@@ -0,0 +1,177 @@
+/* Copyright 2013-2015 Freescale Semiconductor Inc.
+ * Copyright (c) 2016 NXP.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of the above-listed copyright holders nor the
+ * names of any contributors may be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License ("GPL") as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+#ifndef __FSL_DPKG_H_
+#define __FSL_DPKG_H_
+
+#include <fsl_net.h>
+
+/* Data Path Key Generator API
+ * Contains initialization APIs and runtime APIs for the Key Generator
+ */
+
+/** Key Generator properties */
+
+/**
+ * Number of masks per key extraction
+ */
+#define DPKG_NUM_OF_MASKS 4
+/**
+ * Number of extractions per key profile
+ */
+#define DPKG_MAX_NUM_OF_EXTRACTS 10
+
+/**
+ * enum dpkg_extract_from_hdr_type - Selecting extraction by header types
+ * @DPKG_FROM_HDR: Extract selected bytes from header, by offset
+ * @DPKG_FROM_FIELD: Extract selected bytes from header, by offset from field
+ * @DPKG_FULL_FIELD: Extract a full field
+ */
+enum dpkg_extract_from_hdr_type {
+ DPKG_FROM_HDR = 0,
+ DPKG_FROM_FIELD = 1,
+ DPKG_FULL_FIELD = 2
+};
+
+/**
+ * enum dpkg_extract_type - Enumeration for selecting extraction type
+ * @DPKG_EXTRACT_FROM_HDR: Extract from the header
+ * @DPKG_EXTRACT_FROM_DATA: Extract from data not in specific header
+ * @DPKG_EXTRACT_FROM_PARSE: Extract from parser-result;
+ * e.g. can be used to extract header existence;
+ * please refer to 'Parse Result definition' section in the parser BG
+ */
+enum dpkg_extract_type {
+ DPKG_EXTRACT_FROM_HDR = 0,
+ DPKG_EXTRACT_FROM_DATA = 1,
+ DPKG_EXTRACT_FROM_PARSE = 3
+};
+
+/**
+ * struct dpkg_mask - A structure for defining a single extraction mask
+ * @mask: Byte mask for the extracted content
+ * @offset: Offset within the extracted content
+ */
+struct dpkg_mask {
+ uint8_t mask;
+ uint8_t offset;
+};
+
+/**
+ * struct dpkg_extract - A structure for defining a single extraction
+ * @type: Determines how the union below is interpreted:
+ * DPKG_EXTRACT_FROM_HDR: selects 'from_hdr';
+ * DPKG_EXTRACT_FROM_DATA: selects 'from_data';
+ * DPKG_EXTRACT_FROM_PARSE: selects 'from_parse'
+ * @extract: Selects extraction method
+ * @num_of_byte_masks: Defines the number of valid entries in the array below;
+ * This is also the number of bytes to be used as masks
+ * @masks: Masks parameters
+ */
+struct dpkg_extract {
+ enum dpkg_extract_type type;
+ /**
+ * union extract - Selects extraction method
+ * @from_hdr - Used when 'type = DPKG_EXTRACT_FROM_HDR'
+ * @from_data - Used when 'type = DPKG_EXTRACT_FROM_DATA'
+ * @from_parse - Used when 'type = DPKG_EXTRACT_FROM_PARSE'
+ */
+ union {
+ /**
+ * struct from_hdr - Used when 'type = DPKG_EXTRACT_FROM_HDR'
+ * @prot: Any of the supported headers
+ * @type: Defines the type of header extraction:
+ * DPKG_FROM_HDR: use size & offset below;
+ * DPKG_FROM_FIELD: use field, size and offset below;
+ * DPKG_FULL_FIELD: use field below
+ * @field: One of the supported fields (NH_FLD_)
+ *
+ * @size: Size in bytes
+ * @offset: Byte offset
+ * @hdr_index: Clear for cases not listed below;
+ * Used for protocols that may have more than a single
+ * header, 0 indicates an outer header;
+ * Supported protocols (possible values):
+ * NET_PROT_VLAN (0, HDR_INDEX_LAST);
+ * NET_PROT_MPLS (0, 1, HDR_INDEX_LAST);
+ * NET_PROT_IP(0, HDR_INDEX_LAST);
+ * NET_PROT_IPv4(0, HDR_INDEX_LAST);
+ * NET_PROT_IPv6(0, HDR_INDEX_LAST);
+ */
+
+ struct {
+ enum net_prot prot;
+ enum dpkg_extract_from_hdr_type type;
+ uint32_t field;
+ uint8_t size;
+ uint8_t offset;
+ uint8_t hdr_index;
+ } from_hdr;
+ /**
+ * struct from_data
+ * Used when 'type = DPKG_EXTRACT_FROM_DATA'
+ * @size: Size in bytes
+ * @offset: Byte offset
+ */
+ struct {
+ uint8_t size;
+ uint8_t offset;
+ } from_data;
+
+ /**
+ * struct from_parse
+ * Used when 'type = DPKG_EXTRACT_FROM_PARSE'
+ * @size: Size in bytes
+ * @offset: Byte offset
+ */
+ struct {
+ uint8_t size;
+ uint8_t offset;
+ } from_parse;
+ } extract;
+
+ uint8_t num_of_byte_masks;
+ struct dpkg_mask masks[DPKG_NUM_OF_MASKS];
+};
+
+/**
+ * struct dpkg_profile_cfg - A structure for defining a full Key Generation
+ * profile (rule)
+ * @num_extracts: Defines the number of valid entries in the array below
+ * @extracts: Array of required extractions
+ */
+struct dpkg_profile_cfg {
+ uint8_t num_extracts;
+ struct dpkg_extract extracts[DPKG_MAX_NUM_OF_EXTRACTS];
+};
+
+#endif /* __FSL_DPKG_H_ */
diff --git a/drivers/common/dpaa2/mc/fsl_dpni.h b/drivers/common/dpaa2/mc/fsl_dpni.h
new file mode 100644
index 0000000..48ca660
--- /dev/null
+++ b/drivers/common/dpaa2/mc/fsl_dpni.h
@@ -0,0 +1,1076 @@
+/* Copyright 2013-2016 Freescale Semiconductor Inc.
+ * Copyright (c) 2016 NXP.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of the above-listed copyright holders nor the
+ * names of any contributors may be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License ("GPL") as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+#ifndef __FSL_DPNI_H
+#define __FSL_DPNI_H
+
+#include <fsl_dpkg.h>
+
+struct fsl_mc_io;
+
+/**
+ * Data Path Network Interface API
+ * Contains initialization APIs and runtime control APIs for DPNI
+ */
+
+/** General DPNI macros */
+
+/**
+ * Maximum number of traffic classes
+ */
+#define DPNI_MAX_TC 8
+/**
+ * Maximum number of buffer pools per DPNI
+ */
+#define DPNI_MAX_DPBP 8
+/**
+ * Maximum number of storage-profiles per DPNI
+ */
+#define DPNI_MAX_SP 2
+
+/**
+ * All traffic classes considered; see dpni_set_queue()
+ */
+#define DPNI_ALL_TCS (uint8_t)(-1)
+/**
+ * All flows within traffic class considered; see dpni_set_queue()
+ */
+#define DPNI_ALL_TC_FLOWS (uint16_t)(-1)
+/**
+ * Generate new flow ID; see dpni_set_queue()
+ */
+#define DPNI_NEW_FLOW_ID (uint16_t)(-1)
+/**
+ * Tx traffic is always released to a buffer pool on transmit, there are no
+ * resources allocated to have the frames confirmed back to the source after
+ * transmission.
+ */
+#define DPNI_OPT_TX_FRM_RELEASE 0x000001
+/**
+ * Disables support for MAC address filtering for addresses other than primary
+ * MAC address. This affects both unicast and multicast. Promiscuous mode can
+ * still be enabled/disabled for both unicast and multicast. If promiscuous mode
+ * is disabled, only traffic matching the primary MAC address will be accepted.
+ */
+#define DPNI_OPT_NO_MAC_FILTER 0x000002
+/**
+ * Allocate policers for this DPNI. They can be used to rate-limit traffic per
+ * traffic class (TC) basis.
+ */
+#define DPNI_OPT_HAS_POLICING 0x000004
+/**
+ * Congestion can be managed in several ways, allowing the buffer pool to
+ * deplete on ingress, taildrop on each queue or use congestion groups for sets
+ * of queues. If set, it configures a single congestion groups across all TCs.
+ * If reset, a congestion group is allocated for each TC. Only relevant if the
+ * DPNI has multiple traffic classes.
+ */
+#define DPNI_OPT_SHARED_CONGESTION 0x000008
+/**
+ * Enables TCAM for Flow Steering and QoS look-ups. If not specified, all
+ * look-ups are exact match. Note that TCAM is not available on LS1088 and its
+ * variants. Setting this bit on these SoCs will trigger an error.
+ */
+#define DPNI_OPT_HAS_KEY_MASKING 0x000010
+/**
+ * Disables the flow steering table.
+ */
+#define DPNI_OPT_NO_FS 0x000020
+
+/**
+ * dpni_open() - Open a control session for the specified object
+ * @mc_io: Pointer to MC portal's I/O object
+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
+ * @dpni_id: DPNI unique ID
+ * @token: Returned token; use in subsequent API calls
+ *
+ * This function can be used to open a control session for an
+ * already created object; an object may have been declared in
+ * the DPL or by calling the dpni_create() function.
+ * This function returns a unique authentication token,
+ * associated with the specific object ID and the specific MC
+ * portal; this token must be used in all subsequent commands for
+ * this specific object.
+ *
+ * Return: '0' on Success; Error code otherwise.
+ */
+int dpni_open(struct fsl_mc_io *mc_io,
+ uint32_t cmd_flags,
+ int dpni_id,
+ uint16_t *token);
+
+/**
+ * dpni_close() - Close the control session of the object
+ * @mc_io: Pointer to MC portal's I/O object
+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
+ * @token: Token of DPNI object
+ *
+ * After this function is called, no further operations are
+ * allowed on the object without opening a new control session.
+ *
+ * Return: '0' on Success; Error code otherwise.
+ */
+int dpni_close(struct fsl_mc_io *mc_io,
+ uint32_t cmd_flags,
+ uint16_t token);
+
+/**
+ * struct dpni_cfg - Structure representing DPNI configuration
+ * @mac_addr: Primary MAC address
+ * @adv: Advanced parameters; default is all zeros;
+ * use this structure to change default settings
+ */
+struct dpni_cfg {
+ /**
+ * @options: Any combination of the following options:
+ * DPNI_OPT_TX_FRM_RELEASE
+ * DPNI_OPT_NO_MAC_FILTER
+ * DPNI_OPT_HAS_POLICING
+ * DPNI_OPT_SHARED_CONGESTION
+ * DPNI_OPT_HAS_KEY_MASKING
+ * DPNI_OPT_NO_FS
+ * @fs_entries: Number of entries in the flow steering table.
+ * This table is used to select the ingress queue for
+ * ingress traffic, targeting a GPP core or another.
+ * In addition it can be used to discard traffic that
+ * matches the set rule. It is either an exact match table
+ * or a TCAM table, depending on DPNI_OPT_ HAS_KEY_MASKING
+ * bit in OPTIONS field. This field is ignored if
+ * DPNI_OPT_NO_FS bit is set in OPTIONS field. Otherwise,
+ * value 0 defaults to 64. Maximum supported value is 1024.
+ * Note that the total number of entries is limited on the
+ * SoC to as low as 512 entries if TCAM is used.
+ * @vlan_filter_entries: Number of entries in the VLAN address filtering
+ * table. This is an exact match table used to filter
+ * ingress traffic based on VLAN IDs. Value 0 disables VLAN
+ * filtering. Maximum supported value is 16.
+ * @mac_filter_entries: Number of entries in the MAC address filtering
+ * table. This is an exact match table and allows both
+ * unicast and multicast entries. The primary MAC address
+ * of the network interface is not part of this table,
+ * this contains only entries in addition to it. This
+ * field is ignored if DPNI_OPT_ NO_MAC_FILTER is set in
+ * OPTIONS field. Otherwise, value 0 defaults to 80.
+ * Maximum supported value is 80.
+ * @num_queues: Number of Tx and Rx queues used for traffic
+ * distribution. This is orthogonal to QoS and is only
+ * used to distribute traffic to multiple GPP cores.
+ * This configuration affects the number of Tx queues
+ * (logical FQs, all associated with a single CEETM queue),
+ * Rx queues and Tx confirmation queues, if applicable.
+ * Value 0 defaults to one queue. Maximum supported value
+ * is 8.
+ * @num_tcs: Number of traffic classes (TCs), reserved for the DPNI.
+ * TCs can have different priority levels for the purpose
+ * of Tx scheduling (see DPNI_SET_TX_SELECTION), different
+ * BPs (DPNI_ SET_POOLS), policers. There are dedicated QM
+ * queues for traffic classes (including class queues on
+ * Tx). Value 0 defaults to one TC. Maximum supported value
+ * is 8.
+ * @qos_entries: Number of entries in the QoS classification table. This
+ * table is used to select the TC for ingress traffic. It
+ * is either an exact match or a TCAM table, depending on
+ * DPNI_OPT_ HAS_KEY_MASKING bit in OPTIONS field. This
+ * field is ignored if the DPNI has a single TC. Otherwise,
+ * a value of 0 defaults to 64. Maximum supported value
+ * is 64.
+ */
+ uint32_t options;
+ uint16_t fs_entries;
+ uint8_t vlan_filter_entries;
+ uint8_t mac_filter_entries;
+ uint8_t num_queues;
+ uint8_t num_tcs;
+ uint8_t qos_entries;
+};
+
+/**
+ * dpni_create() - Create the DPNI object
+ * @mc_io: Pointer to MC portal's I/O object
+ * @dprc_token: Parent container token; '0' for default container
+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
+ * @cfg: Configuration structure
+ * @obj_id: returned object id
+ *
+ * Create the DPNI object, allocate required resources and
+ * perform required initialization.
+ *
+ * The object can be created either by declaring it in the
+ * DPL file, or by calling this function.
+ *
+ * The function accepts an authentication token of a parent
+ * container that this object should be assigned to. The token
+ * can be '0' so the object will be assigned to the default container.
+ * The newly created object can be opened with the returned
+ * object id and using the container's associated tokens and MC portals.
+ *
+ * Return: '0' on Success; Error code otherwise.
+ */
+int dpni_create(struct fsl_mc_io *mc_io,
+ uint16_t dprc_token,
+ uint32_t cmd_flags,
+ const struct dpni_cfg *cfg,
+ uint32_t *obj_id);
+
+/**
+ * dpni_destroy() - Destroy the DPNI object and release all its resources.
+ * @mc_io: Pointer to MC portal's I/O object
+ * @dprc_token: Parent container token; '0' for default container
+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
+ * @object_id: The object id; it must be a valid id within the container that
+ * created this object;
+ *
+ * The function accepts the authentication token of the parent container that
+ * created the object (not the one that currently owns the object). The object
+ * is searched within parent using the provided 'object_id'.
+ * All tokens to the object must be closed before calling destroy.
+ *
+ * Return: '0' on Success; error code otherwise.
+ */
+int dpni_destroy(struct fsl_mc_io *mc_io,
+ uint16_t dprc_token,
+ uint32_t cmd_flags,
+ uint32_t object_id);
+
+/**
+ * struct dpni_pools_cfg - Structure representing buffer pools configuration
+ * @num_dpbp: Number of DPBPs
+ * @pools: Array of buffer pools parameters; The number of valid entries
+ * must match 'num_dpbp' value
+ */
+struct dpni_pools_cfg {
+ uint8_t num_dpbp;
+ /**
+ * struct pools - Buffer pools parameters
+ * @dpbp_id: DPBP object ID
+ * @buffer_size: Buffer size
+ * @backup_pool: Backup pool
+ */
+ struct {
+ int dpbp_id;
+ uint16_t buffer_size;
+ int backup_pool;
+ } pools[DPNI_MAX_DPBP];
+};
+
+/**
+ * dpni_set_pools() - Set buffer pools configuration
+ * @mc_io: Pointer to MC portal's I/O object
+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
+ * @token: Token of DPNI object
+ * @cfg: Buffer pools configuration
+ *
+ * mandatory for DPNI operation
+ * warning:Allowed only when DPNI is disabled
+ *
+ * Return: '0' on Success; Error code otherwise.
+ */
+int dpni_set_pools(struct fsl_mc_io *mc_io,
+ uint32_t cmd_flags,
+ uint16_t token,
+ const struct dpni_pools_cfg *cfg);
+
+/**
+ * dpni_enable() - Enable the DPNI, allow sending and receiving frames.
+ * @mc_io: Pointer to MC portal's I/O object
+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
+ * @token: Token of DPNI object
+ *
+ * Return: '0' on Success; Error code otherwise.
+ */
+int dpni_enable(struct fsl_mc_io *mc_io,
+ uint32_t cmd_flags,
+ uint16_t token);
+
+/**
+ * dpni_disable() - Disable the DPNI, stop sending and receiving frames.
+ * @mc_io: Pointer to MC portal's I/O object
+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
+ * @token: Token of DPNI object
+ *
+ * Return: '0' on Success; Error code otherwise.
+ */
+int dpni_disable(struct fsl_mc_io *mc_io,
+ uint32_t cmd_flags,
+ uint16_t token);
+
+/**
+ * dpni_is_enabled() - Check if the DPNI is enabled.
+ * @mc_io: Pointer to MC portal's I/O object
+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
+ * @token: Token of DPNI object
+ * @en: Returns '1' if object is enabled; '0' otherwise
+ *
+ * Return: '0' on Success; Error code otherwise.
+ */
+int dpni_is_enabled(struct fsl_mc_io *mc_io,
+ uint32_t cmd_flags,
+ uint16_t token,
+ int *en);
+
+/**
+ * dpni_reset() - Reset the DPNI, returns the object to initial state.
+ * @mc_io: Pointer to MC portal's I/O object
+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
+ * @token: Token of DPNI object
+ *
+ * Return: '0' on Success; Error code otherwise.
+ */
+int dpni_reset(struct fsl_mc_io *mc_io,
+ uint32_t cmd_flags,
+ uint16_t token);
+
+/**
+ * struct dpni_attr - Structure representing DPNI attributes
+ * @options: Any combination of the following options:
+ * DPNI_OPT_TX_FRM_RELEASE
+ * DPNI_OPT_NO_MAC_FILTER
+ * DPNI_OPT_HAS_POLICING
+ * DPNI_OPT_SHARED_CONGESTION
+ * DPNI_OPT_HAS_KEY_MASKING
+ * DPNI_OPT_NO_FS
+ * @num_queues: Number of Tx and Rx queues used for traffic distribution.
+ * @num_tcs: Number of traffic classes (TCs), reserved for the DPNI.
+ * @mac_filter_entries: Number of entries in the MAC address filtering
+ * table.
+ * @vlan_filter_entries: Number of entries in the VLAN address filtering
+ * table.
+ * @qos_entries: Number of entries in the QoS classification table.
+ * @fs_entries: Number of entries in the flow steering table.
+ * @qos_key_size: Size, in bytes, of the QoS look-up key. Defining a key larger
+ * than this when adding QoS entries will result
+ * in an error.
+ * @fs_key_size: Size, in bytes, of the flow steering look-up key. Defining a
+ * key larger than this when composing the hash + FS key
+ * will result in an error.
+ * @wriop_version: Version of WRIOP HW block.
+ * The 3 version values are stored on 6, 5, 5 bits
+ * respectively.
+ * Values returned:
+ * - 0x400 - WRIOP version 1.0.0, used on LS2080 and
+ * variants,
+ * - 0x421 - WRIOP version 1.1.1, used on LS2088 and
+ * variants,
+ * - 0x422 - WRIOP version 1.1.2, used on LS1088 and
+ * variants.
+ */
+struct dpni_attr {
+ uint32_t options;
+ uint8_t num_queues;
+ uint8_t num_tcs;
+ uint8_t mac_filter_entries;
+ uint8_t vlan_filter_entries;
+ uint8_t qos_entries;
+ uint16_t fs_entries;
+ uint8_t qos_key_size;
+ uint8_t fs_key_size;
+ uint16_t wriop_version;
+};
+
+/**
+ * dpni_get_attributes() - Retrieve DPNI attributes.
+ * @mc_io: Pointer to MC portal's I/O object
+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
+ * @token: Token of DPNI object
+ * @attr: Object's attributes
+ *
+ * Return: '0' on Success; Error code otherwise.
+ */
+int dpni_get_attributes(struct fsl_mc_io *mc_io,
+ uint32_t cmd_flags,
+ uint16_t token,
+ struct dpni_attr *attr);
+
+/**
+ * DPNI errors
+ */
+
+/**
+ * Extract out of frame header error
+ */
+#define DPNI_ERROR_EOFHE 0x00020000
+/**
+ * Frame length error
+ */
+#define DPNI_ERROR_FLE 0x00002000
+/**
+ * Frame physical error
+ */
+#define DPNI_ERROR_FPE 0x00001000
+/**
+ * Parsing header error
+ */
+#define DPNI_ERROR_PHE 0x00000020
+/**
+ * Parser L3 checksum error
+ */
+#define DPNI_ERROR_L3CE 0x00000004
+/**
+ * Parser L3 checksum error
+ */
+#define DPNI_ERROR_L4CE 0x00000001
+
+/**
+ * enum dpni_error_action - Defines DPNI behavior for errors
+ * @DPNI_ERROR_ACTION_DISCARD: Discard the frame
+ * @DPNI_ERROR_ACTION_CONTINUE: Continue with the normal flow
+ * @DPNI_ERROR_ACTION_SEND_TO_ERROR_QUEUE: Send the frame to the error queue
+ */
+enum dpni_error_action {
+ DPNI_ERROR_ACTION_DISCARD = 0,
+ DPNI_ERROR_ACTION_CONTINUE = 1,
+ DPNI_ERROR_ACTION_SEND_TO_ERROR_QUEUE = 2
+};
+
+/**
+ * struct dpni_error_cfg - Structure representing DPNI errors treatment
+ * @errors: Errors mask; use 'DPNI_ERROR__<X>
+ * @error_action: The desired action for the errors mask
+ * @set_frame_annotation: Set to '1' to mark the errors in frame annotation
+ * status (FAS); relevant only for the non-discard action
+ */
+struct dpni_error_cfg {
+ uint32_t errors;
+ enum dpni_error_action error_action;
+ int set_frame_annotation;
+};
+
+/**
+ * dpni_set_errors_behavior() - Set errors behavior
+ * @mc_io: Pointer to MC portal's I/O object
+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
+ * @token: Token of DPNI object
+ * @cfg: Errors configuration
+ *
+ * this function may be called numerous times with different
+ * error masks
+ *
+ * Return: '0' on Success; Error code otherwise.
+ */
+int dpni_set_errors_behavior(struct fsl_mc_io *mc_io,
+ uint32_t cmd_flags,
+ uint16_t token,
+ struct dpni_error_cfg *cfg);
+
+/**
+ * DPNI buffer layout modification options
+ */
+
+/**
+ * Select to modify the time-stamp setting
+ */
+#define DPNI_BUF_LAYOUT_OPT_TIMESTAMP 0x00000001
+/**
+ * Select to modify the parser-result setting; not applicable for Tx
+ */
+#define DPNI_BUF_LAYOUT_OPT_PARSER_RESULT 0x00000002
+/**
+ * Select to modify the frame-status setting
+ */
+#define DPNI_BUF_LAYOUT_OPT_FRAME_STATUS 0x00000004
+/**
+ * Select to modify the private-data-size setting
+ */
+#define DPNI_BUF_LAYOUT_OPT_PRIVATE_DATA_SIZE 0x00000008
+/**
+ * Select to modify the data-alignment setting
+ */
+#define DPNI_BUF_LAYOUT_OPT_DATA_ALIGN 0x00000010
+/**
+ * Select to modify the data-head-room setting
+ */
+#define DPNI_BUF_LAYOUT_OPT_DATA_HEAD_ROOM 0x00000020
+/**
+ * Select to modify the data-tail-room setting
+ */
+#define DPNI_BUF_LAYOUT_OPT_DATA_TAIL_ROOM 0x00000040
+
+/**
+ * struct dpni_buffer_layout - Structure representing DPNI buffer layout
+ * @options: Flags representing the suggested modifications to the buffer
+ * layout; Use any combination of 'DPNI_BUF_LAYOUT_OPT_<X>' flags
+ * @pass_timestamp: Pass timestamp value
+ * @pass_parser_result: Pass parser results
+ * @pass_frame_status: Pass frame status
+ * @private_data_size: Size kept for private data (in bytes)
+ * @data_align: Data alignment
+ * @data_head_room: Data head room
+ * @data_tail_room: Data tail room
+ */
+struct dpni_buffer_layout {
+ uint32_t options;
+ int pass_timestamp;
+ int pass_parser_result;
+ int pass_frame_status;
+ uint16_t private_data_size;
+ uint16_t data_align;
+ uint16_t data_head_room;
+ uint16_t data_tail_room;
+};
+
+/**
+ * enum dpni_queue_type - Identifies a type of queue targeted by the command
+ * @DPNI_QUEUE_RX: Rx queue
+ * @DPNI_QUEUE_TX: Tx queue
+ * @DPNI_QUEUE_TX_CONFIRM: Tx confirmation queue
+ * @DPNI_QUEUE_RX_ERR: Rx error queue
+ */enum dpni_queue_type {
+ DPNI_QUEUE_RX,
+ DPNI_QUEUE_TX,
+ DPNI_QUEUE_TX_CONFIRM,
+ DPNI_QUEUE_RX_ERR,
+};
+
+/**
+ * dpni_get_buffer_layout() - Retrieve buffer layout attributes.
+ * @mc_io: Pointer to MC portal's I/O object
+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
+ * @token: Token of DPNI object
+ * @qtype: Type of queue to get the layout from
+ * @layout: Returns buffer layout attributes
+ *
+ * Return: '0' on Success; Error code otherwise.
+ */
+int dpni_get_buffer_layout(struct fsl_mc_io *mc_io,
+ uint32_t cmd_flags,
+ uint16_t token,
+ enum dpni_queue_type qtype,
+ struct dpni_buffer_layout *layout);
+
+/**
+ * dpni_set_buffer_layout() - Set buffer layout configuration.
+ * @mc_io: Pointer to MC portal's I/O object
+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
+ * @token: Token of DPNI object
+ * @qtype: Type of queue to set layout on
+ * @layout: Buffer layout configuration
+ *
+ * Return: '0' on Success; Error code otherwise.
+ *
+ * @warning Allowed only when DPNI is disabled
+ */
+int dpni_set_buffer_layout(struct fsl_mc_io *mc_io,
+ uint32_t cmd_flags,
+ uint16_t token,
+ enum dpni_queue_type qtype,
+ const struct dpni_buffer_layout *layout);
+
+/**
+ * enum dpni_offload - Identifies a type of offload targeted by the command
+ * @DPNI_OFF_RX_L3_CSUM: Rx L3 checksum validation
+ * @DPNI_OFF_RX_L4_CSUM: Rx L4 checksum validation
+ * @DPNI_OFF_TX_L3_CSUM: Tx L3 checksum generation
+ * @DPNI_OFF_TX_L4_CSUM: Tx L4 checksum generation
+ */
+enum dpni_offload {
+ DPNI_OFF_RX_L3_CSUM,
+ DPNI_OFF_RX_L4_CSUM,
+ DPNI_OFF_TX_L3_CSUM,
+ DPNI_OFF_TX_L4_CSUM,
+};
+
+/**
+ * dpni_set_offload() - Set DPNI offload configuration.
+ * @mc_io: Pointer to MC portal's I/O object
+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
+ * @token: Token of DPNI object
+ * @type: Type of DPNI offload
+ * @config: Offload configuration.
+ * For checksum offloads, non-zero value enables
+ * the offload.
+ *
+ * Return: '0' on Success; Error code otherwise.
+ *
+ * @warning Allowed only when DPNI is disabled
+ */
+int dpni_set_offload(struct fsl_mc_io *mc_io,
+ uint32_t cmd_flags,
+ uint16_t token,
+ enum dpni_offload type,
+ uint32_t config);
+
+/**
+ * dpni_get_offload() - Get DPNI offload configuration.
+ * @mc_io: Pointer to MC portal's I/O object
+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
+ * @token: Token of DPNI object
+ * @type: Type of DPNI offload
+ * @config: Offload configuration.
+ * For checksum offloads, a value of 1 indicates that the
+ * offload is enabled.
+ *
+ * Return: '0' on Success; Error code otherwise.
+ *
+ * @warning Allowed only when DPNI is disabled
+ */
+int dpni_get_offload(struct fsl_mc_io *mc_io,
+ uint32_t cmd_flags,
+ uint16_t token,
+ enum dpni_offload type,
+ uint32_t *config);
+
+/**
+ * dpni_get_qdid() - Get the Queuing Destination ID (QDID) that should be used
+ * for enqueue operations
+ * @mc_io: Pointer to MC portal's I/O object
+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
+ * @token: Token of DPNI object
+ * @qtype: Type of queue to get QDID for. For applications lookig to
+ * transmit traffic this should be set to DPNI_QUEUE_TX
+ * @qdid: Returned virtual QDID value that should be used as an argument
+ * in all enqueue operations
+ *
+ * Return: '0' on Success; Error code otherwise.
+ */
+int dpni_get_qdid(struct fsl_mc_io *mc_io,
+ uint32_t cmd_flags,
+ uint16_t token,
+ enum dpni_queue_type qtype,
+ uint16_t *qdid);
+
+/**
+ * dpni_set_max_frame_length() - Set the maximum received frame length.
+ * @mc_io: Pointer to MC portal's I/O object
+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
+ * @token: Token of DPNI object
+ * @max_frame_length: Maximum received frame length (in
+ * bytes); frame is discarded if its
+ * length exceeds this value
+ *
+ * Return: '0' on Success; Error code otherwise.
+ */
+int dpni_set_max_frame_length(struct fsl_mc_io *mc_io,
+ uint32_t cmd_flags,
+ uint16_t token,
+ uint16_t max_frame_length);
+
+/**
+ * dpni_get_max_frame_length() - Get the maximum received frame length.
+ * @mc_io: Pointer to MC portal's I/O object
+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
+ * @token: Token of DPNI object
+ * @max_frame_length: Maximum received frame length (in
+ * bytes); frame is discarded if its
+ * length exceeds this value
+ *
+ * Return: '0' on Success; Error code otherwise.
+ */
+int dpni_get_max_frame_length(struct fsl_mc_io *mc_io,
+ uint32_t cmd_flags,
+ uint16_t token,
+ uint16_t *max_frame_length);
+
+
+/**
+ * dpni_set_unicast_promisc() - Enable/disable unicast promiscuous mode
+ * @mc_io: Pointer to MC portal's I/O object
+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
+ * @token: Token of DPNI object
+ * @en: Set to '1' to enable; '0' to disable
+ *
+ * Return: '0' on Success; Error code otherwise.
+ */
+int dpni_set_unicast_promisc(struct fsl_mc_io *mc_io,
+ uint32_t cmd_flags,
+ uint16_t token,
+ int en);
+
+/**
+ * dpni_get_unicast_promisc() - Get unicast promiscuous mode
+ * @mc_io: Pointer to MC portal's I/O object
+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
+ * @token: Token of DPNI object
+ * @en: Returns '1' if enabled; '0' otherwise
+ *
+ * Return: '0' on Success; Error code otherwise.
+ */
+int dpni_get_unicast_promisc(struct fsl_mc_io *mc_io,
+ uint32_t cmd_flags,
+ uint16_t token,
+ int *en);
+
+/**
+ * dpni_set_primary_mac_addr() - Set the primary MAC address
+ * @mc_io: Pointer to MC portal's I/O object
+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
+ * @token: Token of DPNI object
+ * @mac_addr: MAC address to set as primary address
+ *
+ * Return: '0' on Success; Error code otherwise.
+ */
+int dpni_set_primary_mac_addr(struct fsl_mc_io *mc_io,
+ uint32_t cmd_flags,
+ uint16_t token,
+ const uint8_t mac_addr[6]);
+
+/**
+ * dpni_get_primary_mac_addr() - Get the primary MAC address
+ * @mc_io: Pointer to MC portal's I/O object
+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
+ * @token: Token of DPNI object
+ * @mac_addr: Returned MAC address
+ *
+ * Return: '0' on Success; Error code otherwise.
+ */
+int dpni_get_primary_mac_addr(struct fsl_mc_io *mc_io,
+ uint32_t cmd_flags,
+ uint16_t token,
+ uint8_t mac_addr[6]);
+
+
+/**
+ * dpni_get_port_mac_addr() - Retrieve MAC address associated to the physical
+ * port the DPNI is attached to
+ * @mc_io: Pointer to MC portal's I/O object
+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
+ * @token: Token of DPNI object
+ * @mac_addr: MAC address of the physical port, if any, otherwise 0
+ *
+ * The primary MAC address is not modified by this operation.
+ *
+ * Return: '0' on Success; Error code otherwise.
+ */
+int dpni_get_port_mac_addr(struct fsl_mc_io *mc_io,
+ uint32_t cmd_flags,
+ uint16_t token,
+ uint8_t mac_addr[6]);
+
+/**
+ * enum dpni_dist_mode - DPNI distribution mode
+ * @DPNI_DIST_MODE_NONE: No distribution
+ * @DPNI_DIST_MODE_HASH: Use hash distribution; only relevant if
+ * the 'DPNI_OPT_DIST_HASH' option was set at DPNI creation
+ * @DPNI_DIST_MODE_FS: Use explicit flow steering; only relevant if
+ * the 'DPNI_OPT_DIST_FS' option was set at DPNI creation
+ */
+enum dpni_dist_mode {
+ DPNI_DIST_MODE_NONE = 0,
+ DPNI_DIST_MODE_HASH = 1,
+ DPNI_DIST_MODE_FS = 2
+};
+
+/**
+ * enum dpni_fs_miss_action - DPNI Flow Steering miss action
+ * @DPNI_FS_MISS_DROP: In case of no-match, drop the frame
+ * @DPNI_FS_MISS_EXPLICIT_FLOWID: In case of no-match, use explicit flow-id
+ * @DPNI_FS_MISS_HASH: In case of no-match, distribute using hash
+ */
+enum dpni_fs_miss_action {
+ DPNI_FS_MISS_DROP = 0,
+ DPNI_FS_MISS_EXPLICIT_FLOWID = 1,
+ DPNI_FS_MISS_HASH = 2
+};
+
+/**
+ * struct dpni_fs_tbl_cfg - Flow Steering table configuration
+ * @miss_action: Miss action selection
+ * @default_flow_id: Used when 'miss_action = DPNI_FS_MISS_EXPLICIT_FLOWID'
+ */
+struct dpni_fs_tbl_cfg {
+ enum dpni_fs_miss_action miss_action;
+ uint16_t default_flow_id;
+};
+
+/**
+ * dpni_prepare_key_cfg() - function prepare extract parameters
+ * @cfg: defining a full Key Generation profile (rule)
+ * @key_cfg_buf: Zeroed 256 bytes of memory before mapping it to DMA
+ *
+ * This function has to be called before the following functions:
+ * - dpni_set_rx_tc_dist()
+ * - dpni_set_qos_table()
+ */
+int dpni_prepare_key_cfg(const struct dpkg_profile_cfg *cfg,
+ uint8_t *key_cfg_buf);
+
+/**
+ * struct dpni_rx_tc_dist_cfg - Rx traffic class distribution configuration
+ * @dist_size: Set the distribution size;
+ * supported values: 1,2,3,4,6,7,8,12,14,16,24,28,32,48,56,64,96,
+ * 112,128,192,224,256,384,448,512,768,896,1024
+ * @dist_mode: Distribution mode
+ * @key_cfg_iova: I/O virtual address of 256 bytes DMA-able memory filled with
+ * the extractions to be used for the distribution key by calling
+ * dpni_prepare_key_cfg() relevant only when
+ * 'dist_mode != DPNI_DIST_MODE_NONE', otherwise it can be '0'
+ * @fs_cfg: Flow Steering table configuration; only relevant if
+ * 'dist_mode = DPNI_DIST_MODE_FS'
+ */
+struct dpni_rx_tc_dist_cfg {
+ uint16_t dist_size;
+ enum dpni_dist_mode dist_mode;
+ uint64_t key_cfg_iova;
+ struct dpni_fs_tbl_cfg fs_cfg;
+};
+
+/**
+ * dpni_set_rx_tc_dist() - Set Rx traffic class distribution configuration
+ * @mc_io: Pointer to MC portal's I/O object
+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
+ * @token: Token of DPNI object
+ * @tc_id: Traffic class selection (0-7)
+ * @cfg: Traffic class distribution configuration
+ *
+ * warning: if 'dist_mode != DPNI_DIST_MODE_NONE', call dpni_prepare_key_cfg()
+ * first to prepare the key_cfg_iova parameter
+ *
+ * Return: '0' on Success; error code otherwise.
+ */
+int dpni_set_rx_tc_dist(struct fsl_mc_io *mc_io,
+ uint32_t cmd_flags,
+ uint16_t token,
+ uint8_t tc_id,
+ const struct dpni_rx_tc_dist_cfg *cfg);
+
+/**
+ * enum dpni_dest - DPNI destination types
+ * @DPNI_DEST_NONE: Unassigned destination; The queue is set in parked mode and
+ * does not generate FQDAN notifications; user is expected to
+ * dequeue from the queue based on polling or other user-defined
+ * method
+ * @DPNI_DEST_DPIO: The queue is set in schedule mode and generates FQDAN
+ * notifications to the specified DPIO; user is expected to dequeue
+ * from the queue only after notification is received
+ * @DPNI_DEST_DPCON: The queue is set in schedule mode and does not generate
+ * FQDAN notifications, but is connected to the specified DPCON
+ * object; user is expected to dequeue from the DPCON channel
+ */
+enum dpni_dest {
+ DPNI_DEST_NONE = 0,
+ DPNI_DEST_DPIO = 1,
+ DPNI_DEST_DPCON = 2
+};
+
+
+/**
+ * struct dpni_queue - Queue structure
+ * @user_context: User data, presented to the user along with any frames
+ * from this queue. Not relevant for Tx queues.
+ */
+struct dpni_queue {
+ /**
+ * struct destination - Destination structure
+ * @id: ID of the destination, only relevant if DEST_TYPE is > 0.
+ * Identifies either a DPIO or a DPCON object.
+ * Not relevant for Tx queues.
+ * @type: May be one of the following:
+ * 0 - No destination, queue can be manually
+ * queried, but will not push traffic or
+ * notifications to a DPIO;
+ * 1 - The destination is a DPIO. When traffic
+ * becomes available in the queue a FQDAN
+ * (FQ data available notification) will be
+ * generated to selected DPIO;
+ * 2 - The destination is a DPCON. The queue is
+ * associated with a DPCON object for the
+ * purpose of scheduling between multiple
+ * queues. The DPCON may be independently
+ * configured to generate notifications.
+ * Not relevant for Tx queues.
+ * @hold_active: Hold active, maintains a queue scheduled for longer
+ * in a DPIO during dequeue to reduce spread of traffic.
+ * Only relevant if queues are
+ * not affined to a single DPIO.
+ */
+ struct {
+ uint16_t id;
+ enum dpni_dest type;
+ char hold_active;
+ uint8_t priority;
+ } destination;
+ uint64_t user_context;
+ /**
+ * struct flc - FD FLow Context structure
+ * @value: FLC value to set
+ * @stash_control: Boolean, indicates whether the 6 lowest
+ * significant bits are used for stash control.
+ */
+ struct {
+ uint64_t value;
+ char stash_control;
+ } flc;
+};
+
+/**
+ * struct dpni_queue_id - Queue identification, used for enqueue commands
+ * or queue control
+ * @fqid: FQID used for enqueueing to and/or configuration of this
+ * specific FQ
+ * @qdbin: Queueing bin, used to enqueue using QDID, DQBIN, QPRI.
+ * Only relevant for Tx queues.
+ */
+struct dpni_queue_id {
+ uint32_t fqid;
+ uint16_t qdbin;
+};
+
+/**
+ * enum dpni_confirmation_mode - Defines DPNI options supported for Tx
+ * confirmation
+ * @DPNI_CONF_AFFINE: For each Tx queue set associated with a sender there is
+ * an affine Tx Confirmation queue
+ * @DPNI_CONF_SINGLE: All Tx queues are associated with a single Tx
+ * confirmation queue
+ * @DPNI_CONF_DISABLE: Tx frames are not confirmed. This must be associated
+ * with proper FD set-up to have buffers release to a Buffer Pool, otherwise
+ * buffers will be leaked
+ */
+enum dpni_confirmation_mode {
+ DPNI_CONF_AFFINE,
+ DPNI_CONF_SINGLE,
+ DPNI_CONF_DISABLE,
+};
+
+/**
+ * dpni_set_tx_confirmation_mode() - Tx confirmation mode
+ * @mc_io: Pointer to MC portal's I/O object
+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
+ * @token: Token of DPNI object
+ * @mode: Tx confirmation mode
+ *
+ * This function is useful only when 'DPNI_OPT_TX_CONF_DISABLED' is not
+ * selected at DPNI creation.
+ * Calling this function with 'mode' set to DPNI_CONF_DISABLE disables all
+ * transmit confirmation (including the private confirmation queues), regardless
+ * of previous settings; Note that in this case, Tx error frames are still
+ * enqueued to the general transmit errors queue.
+ * Calling this function with 'mode' set to DPNI_CONF_SINGLE switches all
+ * Tx confirmations to a shared Tx conf queue. The ID of the queue when
+ * calling dpni_set/get_queue is -1.
+ *
+ * Return: '0' on Success; Error code otherwise.
+ */
+int dpni_set_tx_confirmation_mode(struct fsl_mc_io *mc_io,
+ uint32_t cmd_flags,
+ uint16_t token,
+ enum dpni_confirmation_mode mode);
+
+/**
+ * dpni_get_api_version() - Get Data Path Network Interface API version
+ * @mc_io: Pointer to MC portal's I/O object
+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
+ * @major_ver: Major version of data path network interface API
+ * @minor_ver: Minor version of data path network interface API
+ *
+ * Return: '0' on Success; Error code otherwise.
+ */
+int dpni_get_api_version(struct fsl_mc_io *mc_io,
+ uint32_t cmd_flags,
+ uint16_t *major_ver,
+ uint16_t *minor_ver);
+
+/**
+ * Set User Context
+ */
+#define DPNI_QUEUE_OPT_USER_CTX 0x00000001
+
+/**
+ * Set queue destination configuration
+ */
+#define DPNI_QUEUE_OPT_DEST 0x00000002
+
+/**
+ * Set FD[FLC] configuration for traffic on this queue. Note that FLC values
+ * set with dpni_add_fs_entry, if any, take precedence over values per queue.
+ */
+#define DPNI_QUEUE_OPT_FLC 0x00000004
+
+/**
+ * Set the queue to hold active mode. This prevents the queue from being
+ * rescheduled between DPIOs while it carries traffic and is active on one
+ * DPNI. Can help reduce reordering when servicing one queue on multiple
+ * CPUs, but the queue is also less likely to push data to multiple CPUs
+ * especially when congested.
+ */
+#define DPNI_QUEUE_OPT_HOLD_ACTIVE 0x00000008
+
+/**
+ * dpni_set_queue() - Set queue parameters
+ * @mc_io: Pointer to MC portal's I/O object
+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
+ * @token: Token of DPNI object
+ * @qtype: Type of queue - all queue types are supported, although
+ * the command is ignored for Tx
+ * @tc: Traffic class, in range 0 to NUM_TCS - 1
+ * @index: Selects the specific queue out of the set
+ * allocated for the same TC.Value must be in
+ * range 0 to NUM_QUEUES - 1
+ * @options: A combination of DPNI_QUEUE_OPT_ values that control
+ * what configuration options are set on the queue
+ * @queue: Queue configuration structure
+ *
+ * Return: '0' on Success; Error code otherwise.
+ */
+int dpni_set_queue(struct fsl_mc_io *mc_io,
+ uint32_t cmd_flags,
+ uint16_t token,
+ enum dpni_queue_type qtype,
+ uint8_t tc,
+ uint8_t index,
+ uint8_t options,
+ const struct dpni_queue *queue);
+
+/**
+ * dpni_get_queue() - Get queue parameters
+ * @mc_io: Pointer to MC portal's I/O object
+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
+ * @token: Token of DPNI object
+ * @qtype: Type of queue - all queue types are supported
+ * @tc: Traffic class, in range 0 to NUM_TCS - 1
+ * @index: Selects the specific queue out of the set allocated
+ * for the same TC. Value must be in range 0 to
+ * NUM_QUEUES - 1
+ * @queue: Queue configuration structure
+ * @qid: Queue identification
+ *
+ * This function returns current queue configuration which can be changed by
+ * calling dpni_set_queue, and queue identification information.
+ * Returned qid.fqid and/or qid.qdbin values can be used to:
+ * - enqueue traffic for Tx queues,
+ * - perform volatile dequeue for Rx and, if applicable, Tx confirmation
+ * clean-up,
+ * - retrieve queue state.
+ *
+ * All these operations are supported through the DPIO run-time API.
+ *
+ * Return: '0' on Success; Error code otherwise.
+ */
+int dpni_get_queue(struct fsl_mc_io *mc_io,
+ uint32_t cmd_flags,
+ uint16_t token,
+ enum dpni_queue_type qtype,
+ uint8_t tc,
+ uint8_t index,
+ struct dpni_queue *queue,
+ struct dpni_queue_id *qid);
+
+#endif /* __FSL_DPNI_H */
diff --git a/drivers/common/dpaa2/mc/fsl_dpni_cmd.h b/drivers/common/dpaa2/mc/fsl_dpni_cmd.h
new file mode 100644
index 0000000..e5226e2
--- /dev/null
+++ b/drivers/common/dpaa2/mc/fsl_dpni_cmd.h
@@ -0,0 +1,301 @@
+/* Copyright 2013-2016 Freescale Semiconductor Inc.
+ * Copyright (c) 2016 NXP.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of the above-listed copyright holders nor the
+ * names of any contributors may be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License ("GPL") as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+#ifndef _FSL_DPNI_CMD_H
+#define _FSL_DPNI_CMD_H
+
+/* DPNI Version */
+#define DPNI_VER_MAJOR 7
+#define DPNI_VER_MINOR 0
+
+/* Command IDs */
+#define DPNI_CMDID_OPEN ((0x801 << 4) | (0x1))
+#define DPNI_CMDID_CLOSE ((0x800 << 4) | (0x1))
+#define DPNI_CMDID_CREATE ((0x901 << 4) | (0x1))
+#define DPNI_CMDID_DESTROY ((0x981 << 4) | (0x1))
+#define DPNI_CMDID_GET_API_VERSION ((0xa01 << 4) | (0x1))
+
+#define DPNI_CMDID_ENABLE ((0x002 << 4) | (0x1))
+#define DPNI_CMDID_DISABLE ((0x003 << 4) | (0x1))
+#define DPNI_CMDID_GET_ATTR ((0x004 << 4) | (0x1))
+#define DPNI_CMDID_RESET ((0x005 << 4) | (0x1))
+#define DPNI_CMDID_IS_ENABLED ((0x006 << 4) | (0x1))
+
+#define DPNI_CMDID_SET_POOLS ((0x200 << 4) | (0x1))
+#define DPNI_CMDID_SET_ERRORS_BEHAVIOR ((0x20B << 4) | (0x1))
+
+#define DPNI_CMDID_GET_QDID ((0x210 << 4) | (0x1))
+#define DPNI_CMDID_SET_MAX_FRAME_LENGTH ((0x216 << 4) | (0x1))
+#define DPNI_CMDID_GET_MAX_FRAME_LENGTH ((0x217 << 4) | (0x1))
+
+#define DPNI_CMDID_SET_UNICAST_PROMISC ((0x222 << 4) | (0x1))
+#define DPNI_CMDID_GET_UNICAST_PROMISC ((0x223 << 4) | (0x1))
+#define DPNI_CMDID_SET_PRIM_MAC ((0x224 << 4) | (0x1))
+#define DPNI_CMDID_GET_PRIM_MAC ((0x225 << 4) | (0x1))
+
+#define DPNI_CMDID_SET_RX_TC_DIST ((0x235 << 4) | (0x1))
+
+#define DPNI_CMDID_GET_QUEUE ((0x25F << 4) | (0x1))
+#define DPNI_CMDID_SET_QUEUE ((0x260 << 4) | (0x1))
+
+#define DPNI_CMDID_GET_PORT_MAC_ADDR ((0x263 << 4) | (0x1))
+
+#define DPNI_CMDID_GET_BUFFER_LAYOUT ((0x264 << 4) | (0x1))
+#define DPNI_CMDID_SET_BUFFER_LAYOUT ((0x265 << 4) | (0x1))
+
+#define DPNI_CMDID_GET_OFFLOAD ((0x26B << 4) | (0x1))
+#define DPNI_CMDID_SET_OFFLOAD ((0x26C << 4) | (0x1))
+#define DPNI_CMDID_SET_TX_CONFIRMATION_MODE ((0x266 << 4) | (0x1))
+#define DPNI_CMDID_GET_TX_CONFIRMATION_MODE ((0x26D << 4) | (0x1))
+
+/* cmd, param, offset, width, type, arg_name */
+#define DPNI_CMD_OPEN(cmd, dpni_id) \
+ MC_CMD_OP(cmd, 0, 0, 32, int, dpni_id)
+
+/* cmd, param, offset, width, type, arg_name */
+#define DPNI_CMD_CREATE(cmd, cfg) \
+do { \
+ MC_CMD_OP(cmd, 0, 0, 32, uint32_t, (cfg)->options); \
+ MC_CMD_OP(cmd, 0, 32, 8, uint8_t, (cfg)->num_queues); \
+ MC_CMD_OP(cmd, 0, 40, 8, uint8_t, (cfg)->num_tcs); \
+ MC_CMD_OP(cmd, 0, 48, 8, uint8_t, (cfg)->mac_filter_entries); \
+ MC_CMD_OP(cmd, 1, 0, 8, uint8_t, (cfg)->vlan_filter_entries); \
+ MC_CMD_OP(cmd, 1, 16, 8, uint8_t, (cfg)->qos_entries); \
+ MC_CMD_OP(cmd, 1, 32, 16, uint16_t, (cfg)->fs_entries); \
+} while (0)
+
+/* cmd, param, offset, width, type, arg_name */
+#define DPNI_CMD_SET_POOLS(cmd, cfg) \
+do { \
+ MC_CMD_OP(cmd, 0, 0, 8, uint8_t, cfg->num_dpbp); \
+ MC_CMD_OP(cmd, 0, 8, 1, int, cfg->pools[0].backup_pool); \
+ MC_CMD_OP(cmd, 0, 9, 1, int, cfg->pools[1].backup_pool); \
+ MC_CMD_OP(cmd, 0, 10, 1, int, cfg->pools[2].backup_pool); \
+ MC_CMD_OP(cmd, 0, 11, 1, int, cfg->pools[3].backup_pool); \
+ MC_CMD_OP(cmd, 0, 12, 1, int, cfg->pools[4].backup_pool); \
+ MC_CMD_OP(cmd, 0, 13, 1, int, cfg->pools[5].backup_pool); \
+ MC_CMD_OP(cmd, 0, 14, 1, int, cfg->pools[6].backup_pool); \
+ MC_CMD_OP(cmd, 0, 15, 1, int, cfg->pools[7].backup_pool); \
+ MC_CMD_OP(cmd, 0, 32, 32, int, cfg->pools[0].dpbp_id); \
+ MC_CMD_OP(cmd, 4, 32, 16, uint16_t, cfg->pools[0].buffer_size);\
+ MC_CMD_OP(cmd, 1, 0, 32, int, cfg->pools[1].dpbp_id); \
+ MC_CMD_OP(cmd, 4, 48, 16, uint16_t, cfg->pools[1].buffer_size);\
+ MC_CMD_OP(cmd, 1, 32, 32, int, cfg->pools[2].dpbp_id); \
+ MC_CMD_OP(cmd, 5, 0, 16, uint16_t, cfg->pools[2].buffer_size);\
+ MC_CMD_OP(cmd, 2, 0, 32, int, cfg->pools[3].dpbp_id); \
+ MC_CMD_OP(cmd, 5, 16, 16, uint16_t, cfg->pools[3].buffer_size);\
+ MC_CMD_OP(cmd, 2, 32, 32, int, cfg->pools[4].dpbp_id); \
+ MC_CMD_OP(cmd, 5, 32, 16, uint16_t, cfg->pools[4].buffer_size);\
+ MC_CMD_OP(cmd, 3, 0, 32, int, cfg->pools[5].dpbp_id); \
+ MC_CMD_OP(cmd, 5, 48, 16, uint16_t, cfg->pools[5].buffer_size);\
+ MC_CMD_OP(cmd, 3, 32, 32, int, cfg->pools[6].dpbp_id); \
+ MC_CMD_OP(cmd, 6, 0, 16, uint16_t, cfg->pools[6].buffer_size);\
+ MC_CMD_OP(cmd, 4, 0, 32, int, cfg->pools[7].dpbp_id); \
+ MC_CMD_OP(cmd, 6, 16, 16, uint16_t, cfg->pools[7].buffer_size);\
+} while (0)
+
+/* cmd, param, offset, width, type, arg_name */
+#define DPNI_RSP_IS_ENABLED(cmd, en) \
+ MC_RSP_OP(cmd, 0, 0, 1, int, en)
+
+/* DPNI_CMD_GET_ATTR is not used, no input parameters */
+
+#define DPNI_RSP_GET_ATTR(cmd, attr) \
+do { \
+ MC_RSP_OP(cmd, 0, 0, 32, uint32_t, (attr)->options); \
+ MC_RSP_OP(cmd, 0, 32, 8, uint8_t, (attr)->num_queues); \
+ MC_RSP_OP(cmd, 0, 40, 8, uint8_t, (attr)->num_tcs); \
+ MC_RSP_OP(cmd, 0, 48, 8, uint8_t, (attr)->mac_filter_entries); \
+ MC_RSP_OP(cmd, 1, 0, 8, uint8_t, (attr)->vlan_filter_entries); \
+ MC_RSP_OP(cmd, 1, 16, 8, uint8_t, (attr)->qos_entries); \
+ MC_RSP_OP(cmd, 1, 32, 16, uint16_t, (attr)->fs_entries); \
+ MC_RSP_OP(cmd, 2, 0, 8, uint8_t, (attr)->qos_key_size); \
+ MC_RSP_OP(cmd, 2, 8, 8, uint8_t, (attr)->fs_key_size); \
+ MC_RSP_OP(cmd, 2, 16, 16, uint16_t, (attr)->wriop_version); \
+} while (0)
+
+/* cmd, param, offset, width, type, arg_name */
+#define DPNI_CMD_SET_ERRORS_BEHAVIOR(cmd, cfg) \
+do { \
+ MC_CMD_OP(cmd, 0, 0, 32, uint32_t, cfg->errors); \
+ MC_CMD_OP(cmd, 0, 32, 4, enum dpni_error_action, cfg->error_action); \
+ MC_CMD_OP(cmd, 0, 36, 1, int, cfg->set_frame_annotation); \
+} while (0)
+
+#define DPNI_CMD_GET_BUFFER_LAYOUT(cmd, qtype) \
+ MC_CMD_OP(cmd, 0, 0, 8, enum dpni_queue_type, qtype)
+
+#define DPNI_RSP_GET_BUFFER_LAYOUT(cmd, layout) \
+do { \
+ MC_RSP_OP(cmd, 0, 48, 1, char, (layout)->pass_timestamp); \
+ MC_RSP_OP(cmd, 0, 49, 1, char, (layout)->pass_parser_result); \
+ MC_RSP_OP(cmd, 0, 50, 1, char, (layout)->pass_frame_status); \
+ MC_RSP_OP(cmd, 1, 0, 16, uint16_t, (layout)->private_data_size); \
+ MC_RSP_OP(cmd, 1, 16, 16, uint16_t, (layout)->data_align); \
+ MC_RSP_OP(cmd, 1, 32, 16, uint16_t, (layout)->data_head_room); \
+ MC_RSP_OP(cmd, 1, 48, 16, uint16_t, (layout)->data_tail_room); \
+} while (0)
+
+#define DPNI_CMD_SET_BUFFER_LAYOUT(cmd, qtype, layout) \
+do { \
+ MC_CMD_OP(cmd, 0, 0, 8, enum dpni_queue_type, qtype); \
+ MC_CMD_OP(cmd, 0, 32, 16, uint16_t, (layout)->options); \
+ MC_CMD_OP(cmd, 0, 48, 1, char, (layout)->pass_timestamp); \
+ MC_CMD_OP(cmd, 0, 49, 1, char, (layout)->pass_parser_result); \
+ MC_CMD_OP(cmd, 0, 50, 1, char, (layout)->pass_frame_status); \
+ MC_CMD_OP(cmd, 1, 0, 16, uint16_t, (layout)->private_data_size); \
+ MC_CMD_OP(cmd, 1, 16, 16, uint16_t, (layout)->data_align); \
+ MC_CMD_OP(cmd, 1, 32, 16, uint16_t, (layout)->data_head_room); \
+ MC_CMD_OP(cmd, 1, 48, 16, uint16_t, (layout)->data_tail_room); \
+} while (0)
+
+#define DPNI_CMD_SET_OFFLOAD(cmd, type, config) \
+do { \
+ MC_CMD_OP(cmd, 0, 24, 8, enum dpni_offload, type); \
+ MC_CMD_OP(cmd, 0, 32, 32, uint32_t, config); \
+} while (0)
+
+#define DPNI_CMD_GET_OFFLOAD(cmd, type) \
+ MC_CMD_OP(cmd, 0, 24, 8, enum dpni_offload, type)
+
+#define DPNI_RSP_GET_OFFLOAD(cmd, config) \
+ MC_RSP_OP(cmd, 0, 32, 32, uint32_t, config)
+
+#define DPNI_CMD_GET_QDID(cmd, qtype) \
+ MC_CMD_OP(cmd, 0, 0, 8, enum dpni_queue_type, qtype)
+
+/* cmd, param, offset, width, type, arg_name */
+#define DPNI_RSP_GET_QDID(cmd, qdid) \
+ MC_RSP_OP(cmd, 0, 0, 16, uint16_t, qdid)
+
+
+/* cmd, param, offset, width, type, arg_name */
+#define DPNI_CMD_SET_MAX_FRAME_LENGTH(cmd, max_frame_length) \
+ MC_CMD_OP(cmd, 0, 0, 16, uint16_t, max_frame_length)
+
+/* cmd, param, offset, width, type, arg_name */
+#define DPNI_RSP_GET_MAX_FRAME_LENGTH(cmd, max_frame_length) \
+ MC_RSP_OP(cmd, 0, 0, 16, uint16_t, max_frame_length)
+
+/* cmd, param, offset, width, type, arg_name */
+#define DPNI_CMD_SET_UNICAST_PROMISC(cmd, en) \
+ MC_CMD_OP(cmd, 0, 0, 1, int, en)
+
+/* cmd, param, offset, width, type, arg_name */
+#define DPNI_RSP_GET_UNICAST_PROMISC(cmd, en) \
+ MC_RSP_OP(cmd, 0, 0, 1, int, en)
+
+/* cmd, param, offset, width, type, arg_name */
+#define DPNI_CMD_SET_PRIMARY_MAC_ADDR(cmd, mac_addr) \
+do { \
+ MC_CMD_OP(cmd, 0, 16, 8, uint8_t, mac_addr[5]); \
+ MC_CMD_OP(cmd, 0, 24, 8, uint8_t, mac_addr[4]); \
+ MC_CMD_OP(cmd, 0, 32, 8, uint8_t, mac_addr[3]); \
+ MC_CMD_OP(cmd, 0, 40, 8, uint8_t, mac_addr[2]); \
+ MC_CMD_OP(cmd, 0, 48, 8, uint8_t, mac_addr[1]); \
+ MC_CMD_OP(cmd, 0, 56, 8, uint8_t, mac_addr[0]); \
+} while (0)
+
+/* cmd, param, offset, width, type, arg_name */
+#define DPNI_RSP_GET_PRIMARY_MAC_ADDR(cmd, mac_addr) \
+do { \
+ MC_RSP_OP(cmd, 0, 16, 8, uint8_t, mac_addr[5]); \
+ MC_RSP_OP(cmd, 0, 24, 8, uint8_t, mac_addr[4]); \
+ MC_RSP_OP(cmd, 0, 32, 8, uint8_t, mac_addr[3]); \
+ MC_RSP_OP(cmd, 0, 40, 8, uint8_t, mac_addr[2]); \
+ MC_RSP_OP(cmd, 0, 48, 8, uint8_t, mac_addr[1]); \
+ MC_RSP_OP(cmd, 0, 56, 8, uint8_t, mac_addr[0]); \
+} while (0)
+
+
+/* cmd, param, offset, width, type, arg_name */
+#define DPNI_CMD_SET_RX_TC_DIST(cmd, tc_id, cfg) \
+do { \
+ MC_CMD_OP(cmd, 0, 0, 16, uint16_t, cfg->dist_size); \
+ MC_CMD_OP(cmd, 0, 16, 8, uint8_t, tc_id); \
+ MC_CMD_OP(cmd, 0, 24, 4, enum dpni_dist_mode, cfg->dist_mode); \
+ MC_CMD_OP(cmd, 0, 28, 4, enum dpni_fs_miss_action, \
+ cfg->fs_cfg.miss_action); \
+ MC_CMD_OP(cmd, 0, 48, 16, uint16_t, cfg->fs_cfg.default_flow_id); \
+ MC_CMD_OP(cmd, 6, 0, 64, uint64_t, cfg->key_cfg_iova); \
+} while (0)
+
+#define DPNI_CMD_GET_QUEUE(cmd, qtype, tc, index) \
+do { \
+ MC_CMD_OP(cmd, 0, 0, 8, enum dpni_queue_type, qtype); \
+ MC_CMD_OP(cmd, 0, 8, 8, uint8_t, tc); \
+ MC_CMD_OP(cmd, 0, 16, 8, uint8_t, index); \
+} while (0)
+
+#define DPNI_RSP_GET_QUEUE(cmd, queue, queue_id) \
+do { \
+ MC_RSP_OP(cmd, 1, 0, 32, uint32_t, (queue)->destination.id); \
+ MC_RSP_OP(cmd, 1, 48, 8, uint8_t, (queue)->destination.priority); \
+ MC_RSP_OP(cmd, 1, 56, 4, enum dpni_dest, (queue)->destination.type); \
+ MC_RSP_OP(cmd, 1, 62, 1, char, (queue)->flc.stash_control); \
+ MC_RSP_OP(cmd, 1, 63, 1, char, (queue)->destination.hold_active); \
+ MC_RSP_OP(cmd, 2, 0, 64, uint64_t, (queue)->flc.value); \
+ MC_RSP_OP(cmd, 3, 0, 64, uint64_t, (queue)->user_context); \
+ MC_RSP_OP(cmd, 4, 0, 32, uint32_t, (queue_id)->fqid); \
+ MC_RSP_OP(cmd, 4, 32, 16, uint16_t, (queue_id)->qdbin); \
+} while (0)
+
+#define DPNI_CMD_SET_QUEUE(cmd, qtype, tc, index, options, queue) \
+do { \
+ MC_CMD_OP(cmd, 0, 0, 8, enum dpni_queue_type, qtype); \
+ MC_CMD_OP(cmd, 0, 8, 8, uint8_t, tc); \
+ MC_CMD_OP(cmd, 0, 16, 8, uint8_t, index); \
+ MC_CMD_OP(cmd, 0, 24, 8, uint8_t, options); \
+ MC_CMD_OP(cmd, 1, 0, 32, uint32_t, (queue)->destination.id); \
+ MC_CMD_OP(cmd, 1, 48, 8, uint8_t, (queue)->destination.priority); \
+ MC_CMD_OP(cmd, 1, 56, 4, enum dpni_dest, (queue)->destination.type); \
+ MC_CMD_OP(cmd, 1, 62, 1, char, (queue)->flc.stash_control); \
+ MC_CMD_OP(cmd, 1, 63, 1, char, (queue)->destination.hold_active); \
+ MC_CMD_OP(cmd, 2, 0, 64, uint64_t, (queue)->flc.value); \
+ MC_CMD_OP(cmd, 3, 0, 64, uint64_t, (queue)->user_context); \
+} while (0)
+
+/* cmd, param, offset, width, type, arg_name */
+#define DPNI_RSP_GET_API_VERSION(cmd, major, minor) \
+do { \
+ MC_RSP_OP(cmd, 0, 0, 16, uint16_t, major);\
+ MC_RSP_OP(cmd, 0, 16, 16, uint16_t, minor);\
+} while (0)
+
+
+#define DPNI_CMD_SET_TX_CONFIRMATION_MODE(cmd, mode) \
+ MC_CMD_OP(cmd, 0, 32, 8, enum dpni_confirmation_mode, mode)
+
+#define DPNI_RSP_GET_TX_CONFIRMATION_MODE(cmd, mode) \
+ MC_RSP_OP(cmd, 0, 32, 8, enum dpni_confirmation_mode, mode)
+
+#endif /* _FSL_DPNI_CMD_H */
diff --git a/drivers/common/dpaa2/mc/fsl_net.h b/drivers/common/dpaa2/mc/fsl_net.h
new file mode 100644
index 0000000..cf5431b
--- /dev/null
+++ b/drivers/common/dpaa2/mc/fsl_net.h
@@ -0,0 +1,480 @@
+/* Copyright 2013-2015 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of the above-listed copyright holders nor the
+ * names of any contributors may be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License ("GPL") as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+#ifndef __FSL_NET_H
+#define __FSL_NET_H
+
+#define LAST_HDR_INDEX 0xFFFFFFFF
+
+/*****************************************************************************/
+/* Protocol fields */
+/*****************************************************************************/
+
+/************************* Ethernet fields *********************************/
+#define NH_FLD_ETH_DA (1)
+#define NH_FLD_ETH_SA (NH_FLD_ETH_DA << 1)
+#define NH_FLD_ETH_LENGTH (NH_FLD_ETH_DA << 2)
+#define NH_FLD_ETH_TYPE (NH_FLD_ETH_DA << 3)
+#define NH_FLD_ETH_FINAL_CKSUM (NH_FLD_ETH_DA << 4)
+#define NH_FLD_ETH_PADDING (NH_FLD_ETH_DA << 5)
+#define NH_FLD_ETH_ALL_FIELDS ((NH_FLD_ETH_DA << 6) - 1)
+
+#define NH_FLD_ETH_ADDR_SIZE 6
+
+/*************************** VLAN fields ***********************************/
+#define NH_FLD_VLAN_VPRI (1)
+#define NH_FLD_VLAN_CFI (NH_FLD_VLAN_VPRI << 1)
+#define NH_FLD_VLAN_VID (NH_FLD_VLAN_VPRI << 2)
+#define NH_FLD_VLAN_LENGTH (NH_FLD_VLAN_VPRI << 3)
+#define NH_FLD_VLAN_TYPE (NH_FLD_VLAN_VPRI << 4)
+#define NH_FLD_VLAN_ALL_FIELDS ((NH_FLD_VLAN_VPRI << 5) - 1)
+
+#define NH_FLD_VLAN_TCI (NH_FLD_VLAN_VPRI | \
+ NH_FLD_VLAN_CFI | \
+ NH_FLD_VLAN_VID)
+
+/************************ IP (generic) fields ******************************/
+#define NH_FLD_IP_VER (1)
+#define NH_FLD_IP_DSCP (NH_FLD_IP_VER << 2)
+#define NH_FLD_IP_ECN (NH_FLD_IP_VER << 3)
+#define NH_FLD_IP_PROTO (NH_FLD_IP_VER << 4)
+#define NH_FLD_IP_SRC (NH_FLD_IP_VER << 5)
+#define NH_FLD_IP_DST (NH_FLD_IP_VER << 6)
+#define NH_FLD_IP_TOS_TC (NH_FLD_IP_VER << 7)
+#define NH_FLD_IP_ID (NH_FLD_IP_VER << 8)
+#define NH_FLD_IP_ALL_FIELDS ((NH_FLD_IP_VER << 9) - 1)
+
+#define NH_FLD_IP_PROTO_SIZE 1
+
+/***************************** IPV4 fields *********************************/
+#define NH_FLD_IPV4_VER (1)
+#define NH_FLD_IPV4_HDR_LEN (NH_FLD_IPV4_VER << 1)
+#define NH_FLD_IPV4_TOS (NH_FLD_IPV4_VER << 2)
+#define NH_FLD_IPV4_TOTAL_LEN (NH_FLD_IPV4_VER << 3)
+#define NH_FLD_IPV4_ID (NH_FLD_IPV4_VER << 4)
+#define NH_FLD_IPV4_FLAG_D (NH_FLD_IPV4_VER << 5)
+#define NH_FLD_IPV4_FLAG_M (NH_FLD_IPV4_VER << 6)
+#define NH_FLD_IPV4_OFFSET (NH_FLD_IPV4_VER << 7)
+#define NH_FLD_IPV4_TTL (NH_FLD_IPV4_VER << 8)
+#define NH_FLD_IPV4_PROTO (NH_FLD_IPV4_VER << 9)
+#define NH_FLD_IPV4_CKSUM (NH_FLD_IPV4_VER << 10)
+#define NH_FLD_IPV4_SRC_IP (NH_FLD_IPV4_VER << 11)
+#define NH_FLD_IPV4_DST_IP (NH_FLD_IPV4_VER << 12)
+#define NH_FLD_IPV4_OPTS (NH_FLD_IPV4_VER << 13)
+#define NH_FLD_IPV4_OPTS_COUNT (NH_FLD_IPV4_VER << 14)
+#define NH_FLD_IPV4_ALL_FIELDS ((NH_FLD_IPV4_VER << 15) - 1)
+
+#define NH_FLD_IPV4_ADDR_SIZE 4
+#define NH_FLD_IPV4_PROTO_SIZE 1
+
+/***************************** IPV6 fields *********************************/
+#define NH_FLD_IPV6_VER (1)
+#define NH_FLD_IPV6_TC (NH_FLD_IPV6_VER << 1)
+#define NH_FLD_IPV6_SRC_IP (NH_FLD_IPV6_VER << 2)
+#define NH_FLD_IPV6_DST_IP (NH_FLD_IPV6_VER << 3)
+#define NH_FLD_IPV6_NEXT_HDR (NH_FLD_IPV6_VER << 4)
+#define NH_FLD_IPV6_FL (NH_FLD_IPV6_VER << 5)
+#define NH_FLD_IPV6_HOP_LIMIT (NH_FLD_IPV6_VER << 6)
+#define NH_FLD_IPV6_ID (NH_FLD_IPV6_VER << 7)
+#define NH_FLD_IPV6_ALL_FIELDS ((NH_FLD_IPV6_VER << 8) - 1)
+
+#define NH_FLD_IPV6_ADDR_SIZE 16
+#define NH_FLD_IPV6_NEXT_HDR_SIZE 1
+
+/***************************** ICMP fields *********************************/
+#define NH_FLD_ICMP_TYPE (1)
+#define NH_FLD_ICMP_CODE (NH_FLD_ICMP_TYPE << 1)
+#define NH_FLD_ICMP_CKSUM (NH_FLD_ICMP_TYPE << 2)
+#define NH_FLD_ICMP_ID (NH_FLD_ICMP_TYPE << 3)
+#define NH_FLD_ICMP_SQ_NUM (NH_FLD_ICMP_TYPE << 4)
+#define NH_FLD_ICMP_ALL_FIELDS ((NH_FLD_ICMP_TYPE << 5) - 1)
+
+#define NH_FLD_ICMP_CODE_SIZE 1
+#define NH_FLD_ICMP_TYPE_SIZE 1
+
+/***************************** IGMP fields *********************************/
+#define NH_FLD_IGMP_VERSION (1)
+#define NH_FLD_IGMP_TYPE (NH_FLD_IGMP_VERSION << 1)
+#define NH_FLD_IGMP_CKSUM (NH_FLD_IGMP_VERSION << 2)
+#define NH_FLD_IGMP_DATA (NH_FLD_IGMP_VERSION << 3)
+#define NH_FLD_IGMP_ALL_FIELDS ((NH_FLD_IGMP_VERSION << 4) - 1)
+
+/***************************** TCP fields **********************************/
+#define NH_FLD_TCP_PORT_SRC (1)
+#define NH_FLD_TCP_PORT_DST (NH_FLD_TCP_PORT_SRC << 1)
+#define NH_FLD_TCP_SEQ (NH_FLD_TCP_PORT_SRC << 2)
+#define NH_FLD_TCP_ACK (NH_FLD_TCP_PORT_SRC << 3)
+#define NH_FLD_TCP_OFFSET (NH_FLD_TCP_PORT_SRC << 4)
+#define NH_FLD_TCP_FLAGS (NH_FLD_TCP_PORT_SRC << 5)
+#define NH_FLD_TCP_WINDOW (NH_FLD_TCP_PORT_SRC << 6)
+#define NH_FLD_TCP_CKSUM (NH_FLD_TCP_PORT_SRC << 7)
+#define NH_FLD_TCP_URGPTR (NH_FLD_TCP_PORT_SRC << 8)
+#define NH_FLD_TCP_OPTS (NH_FLD_TCP_PORT_SRC << 9)
+#define NH_FLD_TCP_OPTS_COUNT (NH_FLD_TCP_PORT_SRC << 10)
+#define NH_FLD_TCP_ALL_FIELDS ((NH_FLD_TCP_PORT_SRC << 11) - 1)
+
+#define NH_FLD_TCP_PORT_SIZE 2
+
+/***************************** UDP fields **********************************/
+#define NH_FLD_UDP_PORT_SRC (1)
+#define NH_FLD_UDP_PORT_DST (NH_FLD_UDP_PORT_SRC << 1)
+#define NH_FLD_UDP_LEN (NH_FLD_UDP_PORT_SRC << 2)
+#define NH_FLD_UDP_CKSUM (NH_FLD_UDP_PORT_SRC << 3)
+#define NH_FLD_UDP_ALL_FIELDS ((NH_FLD_UDP_PORT_SRC << 4) - 1)
+
+#define NH_FLD_UDP_PORT_SIZE 2
+
+/*************************** UDP-lite fields *******************************/
+#define NH_FLD_UDP_LITE_PORT_SRC (1)
+#define NH_FLD_UDP_LITE_PORT_DST (NH_FLD_UDP_LITE_PORT_SRC << 1)
+#define NH_FLD_UDP_LITE_ALL_FIELDS \
+ ((NH_FLD_UDP_LITE_PORT_SRC << 2) - 1)
+
+#define NH_FLD_UDP_LITE_PORT_SIZE 2
+
+/*************************** UDP-encap-ESP fields **************************/
+#define NH_FLD_UDP_ENC_ESP_PORT_SRC (1)
+#define NH_FLD_UDP_ENC_ESP_PORT_DST (NH_FLD_UDP_ENC_ESP_PORT_SRC << 1)
+#define NH_FLD_UDP_ENC_ESP_LEN (NH_FLD_UDP_ENC_ESP_PORT_SRC << 2)
+#define NH_FLD_UDP_ENC_ESP_CKSUM (NH_FLD_UDP_ENC_ESP_PORT_SRC << 3)
+#define NH_FLD_UDP_ENC_ESP_SPI (NH_FLD_UDP_ENC_ESP_PORT_SRC << 4)
+#define NH_FLD_UDP_ENC_ESP_SEQUENCE_NUM (NH_FLD_UDP_ENC_ESP_PORT_SRC << 5)
+#define NH_FLD_UDP_ENC_ESP_ALL_FIELDS \
+ ((NH_FLD_UDP_ENC_ESP_PORT_SRC << 6) - 1)
+
+#define NH_FLD_UDP_ENC_ESP_PORT_SIZE 2
+#define NH_FLD_UDP_ENC_ESP_SPI_SIZE 4
+
+/***************************** SCTP fields *********************************/
+#define NH_FLD_SCTP_PORT_SRC (1)
+#define NH_FLD_SCTP_PORT_DST (NH_FLD_SCTP_PORT_SRC << 1)
+#define NH_FLD_SCTP_VER_TAG (NH_FLD_SCTP_PORT_SRC << 2)
+#define NH_FLD_SCTP_CKSUM (NH_FLD_SCTP_PORT_SRC << 3)
+#define NH_FLD_SCTP_ALL_FIELDS ((NH_FLD_SCTP_PORT_SRC << 4) - 1)
+
+#define NH_FLD_SCTP_PORT_SIZE 2
+
+/***************************** DCCP fields *********************************/
+#define NH_FLD_DCCP_PORT_SRC (1)
+#define NH_FLD_DCCP_PORT_DST (NH_FLD_DCCP_PORT_SRC << 1)
+#define NH_FLD_DCCP_ALL_FIELDS ((NH_FLD_DCCP_PORT_SRC << 2) - 1)
+
+#define NH_FLD_DCCP_PORT_SIZE 2
+
+/***************************** IPHC fields *********************************/
+#define NH_FLD_IPHC_CID (1)
+#define NH_FLD_IPHC_CID_TYPE (NH_FLD_IPHC_CID << 1)
+#define NH_FLD_IPHC_HCINDEX (NH_FLD_IPHC_CID << 2)
+#define NH_FLD_IPHC_GEN (NH_FLD_IPHC_CID << 3)
+#define NH_FLD_IPHC_D_BIT (NH_FLD_IPHC_CID << 4)
+#define NH_FLD_IPHC_ALL_FIELDS ((NH_FLD_IPHC_CID << 5) - 1)
+
+/***************************** SCTP fields *********************************/
+#define NH_FLD_SCTP_CHUNK_DATA_TYPE (1)
+#define NH_FLD_SCTP_CHUNK_DATA_FLAGS (NH_FLD_SCTP_CHUNK_DATA_TYPE << 1)
+#define NH_FLD_SCTP_CHUNK_DATA_LENGTH (NH_FLD_SCTP_CHUNK_DATA_TYPE << 2)
+#define NH_FLD_SCTP_CHUNK_DATA_TSN (NH_FLD_SCTP_CHUNK_DATA_TYPE << 3)
+#define NH_FLD_SCTP_CHUNK_DATA_STREAM_ID (NH_FLD_SCTP_CHUNK_DATA_TYPE << 4)
+#define NH_FLD_SCTP_CHUNK_DATA_STREAM_SQN (NH_FLD_SCTP_CHUNK_DATA_TYPE << 5)
+#define NH_FLD_SCTP_CHUNK_DATA_PAYLOAD_PID (NH_FLD_SCTP_CHUNK_DATA_TYPE << 6)
+#define NH_FLD_SCTP_CHUNK_DATA_UNORDERED (NH_FLD_SCTP_CHUNK_DATA_TYPE << 7)
+#define NH_FLD_SCTP_CHUNK_DATA_BEGINNING (NH_FLD_SCTP_CHUNK_DATA_TYPE << 8)
+#define NH_FLD_SCTP_CHUNK_DATA_END (NH_FLD_SCTP_CHUNK_DATA_TYPE << 9)
+#define NH_FLD_SCTP_CHUNK_DATA_ALL_FIELDS \
+ ((NH_FLD_SCTP_CHUNK_DATA_TYPE << 10) - 1)
+
+/*************************** L2TPV2 fields *********************************/
+#define NH_FLD_L2TPV2_TYPE_BIT (1)
+#define NH_FLD_L2TPV2_LENGTH_BIT (NH_FLD_L2TPV2_TYPE_BIT << 1)
+#define NH_FLD_L2TPV2_SEQUENCE_BIT (NH_FLD_L2TPV2_TYPE_BIT << 2)
+#define NH_FLD_L2TPV2_OFFSET_BIT (NH_FLD_L2TPV2_TYPE_BIT << 3)
+#define NH_FLD_L2TPV2_PRIORITY_BIT (NH_FLD_L2TPV2_TYPE_BIT << 4)
+#define NH_FLD_L2TPV2_VERSION (NH_FLD_L2TPV2_TYPE_BIT << 5)
+#define NH_FLD_L2TPV2_LEN (NH_FLD_L2TPV2_TYPE_BIT << 6)
+#define NH_FLD_L2TPV2_TUNNEL_ID (NH_FLD_L2TPV2_TYPE_BIT << 7)
+#define NH_FLD_L2TPV2_SESSION_ID (NH_FLD_L2TPV2_TYPE_BIT << 8)
+#define NH_FLD_L2TPV2_NS (NH_FLD_L2TPV2_TYPE_BIT << 9)
+#define NH_FLD_L2TPV2_NR (NH_FLD_L2TPV2_TYPE_BIT << 10)
+#define NH_FLD_L2TPV2_OFFSET_SIZE (NH_FLD_L2TPV2_TYPE_BIT << 11)
+#define NH_FLD_L2TPV2_FIRST_BYTE (NH_FLD_L2TPV2_TYPE_BIT << 12)
+#define NH_FLD_L2TPV2_ALL_FIELDS \
+ ((NH_FLD_L2TPV2_TYPE_BIT << 13) - 1)
+
+/*************************** L2TPV3 fields *********************************/
+#define NH_FLD_L2TPV3_CTRL_TYPE_BIT (1)
+#define NH_FLD_L2TPV3_CTRL_LENGTH_BIT (NH_FLD_L2TPV3_CTRL_TYPE_BIT << 1)
+#define NH_FLD_L2TPV3_CTRL_SEQUENCE_BIT (NH_FLD_L2TPV3_CTRL_TYPE_BIT << 2)
+#define NH_FLD_L2TPV3_CTRL_VERSION (NH_FLD_L2TPV3_CTRL_TYPE_BIT << 3)
+#define NH_FLD_L2TPV3_CTRL_LENGTH (NH_FLD_L2TPV3_CTRL_TYPE_BIT << 4)
+#define NH_FLD_L2TPV3_CTRL_CONTROL (NH_FLD_L2TPV3_CTRL_TYPE_BIT << 5)
+#define NH_FLD_L2TPV3_CTRL_SENT (NH_FLD_L2TPV3_CTRL_TYPE_BIT << 6)
+#define NH_FLD_L2TPV3_CTRL_RECV (NH_FLD_L2TPV3_CTRL_TYPE_BIT << 7)
+#define NH_FLD_L2TPV3_CTRL_FIRST_BYTE (NH_FLD_L2TPV3_CTRL_TYPE_BIT << 8)
+#define NH_FLD_L2TPV3_CTRL_ALL_FIELDS \
+ ((NH_FLD_L2TPV3_CTRL_TYPE_BIT << 9) - 1)
+
+#define NH_FLD_L2TPV3_SESS_TYPE_BIT (1)
+#define NH_FLD_L2TPV3_SESS_VERSION (NH_FLD_L2TPV3_SESS_TYPE_BIT << 1)
+#define NH_FLD_L2TPV3_SESS_ID (NH_FLD_L2TPV3_SESS_TYPE_BIT << 2)
+#define NH_FLD_L2TPV3_SESS_COOKIE (NH_FLD_L2TPV3_SESS_TYPE_BIT << 3)
+#define NH_FLD_L2TPV3_SESS_ALL_FIELDS \
+ ((NH_FLD_L2TPV3_SESS_TYPE_BIT << 4) - 1)
+
+/**************************** PPP fields ***********************************/
+#define NH_FLD_PPP_PID (1)
+#define NH_FLD_PPP_COMPRESSED (NH_FLD_PPP_PID << 1)
+#define NH_FLD_PPP_ALL_FIELDS ((NH_FLD_PPP_PID << 2) - 1)
+
+/************************** PPPoE fields ***********************************/
+#define NH_FLD_PPPOE_VER (1)
+#define NH_FLD_PPPOE_TYPE (NH_FLD_PPPOE_VER << 1)
+#define NH_FLD_PPPOE_CODE (NH_FLD_PPPOE_VER << 2)
+#define NH_FLD_PPPOE_SID (NH_FLD_PPPOE_VER << 3)
+#define NH_FLD_PPPOE_LEN (NH_FLD_PPPOE_VER << 4)
+#define NH_FLD_PPPOE_SESSION (NH_FLD_PPPOE_VER << 5)
+#define NH_FLD_PPPOE_PID (NH_FLD_PPPOE_VER << 6)
+#define NH_FLD_PPPOE_ALL_FIELDS ((NH_FLD_PPPOE_VER << 7) - 1)
+
+/************************* PPP-Mux fields **********************************/
+#define NH_FLD_PPPMUX_PID (1)
+#define NH_FLD_PPPMUX_CKSUM (NH_FLD_PPPMUX_PID << 1)
+#define NH_FLD_PPPMUX_COMPRESSED (NH_FLD_PPPMUX_PID << 2)
+#define NH_FLD_PPPMUX_ALL_FIELDS ((NH_FLD_PPPMUX_PID << 3) - 1)
+
+/*********************** PPP-Mux sub-frame fields **************************/
+#define NH_FLD_PPPMUX_SUBFRM_PFF (1)
+#define NH_FLD_PPPMUX_SUBFRM_LXT (NH_FLD_PPPMUX_SUBFRM_PFF << 1)
+#define NH_FLD_PPPMUX_SUBFRM_LEN (NH_FLD_PPPMUX_SUBFRM_PFF << 2)
+#define NH_FLD_PPPMUX_SUBFRM_PID (NH_FLD_PPPMUX_SUBFRM_PFF << 3)
+#define NH_FLD_PPPMUX_SUBFRM_USE_PID (NH_FLD_PPPMUX_SUBFRM_PFF << 4)
+#define NH_FLD_PPPMUX_SUBFRM_ALL_FIELDS \
+ ((NH_FLD_PPPMUX_SUBFRM_PFF << 5) - 1)
+
+/*************************** LLC fields ************************************/
+#define NH_FLD_LLC_DSAP (1)
+#define NH_FLD_LLC_SSAP (NH_FLD_LLC_DSAP << 1)
+#define NH_FLD_LLC_CTRL (NH_FLD_LLC_DSAP << 2)
+#define NH_FLD_LLC_ALL_FIELDS ((NH_FLD_LLC_DSAP << 3) - 1)
+
+/*************************** NLPID fields **********************************/
+#define NH_FLD_NLPID_NLPID (1)
+#define NH_FLD_NLPID_ALL_FIELDS ((NH_FLD_NLPID_NLPID << 1) - 1)
+
+/*************************** SNAP fields ***********************************/
+#define NH_FLD_SNAP_OUI (1)
+#define NH_FLD_SNAP_PID (NH_FLD_SNAP_OUI << 1)
+#define NH_FLD_SNAP_ALL_FIELDS ((NH_FLD_SNAP_OUI << 2) - 1)
+
+/*************************** LLC SNAP fields *******************************/
+#define NH_FLD_LLC_SNAP_TYPE (1)
+#define NH_FLD_LLC_SNAP_ALL_FIELDS ((NH_FLD_LLC_SNAP_TYPE << 1) - 1)
+
+#define NH_FLD_ARP_HTYPE (1)
+#define NH_FLD_ARP_PTYPE (NH_FLD_ARP_HTYPE << 1)
+#define NH_FLD_ARP_HLEN (NH_FLD_ARP_HTYPE << 2)
+#define NH_FLD_ARP_PLEN (NH_FLD_ARP_HTYPE << 3)
+#define NH_FLD_ARP_OPER (NH_FLD_ARP_HTYPE << 4)
+#define NH_FLD_ARP_SHA (NH_FLD_ARP_HTYPE << 5)
+#define NH_FLD_ARP_SPA (NH_FLD_ARP_HTYPE << 6)
+#define NH_FLD_ARP_THA (NH_FLD_ARP_HTYPE << 7)
+#define NH_FLD_ARP_TPA (NH_FLD_ARP_HTYPE << 8)
+#define NH_FLD_ARP_ALL_FIELDS ((NH_FLD_ARP_HTYPE << 9) - 1)
+
+/*************************** RFC2684 fields ********************************/
+#define NH_FLD_RFC2684_LLC (1)
+#define NH_FLD_RFC2684_NLPID (NH_FLD_RFC2684_LLC << 1)
+#define NH_FLD_RFC2684_OUI (NH_FLD_RFC2684_LLC << 2)
+#define NH_FLD_RFC2684_PID (NH_FLD_RFC2684_LLC << 3)
+#define NH_FLD_RFC2684_VPN_OUI (NH_FLD_RFC2684_LLC << 4)
+#define NH_FLD_RFC2684_VPN_IDX (NH_FLD_RFC2684_LLC << 5)
+#define NH_FLD_RFC2684_ALL_FIELDS ((NH_FLD_RFC2684_LLC << 6) - 1)
+
+/*************************** User defined fields ***************************/
+#define NH_FLD_USER_DEFINED_SRCPORT (1)
+#define NH_FLD_USER_DEFINED_PCDID (NH_FLD_USER_DEFINED_SRCPORT << 1)
+#define NH_FLD_USER_DEFINED_ALL_FIELDS \
+ ((NH_FLD_USER_DEFINED_SRCPORT << 2) - 1)
+
+/*************************** Payload fields ********************************/
+#define NH_FLD_PAYLOAD_BUFFER (1)
+#define NH_FLD_PAYLOAD_SIZE (NH_FLD_PAYLOAD_BUFFER << 1)
+#define NH_FLD_MAX_FRM_SIZE (NH_FLD_PAYLOAD_BUFFER << 2)
+#define NH_FLD_MIN_FRM_SIZE (NH_FLD_PAYLOAD_BUFFER << 3)
+#define NH_FLD_PAYLOAD_TYPE (NH_FLD_PAYLOAD_BUFFER << 4)
+#define NH_FLD_FRAME_SIZE (NH_FLD_PAYLOAD_BUFFER << 5)
+#define NH_FLD_PAYLOAD_ALL_FIELDS ((NH_FLD_PAYLOAD_BUFFER << 6) - 1)
+
+/*************************** GRE fields ************************************/
+#define NH_FLD_GRE_TYPE (1)
+#define NH_FLD_GRE_ALL_FIELDS ((NH_FLD_GRE_TYPE << 1) - 1)
+
+/*************************** MINENCAP fields *******************************/
+#define NH_FLD_MINENCAP_SRC_IP (1)
+#define NH_FLD_MINENCAP_DST_IP (NH_FLD_MINENCAP_SRC_IP << 1)
+#define NH_FLD_MINENCAP_TYPE (NH_FLD_MINENCAP_SRC_IP << 2)
+#define NH_FLD_MINENCAP_ALL_FIELDS \
+ ((NH_FLD_MINENCAP_SRC_IP << 3) - 1)
+
+/*************************** IPSEC AH fields *******************************/
+#define NH_FLD_IPSEC_AH_SPI (1)
+#define NH_FLD_IPSEC_AH_NH (NH_FLD_IPSEC_AH_SPI << 1)
+#define NH_FLD_IPSEC_AH_ALL_FIELDS ((NH_FLD_IPSEC_AH_SPI << 2) - 1)
+
+/*************************** IPSEC ESP fields ******************************/
+#define NH_FLD_IPSEC_ESP_SPI (1)
+#define NH_FLD_IPSEC_ESP_SEQUENCE_NUM (NH_FLD_IPSEC_ESP_SPI << 1)
+#define NH_FLD_IPSEC_ESP_ALL_FIELDS ((NH_FLD_IPSEC_ESP_SPI << 2) - 1)
+
+#define NH_FLD_IPSEC_ESP_SPI_SIZE 4
+
+/*************************** MPLS fields ***********************************/
+#define NH_FLD_MPLS_LABEL_STACK (1)
+#define NH_FLD_MPLS_LABEL_STACK_ALL_FIELDS \
+ ((NH_FLD_MPLS_LABEL_STACK << 1) - 1)
+
+/*************************** MACSEC fields *********************************/
+#define NH_FLD_MACSEC_SECTAG (1)
+#define NH_FLD_MACSEC_ALL_FIELDS ((NH_FLD_MACSEC_SECTAG << 1) - 1)
+
+/*************************** GTP fields ************************************/
+#define NH_FLD_GTP_TEID (1)
+
+/* Protocol options */
+
+/* Ethernet options */
+#define NH_OPT_ETH_BROADCAST 1
+#define NH_OPT_ETH_MULTICAST 2
+#define NH_OPT_ETH_UNICAST 3
+#define NH_OPT_ETH_BPDU 4
+
+#define NH_ETH_IS_MULTICAST_ADDR(addr) (addr[0] & 0x01)
+/* also applicable for broadcast */
+
+/* VLAN options */
+#define NH_OPT_VLAN_CFI 1
+
+/* IPV4 options */
+#define NH_OPT_IPV4_UNICAST 1
+#define NH_OPT_IPV4_MULTICAST 2
+#define NH_OPT_IPV4_BROADCAST 3
+#define NH_OPT_IPV4_OPTION 4
+#define NH_OPT_IPV4_FRAG 5
+#define NH_OPT_IPV4_INITIAL_FRAG 6
+
+/* IPV6 options */
+#define NH_OPT_IPV6_UNICAST 1
+#define NH_OPT_IPV6_MULTICAST 2
+#define NH_OPT_IPV6_OPTION 3
+#define NH_OPT_IPV6_FRAG 4
+#define NH_OPT_IPV6_INITIAL_FRAG 5
+
+/* General IP options (may be used for any version) */
+#define NH_OPT_IP_FRAG 1
+#define NH_OPT_IP_INITIAL_FRAG 2
+#define NH_OPT_IP_OPTION 3
+
+/* Minenc. options */
+#define NH_OPT_MINENCAP_SRC_ADDR_PRESENT 1
+
+/* GRE. options */
+#define NH_OPT_GRE_ROUTING_PRESENT 1
+
+/* TCP options */
+#define NH_OPT_TCP_OPTIONS 1
+#define NH_OPT_TCP_CONTROL_HIGH_BITS 2
+#define NH_OPT_TCP_CONTROL_LOW_BITS 3
+
+/* CAPWAP options */
+#define NH_OPT_CAPWAP_DTLS 1
+
+enum net_prot {
+ NET_PROT_NONE = 0,
+ NET_PROT_PAYLOAD,
+ NET_PROT_ETH,
+ NET_PROT_VLAN,
+ NET_PROT_IPV4,
+ NET_PROT_IPV6,
+ NET_PROT_IP,
+ NET_PROT_TCP,
+ NET_PROT_UDP,
+ NET_PROT_UDP_LITE,
+ NET_PROT_IPHC,
+ NET_PROT_SCTP,
+ NET_PROT_SCTP_CHUNK_DATA,
+ NET_PROT_PPPOE,
+ NET_PROT_PPP,
+ NET_PROT_PPPMUX,
+ NET_PROT_PPPMUX_SUBFRM,
+ NET_PROT_L2TPV2,
+ NET_PROT_L2TPV3_CTRL,
+ NET_PROT_L2TPV3_SESS,
+ NET_PROT_LLC,
+ NET_PROT_LLC_SNAP,
+ NET_PROT_NLPID,
+ NET_PROT_SNAP,
+ NET_PROT_MPLS,
+ NET_PROT_IPSEC_AH,
+ NET_PROT_IPSEC_ESP,
+ NET_PROT_UDP_ENC_ESP, /* RFC 3948 */
+ NET_PROT_MACSEC,
+ NET_PROT_GRE,
+ NET_PROT_MINENCAP,
+ NET_PROT_DCCP,
+ NET_PROT_ICMP,
+ NET_PROT_IGMP,
+ NET_PROT_ARP,
+ NET_PROT_CAPWAP_DATA,
+ NET_PROT_CAPWAP_CTRL,
+ NET_PROT_RFC2684,
+ NET_PROT_ICMPV6,
+ NET_PROT_FCOE,
+ NET_PROT_FIP,
+ NET_PROT_ISCSI,
+ NET_PROT_GTP,
+ NET_PROT_USER_DEFINED_L2,
+ NET_PROT_USER_DEFINED_L3,
+ NET_PROT_USER_DEFINED_L4,
+ NET_PROT_USER_DEFINED_L5,
+ NET_PROT_USER_DEFINED_SHIM1,
+ NET_PROT_USER_DEFINED_SHIM2,
+
+ NET_PROT_DUMMY_LAST
+};
+
+/*! IEEE8021.Q */
+#define NH_IEEE8021Q_ETYPE 0x8100
+#define NH_IEEE8021Q_HDR(etype, pcp, dei, vlan_id) \
+ ((((uint32_t)(etype & 0xFFFF)) << 16) | \
+ (((uint32_t)(pcp & 0x07)) << 13) | \
+ (((uint32_t)(dei & 0x01)) << 12) | \
+ (((uint32_t)(vlan_id & 0xFFF))))
+
+#endif /* __FSL_NET_H */
--
1.9.1
next prev parent reply other threads:[~2016-12-04 12:43 UTC|newest]
Thread overview: 549+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-12-04 18:16 [PATCH 00/32] NXP DPAA2 PMD Hemant Agrawal
2016-12-04 18:16 ` [PATCH 01/32] doc: add dpaa2 nic details Hemant Agrawal
2016-12-05 17:12 ` Mcnamara, John
2016-12-06 13:58 ` Hemant Agrawal
2016-12-06 19:48 ` Ferruh Yigit
2016-12-04 18:16 ` [PATCH 02/32] drivers/common: introducing dpaa2 mc driver Hemant Agrawal
2016-12-06 19:48 ` Ferruh Yigit
2016-12-12 10:32 ` Hemant Agrawal
2016-12-15 6:04 ` Jerin Jacob
2016-12-19 5:27 ` Hemant Agrawal
2016-12-17 9:55 ` Jerin Jacob
2016-12-19 15:23 ` Hemant Agrawal
2016-12-04 18:16 ` Hemant Agrawal [this message]
2016-12-04 18:16 ` [PATCH 04/32] drivers/common/dpaa2: add mc dpio object support Hemant Agrawal
2016-12-04 18:17 ` [PATCH 05/32] drivers/common/dpaa2: add mc dpbp " Hemant Agrawal
2016-12-04 18:17 ` [PATCH 06/32] drivers/common/dpaa2: add mc dpseci " Hemant Agrawal
2016-12-04 18:17 ` [PATCH 07/32] drivers/common/dpaa2: adding qbman driver Hemant Agrawal
2016-12-04 18:17 ` [PATCH 08/32] mk/dpaa2: add the crc support to the machine type Hemant Agrawal
2016-12-15 6:35 ` Jerin Jacob
2016-12-04 18:17 ` [PATCH 09/32] lib/ether: add rte_device in rte_eth_dev Hemant Agrawal
2016-12-06 19:48 ` Ferruh Yigit
2016-12-07 6:41 ` Hemant Agrawal
2016-12-15 14:41 ` Ferruh Yigit
2016-12-19 5:30 ` Hemant Agrawal
2016-12-04 18:17 ` [PATCH 10/32] net/dpaa2: introducing dpaa2 bus driver for fsl-mc bus Hemant Agrawal
2016-12-06 19:49 ` Ferruh Yigit
2016-12-07 6:57 ` Hemant Agrawal
2016-12-07 10:13 ` Shreyansh Jain
2016-12-07 10:40 ` Thomas Monjalon
2016-12-07 12:21 ` David Marchand
2016-12-07 12:32 ` Hemant Agrawal
2016-12-04 18:17 ` [PATCH 11/32] net/dpaa2: add dpaa2 vfio support Hemant Agrawal
2016-12-06 21:04 ` Thomas Monjalon
2016-12-07 7:00 ` Hemant Agrawal
2016-12-07 8:38 ` Thomas Monjalon
2016-12-07 10:04 ` Hemant Agrawal
2016-12-04 18:17 ` [PATCH 12/32] net/dpaa2: vfio scan for net and sec device Hemant Agrawal
2016-12-04 18:17 ` [PATCH 13/32] net/dpaa2: add debug log macros Hemant Agrawal
2016-12-06 19:49 ` Ferruh Yigit
2016-12-19 15:24 ` Hemant Agrawal
2016-12-04 18:17 ` [PATCH 14/32] net/dpaa2: dpio object driver Hemant Agrawal
2016-12-04 18:17 ` [PATCH 15/32] net/dpaa2: dpio routine to affine to crypto threads Hemant Agrawal
2016-12-06 19:49 ` Ferruh Yigit
2016-12-19 15:25 ` Hemant Agrawal
2016-12-04 18:17 ` [PATCH 16/32] net/dpaa2: dpio add support to check SOC type Hemant Agrawal
2016-12-15 6:34 ` Jerin Jacob
2016-12-15 7:01 ` Hemant Agrawal
2016-12-04 18:17 ` [PATCH 17/32] net/dpaa2: dpbp based mempool hw offload driver Hemant Agrawal
2016-12-06 19:49 ` Ferruh Yigit
2016-12-15 6:09 ` Jerin Jacob
2016-12-15 6:37 ` Shreyansh Jain
2016-12-15 6:54 ` Jerin Jacob
2016-12-04 18:17 ` [PATCH 18/32] net/dpaa2: introducing dpaa2 pmd driver Hemant Agrawal
2016-12-06 19:49 ` Ferruh Yigit
2016-12-06 21:08 ` Thomas Monjalon
2016-12-07 9:55 ` Hemant Agrawal
2016-12-04 18:17 ` [PATCH 19/32] net/dpaa2: adding eth ops to dpaa2 Hemant Agrawal
2016-12-06 19:49 ` Ferruh Yigit
2016-12-19 15:28 ` Hemant Agrawal
2016-12-04 18:17 ` [PATCH 20/32] net/dpaa2: add queue configuration support Hemant Agrawal
2016-12-06 19:49 ` Ferruh Yigit
2016-12-19 15:30 ` Hemant Agrawal
2016-12-04 18:17 ` [PATCH 21/32] net/dpaa2: add rss flow distribution Hemant Agrawal
2016-12-06 19:50 ` Ferruh Yigit
2016-12-04 18:17 ` [PATCH 22/32] net/dpaa2: configure mac address at init Hemant Agrawal
2016-12-06 19:50 ` Ferruh Yigit
2016-12-19 15:31 ` Hemant Agrawal
2016-12-04 18:17 ` [PATCH 23/32] net/dpaa2: attach the buffer pool to dpni Hemant Agrawal
2016-12-04 18:17 ` [PATCH 24/32] net/dpaa2: add support for l3 and l4 checksum offload Hemant Agrawal
2016-12-04 18:17 ` [PATCH 25/32] net/dpaa2: add support for promiscuous mode Hemant Agrawal
2016-12-04 18:17 ` [PATCH 26/32] net/dpaa2: add mtu config support Hemant Agrawal
2016-12-04 18:17 ` [PATCH 27/32] net/dpaa2: add packet rx and tx support Hemant Agrawal
2016-12-04 18:17 ` [PATCH 28/32] net/dpaa2: add support for physical address usages Hemant Agrawal
2016-12-06 19:50 ` Ferruh Yigit
2016-12-04 18:17 ` [PATCH 29/32] net/dpaa2: rx packet parsing and packet type support Hemant Agrawal
2016-12-04 18:17 ` [PATCH 30/32] net/dpaa2: frame queue based dq storage alloc Hemant Agrawal
2016-12-04 18:17 ` [PATCH 31/32] net/dpaa2: add support for non hw buffer pool packet transmit Hemant Agrawal
2016-12-04 18:17 ` [PATCH 32/32] net/dpaa2: enable stashing for LS2088A devices Hemant Agrawal
2016-12-06 19:50 ` Ferruh Yigit
2016-12-06 19:48 ` [PATCH 00/32] NXP DPAA2 PMD Ferruh Yigit
2016-12-07 9:53 ` Hemant Agrawal
2016-12-19 20:53 ` [PATCHv2 00/34] " Hemant Agrawal
2016-12-19 20:53 ` [PATCHv2 01/34] lib/ether: add rte_device in rte_eth_dev Hemant Agrawal
2016-12-19 16:16 ` Stephen Hemminger
2016-12-20 4:41 ` Shreyansh Jain
2016-12-20 6:12 ` Hemant Agrawal
2016-12-19 20:53 ` [PATCHv2 02/34] mk/dpaa2: add the crc support to the machine type Hemant Agrawal
2016-12-19 20:53 ` [PATCHv2 03/34] doc: add dpaa2 nic details Hemant Agrawal
2016-12-21 18:45 ` Mcnamara, John
2016-12-19 20:53 ` [PATCHv2 04/34] drivers/common/dpaa2: adding qbman driver Hemant Agrawal
2016-12-19 20:53 ` [PATCHv2 05/34] bus/fslmc: introducing fsl-mc bus driver Hemant Agrawal
2016-12-19 20:53 ` [PATCHv2 06/34] bus/fslmc: introduce mc object functions Hemant Agrawal
2016-12-19 20:53 ` [PATCHv2 07/34] bus/fslmc: add mc dpni object support Hemant Agrawal
2016-12-19 20:53 ` [PATCHv2 08/34] bus/fslmc: add mc dpio " Hemant Agrawal
2016-12-19 20:53 ` [PATCHv2 09/34] bus/fslmc: add mc dpbp " Hemant Agrawal
2016-12-19 20:53 ` [PATCHv2 10/34] bus/fslmc: add mc dpseci " Hemant Agrawal
2016-12-19 20:53 ` [PATCHv2 11/34] bus/fslmc: add vfio support Hemant Agrawal
2016-12-19 20:53 ` [PATCHv2 12/34] bus/fslmc: scan for net and sec devices Hemant Agrawal
2016-12-19 20:53 ` [PATCHv2 13/34] net/dpaa2: introducing NXP dpaa2 pmd driver Hemant Agrawal
2016-12-19 20:53 ` [PATCHv2 14/34] bus/fslmc: add debug log message support Hemant Agrawal
2016-12-19 20:53 ` [PATCHv2 15/34] drivers/common/dpaa2: dpio object driver Hemant Agrawal
2016-12-19 20:53 ` [PATCHv2 16/34] drivers/pool/dpaa2: adding hw offloaded mempool Hemant Agrawal
2016-12-19 20:53 ` [PATCHv2 17/34] drivers/common/dpaa2: dpio routine to affine to crypto threads Hemant Agrawal
2016-12-19 20:53 ` [PATCHv2 18/34] net/dpaa2: adding eth ops to dpaa2 Hemant Agrawal
2016-12-19 20:53 ` [PATCHv2 19/34] net/dpaa2: add queue configuration support Hemant Agrawal
2016-12-19 20:53 ` [PATCHv2 20/34] net/dpaa2: add rss flow distribution Hemant Agrawal
2016-12-19 20:54 ` [PATCHv2 21/34] net/dpaa2: configure mac address at init Hemant Agrawal
2016-12-19 20:54 ` [PATCHv2 22/34] net/dpaa2: attach the buffer pool to dpni Hemant Agrawal
2016-12-19 20:54 ` [PATCHv2 23/34] net/dpaa2: add support for l3 and l4 checksum offload Hemant Agrawal
2016-12-19 20:54 ` [PATCHv2 24/34] net/dpaa2: add support for promiscuous mode Hemant Agrawal
2016-12-19 20:54 ` [PATCHv2 25/34] net/dpaa2: add mtu config support Hemant Agrawal
2016-12-19 20:54 ` [PATCHv2 26/34] net/dpaa2: add packet rx and tx support Hemant Agrawal
2016-12-19 20:54 ` [PATCHv2 27/34] net/dpaa2: rx packet parsing and packet type support Hemant Agrawal
2016-12-19 20:54 ` [PATCHv2 28/34] net/dpaa2: link status update Hemant Agrawal
2016-12-19 20:54 ` [PATCHv2 29/34] net/dpaa2: basic stats support Hemant Agrawal
2016-12-19 20:54 ` [PATCHv2 30/34] net/dpaa2: enable stashing for LS2088A devices Hemant Agrawal
2016-12-19 20:54 ` [PATCHv2 31/34] net/dpaa2: add support for non hw buffer pool packet transmit Hemant Agrawal
2016-12-19 20:54 ` [PATCHv2 32/34] net/dpaa2: enabling the use of physical addresses Hemant Agrawal
2016-12-19 20:54 ` [PATCHv2 33/34] bus/fslmc: add support for dmamap to ARM SMMU Hemant Agrawal
2016-12-19 20:54 ` [PATCHv2 34/34] drivers/common/dpaa2: frame queue based dq storage alloc Hemant Agrawal
2016-12-29 5:16 ` [PATCH v3 00/33] NXP DPAA2 PMD Shreyansh Jain
2016-12-29 5:16 ` [PATCH v3 01/33] mk/dpaa2: add the crc support to the machine type Shreyansh Jain
2016-12-29 5:16 ` [PATCH v3 02/33] eal/vfio: adding vfio utility functions in map file Shreyansh Jain
2016-12-29 5:16 ` [PATCH v3 03/33] doc: add dpaa2 nic details Shreyansh Jain
2016-12-29 5:16 ` [PATCH v3 04/33] drivers/common/dpaa2: adding qbman driver Shreyansh Jain
2016-12-29 5:16 ` [PATCH v3 05/33] bus/fslmc: introducing fsl-mc bus driver Shreyansh Jain
2016-12-29 5:16 ` [PATCH v3 06/33] bus/fslmc: introduce mc object functions Shreyansh Jain
2016-12-29 5:16 ` [PATCH v3 07/33] bus/fslmc: add mc dpni object support Shreyansh Jain
2016-12-29 5:16 ` [PATCH v3 08/33] bus/fslmc: add mc dpio " Shreyansh Jain
2016-12-29 5:16 ` [PATCH v3 09/33] bus/fslmc: add mc dpbp " Shreyansh Jain
2016-12-29 5:16 ` [PATCH v3 10/33] bus/fslmc: add mc dpseci " Shreyansh Jain
2016-12-29 5:16 ` [PATCH v3 11/33] bus/fslmc: add vfio support Shreyansh Jain
2016-12-29 5:16 ` [PATCH v3 12/33] bus/fslmc: scan for net and sec devices Shreyansh Jain
2016-12-29 5:16 ` [PATCH v3 13/33] net/dpaa2: introducing NXP dpaa2 pmd driver Shreyansh Jain
2016-12-29 5:16 ` [PATCH v3 14/33] bus/fslmc: add debug log message support Shreyansh Jain
2016-12-29 5:16 ` [PATCH v3 15/33] drivers/common/dpaa2: dpio portal driver Shreyansh Jain
2016-12-29 5:16 ` [PATCH v3 16/33] drivers/pool/dpaa2: adding hw offloaded mempool Shreyansh Jain
2016-12-29 7:08 ` Santosh Shukla
2017-01-03 8:22 ` Hemant Agrawal
2016-12-29 5:16 ` [PATCH v3 17/33] drivers/common/dpaa2: dpio routine to affine to crypto threads Shreyansh Jain
2016-12-29 5:16 ` [PATCH v3 18/33] net/dpaa2: adding eth ops to dpaa2 Shreyansh Jain
2016-12-29 5:16 ` [PATCH v3 19/33] net/dpaa2: add rss flow distribution Shreyansh Jain
2016-12-29 5:16 ` [PATCH v3 20/33] net/dpaa2: configure mac address at init Shreyansh Jain
2016-12-29 5:16 ` [PATCH v3 21/33] net/dpaa2: attach the buffer pool to dpni Shreyansh Jain
2016-12-29 5:16 ` [PATCH v3 22/33] net/dpaa2: add support for l3 and l4 checksum offload Shreyansh Jain
2016-12-29 5:16 ` [PATCH v3 23/33] net/dpaa2: add support for promiscuous mode Shreyansh Jain
2016-12-29 5:16 ` [PATCH v3 24/33] net/dpaa2: add mtu config support Shreyansh Jain
2016-12-29 5:16 ` [PATCH v3 25/33] net/dpaa2: add packet rx and tx support Shreyansh Jain
2016-12-29 5:16 ` [PATCH v3 26/33] net/dpaa2: rx packet parsing and packet type support Shreyansh Jain
2016-12-29 5:16 ` [PATCH v3 27/33] net/dpaa2: link status update Shreyansh Jain
2016-12-29 5:16 ` [PATCH v3 28/33] net/dpaa2: basic stats support Shreyansh Jain
2016-12-29 5:16 ` [PATCH v3 29/33] net/dpaa2: enable stashing for LS2088A devices Shreyansh Jain
2016-12-29 5:16 ` [PATCH v3 30/33] net/dpaa2: add support for non hw buffer pool packet transmit Shreyansh Jain
2016-12-29 5:16 ` [PATCH v3 31/33] net/dpaa2: enabling the use of physical addresses Shreyansh Jain
2016-12-29 5:16 ` [PATCH v3 32/33] bus/fslmc: add support for dmamap to ARM SMMU Shreyansh Jain
2016-12-29 5:16 ` [PATCH v3 33/33] drivers/common/dpaa2: frame queue based dq storage alloc Shreyansh Jain
2017-01-09 17:42 ` [PATCH v3 00/33] NXP DPAA2 PMD Ferruh Yigit
2017-01-10 4:19 ` Shreyansh Jain
2017-01-17 18:52 ` [PATCHv4 " Hemant Agrawal
2017-01-17 18:52 ` [PATCHv4 01/33] mk/dpaa2: add the crc support to the machine type Hemant Agrawal
2017-01-17 18:52 ` [PATCHv4 02/33] doc: add dpaa2 nic details Hemant Agrawal
2017-01-17 18:52 ` [PATCHv4 03/33] drivers/common/dpaa2: adding qbman driver Hemant Agrawal
2017-01-17 18:52 ` [PATCHv4 04/33] bus/fslmc: introducing fsl-mc bus driver Hemant Agrawal
2017-01-17 18:52 ` [PATCHv4 05/33] bus/fslmc: introduce mc object functions Hemant Agrawal
2017-01-17 18:52 ` [PATCHv4 06/33] bus/fslmc: add mc dpni object support Hemant Agrawal
2017-01-17 18:52 ` [PATCHv4 07/33] bus/fslmc: add mc dpio " Hemant Agrawal
2017-01-17 18:52 ` [PATCHv4 08/33] bus/fslmc: add mc dpbp " Hemant Agrawal
2017-01-17 18:52 ` [PATCHv4 09/33] bus/fslmc: add mc dpseci " Hemant Agrawal
2017-01-17 18:52 ` [PATCHv4 10/33] eal/vfio: adding vfio utility functions in map file Hemant Agrawal
2017-01-17 18:52 ` [PATCHv4 11/33] bus/fslmc: add vfio support Hemant Agrawal
2017-01-17 18:52 ` [PATCHv4 12/33] bus/fslmc: scan for net and sec devices Hemant Agrawal
2017-01-17 18:52 ` [PATCHv4 13/33] net/dpaa2: introducing NXP dpaa2 pmd driver Hemant Agrawal
2017-01-17 18:52 ` [PATCHv4 14/33] bus/fslmc: add debug log message support Hemant Agrawal
2017-01-17 18:52 ` [PATCHv4 15/33] drivers/common/dpaa2: dpio portal driver Hemant Agrawal
2017-01-17 18:52 ` [PATCHv4 16/33] drivers/pool/dpaa2: adding hw offloaded mempool Hemant Agrawal
2017-01-17 18:52 ` [PATCHv4 17/33] drivers/common/dpaa2: dpio routine to affine to crypto threads Hemant Agrawal
2017-01-17 18:52 ` [PATCHv4 18/33] net/dpaa2: adding eth ops to dpaa2 Hemant Agrawal
2017-01-17 18:52 ` [PATCHv4 19/33] net/dpaa2: add rss flow distribution Hemant Agrawal
2017-01-17 18:52 ` [PATCHv4 20/33] net/dpaa2: configure mac address at init Hemant Agrawal
2017-01-17 18:52 ` [PATCHv4 21/33] net/dpaa2: attach the buffer pool to dpni Hemant Agrawal
2017-01-17 18:52 ` [PATCHv4 22/33] net/dpaa2: add support for l3 and l4 checksum offload Hemant Agrawal
2017-01-17 18:52 ` [PATCHv4 23/33] net/dpaa2: add support for promiscuous mode Hemant Agrawal
2017-01-17 18:52 ` [PATCHv4 24/33] net/dpaa2: add mtu config support Hemant Agrawal
2017-01-17 18:52 ` [PATCHv4 25/33] net/dpaa2: add packet rx and tx support Hemant Agrawal
2017-01-17 18:52 ` [PATCHv4 26/33] net/dpaa2: rx packet parsing and packet type support Hemant Agrawal
2017-01-17 18:52 ` [PATCHv4 27/33] net/dpaa2: link status update Hemant Agrawal
2017-01-17 18:52 ` [PATCHv4 28/33] net/dpaa2: basic stats support Hemant Agrawal
2017-01-17 18:52 ` [PATCHv4 29/33] net/dpaa2: enable stashing for LS2088A devices Hemant Agrawal
2017-01-17 18:52 ` [PATCHv4 30/33] net/dpaa2: add support for non hw buffer pool packet transmit Hemant Agrawal
2017-01-17 18:52 ` [PATCHv4 31/33] net/dpaa2: enabling the use of physical addresses Hemant Agrawal
2017-01-17 18:52 ` [PATCHv4 32/33] bus/fslmc: add support for dmamap to ARM SMMU Hemant Agrawal
2017-01-17 18:52 ` [PATCHv4 33/33] drivers/common/dpaa2: frame queue based dq storage alloc Hemant Agrawal
2017-01-19 13:23 ` [PATCHv5 00/33] NXP DPAA2 PMD Hemant Agrawal
2017-01-19 13:23 ` [PATCH] cryptodev: decouple from PCI device Hemant Agrawal
2017-01-19 13:27 ` Hemant Agrawal
2017-01-20 12:28 ` De Lara Guarch, Pablo
2017-01-19 13:23 ` [PATCH] mbuf: use pktmbuf helper to create the pool Hemant Agrawal
2017-01-19 13:27 ` Hemant Agrawal
2017-01-19 13:23 ` [PATCHv5 01/33] mk/dpaa2: add the crc support to the machine type Hemant Agrawal
2017-01-19 13:23 ` [PATCHv5 02/33] doc: add dpaa2 nic details Hemant Agrawal
2017-01-19 17:08 ` Thomas Monjalon
2017-01-20 4:47 ` Hemant Agrawal
2017-01-19 17:34 ` Mcnamara, John
2017-01-20 4:46 ` Hemant Agrawal
2017-01-19 13:23 ` [PATCHv5 03/33] drivers/common/dpaa2: adding qbman driver Hemant Agrawal
2017-01-19 19:07 ` Ferruh Yigit
2017-01-20 4:48 ` Hemant Agrawal
2017-01-19 13:23 ` [PATCHv5 04/33] bus/fslmc: introducing fsl-mc bus driver Hemant Agrawal
2017-01-19 17:12 ` Thomas Monjalon
2017-01-19 19:08 ` Ferruh Yigit
2017-01-20 5:05 ` Shreyansh Jain
2017-01-20 11:39 ` Ferruh Yigit
2017-01-19 13:23 ` [PATCHv5 05/33] bus/fslmc: introduce mc object functions Hemant Agrawal
2017-01-19 19:10 ` Ferruh Yigit
2017-01-20 4:52 ` Hemant Agrawal
2017-01-19 13:23 ` [PATCHv5 06/33] bus/fslmc: add mc dpni object support Hemant Agrawal
2017-01-19 17:14 ` Thomas Monjalon
2017-01-20 12:00 ` Hemant Agrawal
2017-01-19 13:23 ` [PATCHv5 07/33] bus/fslmc: add mc dpio " Hemant Agrawal
2017-01-19 13:23 ` [PATCHv5 08/33] bus/fslmc: add mc dpbp " Hemant Agrawal
2017-01-19 13:23 ` [PATCHv5 09/33] bus/fslmc: add mc dpseci " Hemant Agrawal
2017-01-19 13:23 ` [PATCHv5 10/33] eal/vfio: adding vfio utility functions in map file Hemant Agrawal
2017-01-19 17:16 ` Thomas Monjalon
2017-01-19 13:23 ` [PATCHv5 11/33] bus/fslmc: add vfio support Hemant Agrawal
2017-01-19 17:23 ` Thomas Monjalon
2017-01-20 4:58 ` Hemant Agrawal
2017-01-19 19:12 ` Ferruh Yigit
2017-01-19 13:23 ` [PATCHv5 12/33] bus/fslmc: scan for net and sec devices Hemant Agrawal
2017-01-19 13:23 ` [PATCHv5 13/33] net/dpaa2: introducing NXP dpaa2 pmd driver Hemant Agrawal
2017-01-19 19:15 ` Ferruh Yigit
2017-01-20 14:01 ` Shreyansh Jain
2017-01-19 13:23 ` [PATCHv5 14/33] bus/fslmc: add debug log message support Hemant Agrawal
2017-01-19 13:23 ` [PATCHv5 15/33] drivers/common/dpaa2: dpio portal driver Hemant Agrawal
2017-01-19 13:23 ` [PATCHv5 16/33] drivers/pool/dpaa2: adding hw offloaded mempool Hemant Agrawal
2017-01-19 13:23 ` [PATCHv5 17/33] drivers/common/dpaa2: dpio routine to affine to crypto threads Hemant Agrawal
2017-01-19 13:23 ` [PATCHv5 18/33] net/dpaa2: adding eth ops to dpaa2 Hemant Agrawal
2017-01-19 13:23 ` [PATCHv5 19/33] net/dpaa2: add rss flow distribution Hemant Agrawal
2017-01-19 13:23 ` [PATCHv5 20/33] net/dpaa2: configure mac address at init Hemant Agrawal
2017-01-19 13:23 ` [PATCHv5 21/33] net/dpaa2: attach the buffer pool to dpni Hemant Agrawal
2017-01-19 13:23 ` [PATCHv5 22/33] net/dpaa2: add support for l3 and l4 checksum offload Hemant Agrawal
2017-01-19 13:23 ` [PATCHv5 23/33] net/dpaa2: add support for promiscuous mode Hemant Agrawal
2017-01-19 13:23 ` [PATCHv5 24/33] net/dpaa2: add mtu config support Hemant Agrawal
2017-01-19 13:23 ` [PATCHv5 25/33] net/dpaa2: add packet rx and tx support Hemant Agrawal
2017-01-19 13:23 ` [PATCHv5 26/33] net/dpaa2: rx packet parsing and packet type support Hemant Agrawal
2017-01-19 13:23 ` [PATCHv5 27/33] net/dpaa2: link status update Hemant Agrawal
2017-01-19 13:23 ` [PATCHv5 28/33] net/dpaa2: basic stats support Hemant Agrawal
2017-01-19 13:23 ` [PATCHv5 29/33] net/dpaa2: enable stashing for LS2088A devices Hemant Agrawal
2017-01-19 13:23 ` [PATCHv5 30/33] net/dpaa2: add support for non hw buffer pool packet transmit Hemant Agrawal
2017-01-19 13:23 ` [PATCHv5 31/33] net/dpaa2: enabling the use of physical addresses Hemant Agrawal
2017-01-19 13:23 ` [PATCHv5 32/33] bus/fslmc: add support for dmamap to ARM SMMU Hemant Agrawal
2017-01-19 13:24 ` [PATCHv5 33/33] drivers/common/dpaa2: frame queue based dq storage alloc Hemant Agrawal
2017-01-23 11:59 ` [PATCHv6 00/33] NXP DPAA2 PMD Hemant Agrawal
2017-01-23 11:59 ` [PATCHv6 01/33] mk/dpaa2: add the crc support to the machine type Hemant Agrawal
2017-01-23 11:59 ` [PATCHv6 02/33] drivers/common/dpaa2: adding qbman driver Hemant Agrawal
2017-01-23 17:30 ` Ferruh Yigit
2017-01-24 6:28 ` Shreyansh Jain
2017-01-23 11:59 ` [PATCHv6 03/33] bus/fslmc: introducing fsl-mc bus driver Hemant Agrawal
2017-01-23 11:59 ` [PATCHv6 04/33] bus/fslmc: introduce mc object functions Hemant Agrawal
2017-01-23 11:59 ` [PATCHv6 05/33] bus/fslmc: add mc dpni object support Hemant Agrawal
2017-01-23 11:59 ` [PATCHv6 06/33] bus/fslmc: add mc dpio " Hemant Agrawal
2017-01-23 11:59 ` [PATCHv6 07/33] bus/fslmc: add mc dpbp " Hemant Agrawal
2017-01-23 11:59 ` [PATCHv6 08/33] bus/fslmc: add mc dpseci " Hemant Agrawal
2017-01-23 11:59 ` [PATCHv6 09/33] eal/vfio: adding vfio utility functions in map file Hemant Agrawal
2017-01-23 11:59 ` [PATCHv6 10/33] bus/fslmc: add vfio support Hemant Agrawal
2017-01-23 11:59 ` [PATCHv6 11/33] bus/fslmc: scan for net and sec devices Hemant Agrawal
2017-01-23 11:59 ` [PATCHv6 12/33] net/dpaa2: introducing NXP dpaa2 pmd driver Hemant Agrawal
2017-01-23 17:32 ` Ferruh Yigit
2017-01-24 8:38 ` Shreyansh Jain
2017-01-23 11:59 ` [PATCHv6 13/33] doc: add dpaa2 nic details Hemant Agrawal
2017-01-23 11:59 ` [PATCHv6 14/33] bus/fslmc: add debug log message support Hemant Agrawal
2017-01-23 11:59 ` [PATCHv6 15/33] drivers/common/dpaa2: dpio portal driver Hemant Agrawal
2017-01-23 11:59 ` [PATCHv6 16/33] drivers/pool/dpaa2: adding hw offloaded mempool Hemant Agrawal
2017-01-23 17:34 ` Ferruh Yigit
2017-01-24 9:12 ` Shreyansh Jain
2017-01-24 10:49 ` Ferruh Yigit
2017-01-24 14:37 ` Hemant Agrawal
2017-01-24 16:35 ` Ferruh Yigit
2017-01-24 17:28 ` Thomas Monjalon
2017-01-25 12:23 ` Neil Horman
2017-01-25 13:34 ` Shreyansh Jain
2017-01-25 13:47 ` Jerin Jacob
2017-01-25 15:07 ` Neil Horman
2017-01-26 12:05 ` Shreyansh Jain
2017-01-25 15:29 ` Ferruh Yigit
2017-01-25 15:33 ` Ferruh Yigit
2017-01-23 11:59 ` [PATCHv6 17/33] drivers/common/dpaa2: dpio routine to affine to crypto threads Hemant Agrawal
2017-01-23 11:59 ` [PATCHv6 18/33] net/dpaa2: adding eth ops to dpaa2 Hemant Agrawal
2017-01-23 17:35 ` Ferruh Yigit
2017-01-23 11:59 ` [PATCHv6 19/33] net/dpaa2: add rss flow distribution Hemant Agrawal
2017-01-23 11:59 ` [PATCHv6 20/33] net/dpaa2: configure mac address at init Hemant Agrawal
2017-01-23 11:59 ` [PATCHv6 21/33] net/dpaa2: attach the buffer pool to dpni Hemant Agrawal
2017-01-23 11:59 ` [PATCHv6 22/33] net/dpaa2: add support for l3 and l4 checksum offload Hemant Agrawal
2017-01-23 17:35 ` Ferruh Yigit
2017-01-24 10:45 ` Hemant Agrawal
2017-01-24 10:51 ` Ferruh Yigit
2017-01-23 11:59 ` [PATCHv6 23/33] net/dpaa2: add support for promiscuous mode Hemant Agrawal
2017-01-23 11:59 ` [PATCHv6 24/33] net/dpaa2: add mtu config support Hemant Agrawal
2017-01-23 11:59 ` [PATCHv6 25/33] net/dpaa2: add packet rx and tx support Hemant Agrawal
2017-01-23 11:59 ` [PATCHv6 26/33] net/dpaa2: rx packet parsing and packet type support Hemant Agrawal
2017-01-23 11:59 ` [PATCHv6 27/33] net/dpaa2: link status update Hemant Agrawal
2017-01-23 11:59 ` [PATCHv6 28/33] net/dpaa2: basic stats support Hemant Agrawal
2017-01-23 11:59 ` [PATCHv6 29/33] net/dpaa2: enable stashing for LS2088A devices Hemant Agrawal
2017-01-23 12:00 ` [PATCHv6 30/33] net/dpaa2: add support for non hw buffer pool packet transmit Hemant Agrawal
2017-01-23 12:00 ` [PATCHv6 31/33] net/dpaa2: enabling the use of physical addresses Hemant Agrawal
2017-01-23 12:00 ` [PATCHv6 32/33] bus/fslmc: add support for dmamap to ARM SMMU Hemant Agrawal
2017-01-23 12:00 ` [PATCHv6 33/33] drivers/common/dpaa2: frame queue based dq storage alloc Hemant Agrawal
2017-01-23 17:56 ` [PATCHv6 00/33] NXP DPAA2 PMD Ferruh Yigit
2017-01-26 11:55 ` Ferruh Yigit
2017-01-26 12:18 ` Hemant Agrawal
2017-01-26 18:02 ` Thomas Monjalon
2017-01-23 17:58 ` Ferruh Yigit
2017-01-24 11:25 ` Ferruh Yigit
2017-01-25 4:03 ` Hemant Agrawal
2017-02-16 0:38 ` [PATCHv7 00/47] " Hemant Agrawal
2017-02-16 0:39 ` [PATCHv7 01/47] mk/dpaa2: add the crc support to the machine type Hemant Agrawal
2017-02-16 0:39 ` [PATCHv7 02/47] mk: handle intra drivers dependencies for shared build Hemant Agrawal
2017-02-16 0:39 ` [PATCHv7 03/47] common/dpaa2: adding qbman driver Hemant Agrawal
2017-02-16 5:57 ` Shreyansh Jain
2017-02-21 13:42 ` Hello Ferruh, Neil, Shreyansh Jain
2017-02-21 13:45 ` [PATCHv7 03/47] common/dpaa2: adding qbman driver Shreyansh Jain
2017-02-21 14:39 ` Hello Ferruh, Neil, Ferruh Yigit
2017-02-22 8:23 ` [PATCHv7 03/47] common/dpaa2: adding qbman driver Shreyansh Jain
2017-02-24 9:58 ` Ferruh Yigit
2017-02-27 10:01 ` Shreyansh Jain
2017-02-27 15:35 ` Ferruh Yigit
2017-02-28 5:27 ` Shreyansh Jain
2017-03-01 11:00 ` Thomas Monjalon
2017-03-01 12:26 ` Hemant Agrawal
2017-02-22 12:41 ` Hello Ferruh, Neil, Neil Horman
2017-02-16 0:39 ` [PATCHv7 04/47] bus/fslmc: introducing fsl-mc bus driver Hemant Agrawal
2017-02-16 0:39 ` [PATCHv7 05/47] bus/fslmc: introduce MC object functions Hemant Agrawal
2017-02-16 0:39 ` [PATCHv7 06/47] bus/fslmc: add mc dpni object support Hemant Agrawal
2017-02-16 0:39 ` [PATCHv7 07/47] bus/fslmc: add mc dpio " Hemant Agrawal
2017-02-16 0:39 ` [PATCHv7 08/47] bus/fslmc: add mc dpbp " Hemant Agrawal
2017-02-16 0:39 ` [PATCHv7 09/47] bus/fslmc: add mc dpseci " Hemant Agrawal
2017-02-16 0:39 ` [PATCHv7 10/47] eal/vfio: adding vfio utility functions in map file Hemant Agrawal
2017-02-16 0:39 ` [PATCHv7 11/47] bus/fslmc: add vfio support Hemant Agrawal
2017-02-16 0:39 ` [PATCHv7 12/47] bus/fslmc: scan for net and sec devices Hemant Agrawal
2017-02-16 0:39 ` [PATCHv7 13/47] net/dpaa2: introducing NXP DPAA2 PMD driver Hemant Agrawal
2017-02-16 0:39 ` [PATCHv7 14/47] doc: add DPAA2 NIC details Hemant Agrawal
2017-02-16 0:39 ` [PATCHv7 15/47] bus/fslmc: add debug log support Hemant Agrawal
2017-02-16 0:39 ` [PATCHv7 16/47] net/dpaa2: " Hemant Agrawal
2017-02-16 0:39 ` [PATCHv7 17/47] common/dpaa2: " Hemant Agrawal
2017-02-16 0:39 ` [PATCHv7 18/47] config: enable support for DPAA2 debug logging Hemant Agrawal
2017-02-16 0:39 ` [PATCHv7 19/47] bus/fslmc: dpio portal driver Hemant Agrawal
2017-02-16 0:39 ` [PATCHv7 20/47] pool/dpaa2: add DPAA2 hardware offloaded mempool Hemant Agrawal
2017-02-16 0:39 ` [PATCHv7 21/47] bus/fslmc: affine dpio to crypto threads Hemant Agrawal
2017-02-16 0:39 ` [PATCHv7 22/47] bus/fslmc: define queues for DPAA2 devices Hemant Agrawal
2017-02-16 0:39 ` [PATCHv7 23/47] net/dpaa2: adding eth ops to dpaa2 Hemant Agrawal
2017-02-16 0:39 ` [PATCHv7 24/47] net/dpaa2: add RSS flow distribution Hemant Agrawal
2017-02-16 0:39 ` [PATCHv7 25/47] net/dpaa2: configure MAC address at init Hemant Agrawal
2017-02-16 0:39 ` [PATCHv7 26/47] bus/fslmc: define hardware annotation area size Hemant Agrawal
2017-02-16 0:39 ` [PATCHv7 27/47] net/dpaa2: attach the buffer pool to dpni Hemant Agrawal
2017-02-16 0:39 ` [PATCHv7 28/47] bus/fslmc: introduce true and false macros Hemant Agrawal
2017-02-16 0:39 ` [PATCHv7 29/47] net/dpaa2: add support for L3 and L4 checksum offload Hemant Agrawal
2017-02-16 0:39 ` [PATCHv7 30/47] net/dpaa2: add support for promiscuous mode Hemant Agrawal
2017-02-16 0:39 ` [PATCHv7 31/47] bus/fslmc: define VLAN header length Hemant Agrawal
2017-02-16 0:39 ` [PATCHv7 32/47] net/dpaa2: add MTU configuration support Hemant Agrawal
2017-02-16 0:39 ` [PATCHv7 33/47] bus/fslmc: add packet FLE definitions Hemant Agrawal
2017-02-16 0:39 ` [PATCHv7 34/47] net/dpaa2: enable packet Rx and Tx operations Hemant Agrawal
2017-02-16 0:39 ` [PATCHv7 35/47] net/dpaa2: support for Rx packet parsing and packet type Hemant Agrawal
2017-02-16 0:39 ` [PATCHv7 36/47] net/dpaa2: link status update Hemant Agrawal
2017-02-16 0:39 ` [PATCHv7 37/47] net/dpaa2: basic stats support Hemant Agrawal
2017-02-16 0:39 ` [PATCHv7 38/47] net/dpaa2: enable stashing for LS2088A devices Hemant Agrawal
2017-02-16 0:39 ` [PATCHv7 39/47] net/dpaa2: handle non-hardware backed buffer pool Hemant Agrawal
2017-02-16 0:39 ` [PATCHv7 40/47] bus/fslmc: add physical-virtual address translation helpers Hemant Agrawal
2017-02-16 0:39 ` [PATCHv7 41/47] pool/dpaa2: enable physical addressing for pool buffers Hemant Agrawal
2017-02-16 0:39 ` [PATCHv7 42/47] net/dpaa2: enable physical addressing for packet buffers Hemant Agrawal
2017-02-16 0:39 ` [PATCHv7 43/47] config: add configuration for toggling physical addressing Hemant Agrawal
2017-02-16 0:39 ` [PATCHv7 44/47] bus/fslmc: add support for DMA mapping for ARM SMMU Hemant Agrawal
2017-02-16 0:39 ` [PATCHv7 45/47] net/dpaa2: enable DMA Mapping during device scanning Hemant Agrawal
2017-02-16 0:39 ` [PATCHv7 46/47] bus/fslmc: frame queue based dq storage alloc Hemant Agrawal
2017-02-16 0:39 ` [PATCHv7 47/47] net/dpaa2: enable frame queue based dequeuing Hemant Agrawal
2017-02-16 13:22 ` [PATCHv7 00/47] NXP DPAA2 PMD Neil Horman
2017-02-16 13:27 ` Bruce Richardson
2017-02-17 11:34 ` Ferruh Yigit
2017-02-17 12:13 ` Bruce Richardson
2017-02-17 12:17 ` Vincent JARDIN
2017-02-17 22:48 ` Neil Horman
2017-02-17 13:40 ` Thomas Monjalon
2017-02-17 12:29 ` Hemant Agrawal
2017-02-19 14:44 ` Neil Horman
2017-02-20 5:31 ` Hemant Agrawal
2017-02-20 12:20 ` Neil Horman
2017-03-03 12:46 ` [PATCHv8 00/46] " Hemant Agrawal
2017-03-03 12:46 ` [PATCHv8 01/46] mk/dpaa2: add the crc support to the machine type Hemant Agrawal
2017-03-03 12:46 ` [PATCHv8 02/46] mk: handle intra drivers dependencies for shared build Hemant Agrawal
2017-03-03 12:46 ` [PATCHv8 03/46] bus/fslmc: introducing fsl-mc bus driver Hemant Agrawal
2017-03-03 12:46 ` [PATCHv8 04/46] bus/fslmc: add QBMAN driver to bus Hemant Agrawal
2017-03-03 12:46 ` [PATCHv8 05/46] bus/fslmc: introduce MC object functions Hemant Agrawal
2017-03-03 12:46 ` [PATCHv8 06/46] bus/fslmc: add mc dpio object support Hemant Agrawal
2017-03-03 12:46 ` [PATCHv8 07/46] bus/fslmc: add mc dpbp " Hemant Agrawal
2017-03-03 12:46 ` [PATCHv8 08/46] eal/vfio: adding vfio utility functions in map file Hemant Agrawal
2017-03-03 12:46 ` [PATCHv8 09/46] bus/fslmc: add vfio support Hemant Agrawal
2017-03-03 12:46 ` [PATCHv8 10/46] bus/fslmc: scan for net and sec device Hemant Agrawal
2017-03-03 12:46 ` [PATCHv8 11/46] net/dpaa2: introducing NXP DPAA2 PMD driver Hemant Agrawal
2017-03-03 12:46 ` [PATCHv8 12/46] doc: add DPAA2 NIC details Hemant Agrawal
2017-03-03 12:46 ` [PATCHv8 13/46] bus/fslmc: add debug log support Hemant Agrawal
2017-03-03 12:46 ` [PATCHv8 14/46] net/dpaa2: " Hemant Agrawal
2017-03-03 12:46 ` [PATCHv8 15/46] config: enable support for DPAA2 debug logging Hemant Agrawal
2017-03-03 12:46 ` [PATCHv8 16/46] net/dpaa2: add mc dpni object support Hemant Agrawal
2017-03-03 12:46 ` [PATCHv8 17/46] bus/fslmc: dpio portal driver Hemant Agrawal
2017-03-03 12:46 ` [PATCHv8 18/46] bus/fslmc: introduce support for hw mempool object Hemant Agrawal
2017-03-03 12:46 ` [PATCHv8 19/46] pool/dpaa2: add DPAA2 hardware offloaded mempool Hemant Agrawal
2017-03-07 16:24 ` Ferruh Yigit
2017-03-08 9:05 ` Olivier MATZ
2017-03-08 12:52 ` Hemant Agrawal
2017-03-08 15:39 ` Thomas Monjalon
2017-03-09 5:57 ` Hemant Agrawal
2017-03-14 6:42 ` Hemant Agrawal
2017-03-14 8:14 ` Olivier Matz
2017-03-03 12:46 ` [PATCHv8 20/46] bus/fslmc: affine dpio to crypto threads Hemant Agrawal
2017-03-03 12:46 ` [PATCHv8 21/46] bus/fslmc: define queues for DPAA2 devices Hemant Agrawal
2017-03-03 12:46 ` [PATCHv8 22/46] net/dpaa2: adding eth ops to dpaa2 Hemant Agrawal
2017-03-03 12:46 ` [PATCHv8 23/46] net/dpaa2: add RSS flow distribution Hemant Agrawal
2017-03-03 12:46 ` [PATCHv8 24/46] net/dpaa2: configure MAC address at init Hemant Agrawal
2017-03-03 12:46 ` [PATCHv8 25/46] bus/fslmc: define hardware annotation area size Hemant Agrawal
2017-03-03 12:46 ` [PATCHv8 26/46] net/dpaa2: attach the buffer pool to dpni Hemant Agrawal
2017-03-03 12:46 ` [PATCHv8 27/46] bus/fslmc: introduce true and false macros Hemant Agrawal
2017-03-03 12:46 ` [PATCHv8 28/46] net/dpaa2: add support for L3 and L4 checksum offload Hemant Agrawal
2017-03-03 12:46 ` [PATCHv8 29/46] net/dpaa2: add support for promiscuous mode Hemant Agrawal
2017-03-03 12:46 ` [PATCHv8 30/46] bus/fslmc: define VLAN header length Hemant Agrawal
2017-03-03 12:46 ` [PATCHv8 31/46] net/dpaa2: add MTU configuration support Hemant Agrawal
2017-03-03 12:46 ` [PATCHv8 32/46] bus/fslmc: add packet FLE definitions Hemant Agrawal
2017-03-03 12:46 ` [PATCHv8 33/46] net/dpaa2: enable packet Rx and Tx operations Hemant Agrawal
2017-03-03 12:46 ` [PATCHv8 34/46] net/dpaa2: support for Rx packet parsing and packet type Hemant Agrawal
2017-03-03 12:46 ` [PATCHv8 35/46] net/dpaa2: link status update Hemant Agrawal
2017-03-03 12:46 ` [PATCHv8 36/46] net/dpaa2: basic stats support Hemant Agrawal
2017-03-03 12:46 ` [PATCHv8 37/46] net/dpaa2: enable stashing for LS2088A devices Hemant Agrawal
2017-03-03 12:46 ` [PATCHv8 38/46] net/dpaa2: handle non-hardware backed buffer pool Hemant Agrawal
2017-03-03 12:46 ` [PATCHv8 39/46] bus/fslmc: add physical-virtual address translation helpers Hemant Agrawal
2017-03-03 12:46 ` [PATCHv8 40/46] pool/dpaa2: enable physical addressing for pool buffers Hemant Agrawal
2017-03-03 12:46 ` [PATCHv8 41/46] net/dpaa2: enable physical addressing for packet buffers Hemant Agrawal
2017-03-03 12:46 ` [PATCHv8 42/46] config: add configuration for toggling physical addressing Hemant Agrawal
2017-03-03 12:47 ` [PATCHv8 43/46] bus/fslmc: add support for DMA mapping for ARM SMMU Hemant Agrawal
2017-03-03 12:47 ` [PATCHv8 44/46] net/dpaa2: enable DMA Mapping during device scanning Hemant Agrawal
2017-03-03 12:47 ` [PATCHv8 45/46] bus/fslmc: frame queue based dq storage alloc Hemant Agrawal
2017-03-03 12:47 ` [PATCHv8 46/46] net/dpaa2: enable frame queue based dequeuing Hemant Agrawal
2017-03-07 16:13 ` [PATCHv8 00/46] NXP DPAA2 PMD Thomas Monjalon
2017-03-07 17:00 ` Ferruh Yigit
2017-03-08 12:30 ` Shreyansh Jain
2017-03-17 13:08 ` [PATCH v9 00/22] " Hemant Agrawal
2017-03-17 13:08 ` [PATCH v9 01/22] net/dpaa2: introducing NXP DPAA2 PMD driver Hemant Agrawal
2017-03-17 13:08 ` [PATCH v9 02/22] doc: add DPAA2 NIC details Hemant Agrawal
2017-03-24 15:35 ` Ferruh Yigit
2017-03-17 13:08 ` [PATCH v9 03/22] net/dpaa2: add debug log support Hemant Agrawal
2017-03-17 13:08 ` [PATCH v9 04/22] config: enable support for DPAA2 debug logging Hemant Agrawal
2017-03-17 13:08 ` [PATCH v9 05/22] net/dpaa2: add mc dpni object support Hemant Agrawal
2017-03-17 13:08 ` [PATCH v9 06/22] net/dpaa2: adding eth ops to dpaa2 Hemant Agrawal
2017-03-17 13:08 ` [PATCH v9 07/22] net/dpaa2: add RSS flow distribution Hemant Agrawal
2017-03-17 13:08 ` [PATCH v9 08/22] net/dpaa2: configure MAC address at init Hemant Agrawal
2017-03-17 13:08 ` [PATCH v9 09/22] net/dpaa2: attach the buffer pool to dpni Hemant Agrawal
2017-03-17 13:08 ` [PATCH v9 10/22] net/dpaa2: add support for L3 and L4 checksum offload Hemant Agrawal
2017-03-17 13:08 ` [PATCH v9 11/22] net/dpaa2: add support for promiscuous mode Hemant Agrawal
2017-03-17 13:08 ` [PATCH v9 12/22] net/dpaa2: add MTU configuration support Hemant Agrawal
2017-03-17 13:08 ` [PATCH v9 13/22] net/dpaa2: enable packet Rx and Tx operations Hemant Agrawal
2017-03-17 13:08 ` [PATCH v9 14/22] net/dpaa2: support for Rx packet parsing and packet type Hemant Agrawal
2017-03-17 13:08 ` [PATCH v9 15/22] net/dpaa2: link status update Hemant Agrawal
2017-03-17 13:08 ` [PATCH v9 16/22] net/dpaa2: basic stats support Hemant Agrawal
2017-03-17 13:08 ` [PATCH v9 17/22] net/dpaa2: enable stashing for LS2088A devices Hemant Agrawal
2017-03-17 13:08 ` [PATCH v9 18/22] net/dpaa2: handle non-hardware backed buffer pool Hemant Agrawal
2017-03-17 13:08 ` [PATCH v9 19/22] net/dpaa2: enable physical addressing for packet buffers Hemant Agrawal
2017-03-17 13:08 ` [PATCH v9 20/22] config: add configuration for toggling physical addressing Hemant Agrawal
2017-03-17 13:08 ` [PATCH v9 21/22] net/dpaa2: enable DMA Mapping during device scanning Hemant Agrawal
2017-03-17 13:08 ` [PATCH v9 22/22] net/dpaa2: enable frame queue based dequeuing Hemant Agrawal
2017-03-23 14:34 ` [PATCH v9 00/22] NXP DPAA2 PMD Ferruh Yigit
2017-03-23 16:59 ` Hemant Agrawal
2017-03-24 13:35 ` [PATCH v10 " Hemant Agrawal
2017-03-24 13:35 ` [PATCH v10 01/22] net/dpaa2: introducing NXP DPAA2 PMD driver Hemant Agrawal
2017-03-24 13:35 ` [PATCH v10 02/22] doc: add DPAA2 NIC details Hemant Agrawal
2017-03-24 13:35 ` [PATCH v10 03/22] net/dpaa2: add debug log support Hemant Agrawal
2017-03-24 13:35 ` [PATCH v10 04/22] config: enable support for DPAA2 debug logging Hemant Agrawal
2017-03-24 13:35 ` [PATCH v10 05/22] net/dpaa2: add mc dpni object support Hemant Agrawal
2017-03-24 13:35 ` [PATCH v10 06/22] net/dpaa2: adding eth ops to dpaa2 Hemant Agrawal
2017-03-24 13:35 ` [PATCH v10 07/22] net/dpaa2: add RSS flow distribution Hemant Agrawal
2017-03-24 13:35 ` [PATCH v10 08/22] net/dpaa2: configure MAC address at init Hemant Agrawal
2017-03-24 13:35 ` [PATCH v10 09/22] net/dpaa2: attach the buffer pool to dpni Hemant Agrawal
2017-03-24 13:35 ` [PATCH v10 10/22] net/dpaa2: add support for L3 and L4 checksum offload Hemant Agrawal
2017-03-24 13:35 ` [PATCH v10 11/22] net/dpaa2: add support for promiscuous mode Hemant Agrawal
2017-03-24 13:35 ` [PATCH v10 12/22] net/dpaa2: add MTU configuration support Hemant Agrawal
2017-03-24 13:35 ` [PATCH v10 13/22] net/dpaa2: enable packet Rx and Tx operations Hemant Agrawal
2017-03-24 13:35 ` [PATCH v10 14/22] net/dpaa2: support for Rx packet parsing and packet type Hemant Agrawal
2017-03-24 13:35 ` [PATCH v10 15/22] net/dpaa2: link status update Hemant Agrawal
2017-03-24 13:35 ` [PATCH v10 16/22] net/dpaa2: basic stats support Hemant Agrawal
2017-03-24 13:35 ` [PATCH v10 17/22] net/dpaa2: enable stashing for LS2088A devices Hemant Agrawal
2017-03-24 13:35 ` [PATCH v10 18/22] net/dpaa2: handle non-hardware backed buffer pool Hemant Agrawal
2017-03-24 13:35 ` [PATCH v10 19/22] net/dpaa2: enable physical addressing for packet buffers Hemant Agrawal
2017-03-24 13:35 ` [PATCH v10 20/22] config: add configuration for toggling physical addressing Hemant Agrawal
2017-03-24 13:35 ` [PATCH v10 21/22] net/dpaa2: enable DMA Mapping during device scanning Hemant Agrawal
2017-03-24 13:35 ` [PATCH v10 22/22] net/dpaa2: enable frame queue based dequeuing Hemant Agrawal
2017-03-24 14:58 ` [PATCH v10 00/22] NXP DPAA2 PMD Ferruh Yigit
2017-03-24 15:19 ` Shreyansh Jain
2017-04-09 8:11 ` [PATCH v11 " Hemant Agrawal
2017-04-09 8:11 ` [PATCH v11 01/22] net/dpaa2: introducing NXP DPAA2 PMD driver Hemant Agrawal
2017-04-09 8:11 ` [PATCH v11 02/22] doc: add DPAA2 NIC details Hemant Agrawal
2017-04-09 12:23 ` Shreyansh Jain
2017-04-10 4:54 ` [PATCH] doc: fix build error in DPAA2 PMD guide Shreyansh Jain
2017-04-10 7:46 ` Mcnamara, John
2017-04-11 14:58 ` Ferruh Yigit
2017-04-11 17:13 ` Shreyansh Jain
2017-04-09 8:11 ` [PATCH v11 03/22] net/dpaa2: add debug log support Hemant Agrawal
2017-04-09 8:11 ` [PATCH v11 04/22] config: enable support for DPAA2 debug logging Hemant Agrawal
2017-04-09 8:11 ` [PATCH v11 05/22] net/dpaa2: add mc dpni object support Hemant Agrawal
2017-04-09 8:11 ` [PATCH v11 06/22] net/dpaa2: adding eth ops to dpaa2 Hemant Agrawal
2017-04-09 8:11 ` [PATCH v11 07/22] net/dpaa2: add RSS flow distribution Hemant Agrawal
2017-04-09 8:11 ` [PATCH v11 08/22] net/dpaa2: configure MAC address at init Hemant Agrawal
2017-04-09 8:11 ` [PATCH v11 09/22] net/dpaa2: attach the buffer pool to dpni Hemant Agrawal
2017-04-09 8:11 ` [PATCH v11 10/22] net/dpaa2: add support for L3 and L4 checksum offload Hemant Agrawal
2017-04-09 8:11 ` [PATCH v11 11/22] net/dpaa2: add support for promiscuous mode Hemant Agrawal
2017-04-09 8:11 ` [PATCH v11 12/22] net/dpaa2: add MTU configuration support Hemant Agrawal
2017-04-09 8:11 ` [PATCH v11 13/22] net/dpaa2: enable packet Rx and Tx operations Hemant Agrawal
2017-04-09 8:11 ` [PATCH v11 14/22] net/dpaa2: support for Rx packet parsing and packet type Hemant Agrawal
2017-04-09 8:11 ` [PATCH v11 15/22] net/dpaa2: link status update Hemant Agrawal
2017-04-09 8:11 ` [PATCH v11 16/22] net/dpaa2: basic stats support Hemant Agrawal
2017-04-09 8:11 ` [PATCH v11 17/22] net/dpaa2: enable stashing for LS2088A devices Hemant Agrawal
2017-04-09 8:11 ` [PATCH v11 18/22] net/dpaa2: handle non-hardware backed buffer pool Hemant Agrawal
2017-04-09 8:11 ` [PATCH v11 19/22] net/dpaa2: enable physical addressing for packet buffers Hemant Agrawal
2017-04-09 8:11 ` [PATCH v11 20/22] config: add configuration for toggling physical addressing Hemant Agrawal
2017-04-09 8:11 ` [PATCH v11 21/22] net/dpaa2: enable DMA Mapping during device scanning Hemant Agrawal
2017-04-09 8:11 ` [PATCH v11 22/22] net/dpaa2: enable frame queue based dequeuing Hemant Agrawal
2017-04-11 13:49 ` [PATCH v12 00/22] NXP DPAA2 PMD Hemant Agrawal
2017-04-11 13:49 ` [PATCH v12 01/22] net/dpaa2: introducing NXP DPAA2 PMD driver Hemant Agrawal
2017-04-11 13:49 ` [PATCH v12 02/22] doc: add DPAA2 NIC details Hemant Agrawal
2017-04-12 15:28 ` Ferruh Yigit
2017-04-13 9:22 ` Shreyansh Jain
2017-04-13 9:18 ` Ferruh Yigit
2017-04-14 12:08 ` Ferruh Yigit
2017-04-14 16:50 ` Shreyansh Jain
2017-04-11 13:49 ` [PATCH v12 03/22] net/dpaa2: add debug log support Hemant Agrawal
2017-04-11 13:49 ` [PATCH v12 04/22] config: enable support for DPAA2 debug logging Hemant Agrawal
2017-04-11 13:49 ` [PATCH v12 05/22] net/dpaa2: add mc dpni object support Hemant Agrawal
2017-04-11 13:49 ` [PATCH v12 06/22] net/dpaa2: adding eth ops to dpaa2 Hemant Agrawal
2017-04-11 13:49 ` [PATCH v12 07/22] net/dpaa2: add RSS flow distribution Hemant Agrawal
2017-04-11 13:49 ` [PATCH v12 08/22] net/dpaa2: configure MAC address at init Hemant Agrawal
2017-04-11 13:49 ` [PATCH v12 09/22] net/dpaa2: attach the buffer pool to dpni Hemant Agrawal
2017-04-11 13:49 ` [PATCH v12 10/22] net/dpaa2: add support for L3 and L4 checksum offload Hemant Agrawal
2017-04-11 13:49 ` [PATCH v12 11/22] net/dpaa2: add support for promiscuous mode Hemant Agrawal
2017-04-11 13:49 ` [PATCH v12 12/22] net/dpaa2: add MTU configuration support Hemant Agrawal
2017-04-11 13:49 ` [PATCH v12 13/22] net/dpaa2: enable packet Rx and Tx operations Hemant Agrawal
2017-04-11 13:49 ` [PATCH v12 14/22] net/dpaa2: support for Rx packet parsing and packet type Hemant Agrawal
2017-04-11 13:49 ` [PATCH v12 15/22] net/dpaa2: link status update Hemant Agrawal
2017-04-11 13:49 ` [PATCH v12 16/22] net/dpaa2: basic stats support Hemant Agrawal
2017-04-11 13:49 ` [PATCH v12 17/22] net/dpaa2: enable stashing for LS2088A devices Hemant Agrawal
2017-04-11 13:49 ` [PATCH v12 18/22] net/dpaa2: handle non-hardware backed buffer pool Hemant Agrawal
2017-04-11 13:49 ` [PATCH v12 19/22] net/dpaa2: enable physical addressing for packet buffers Hemant Agrawal
2017-04-11 13:49 ` [PATCH v12 20/22] config: add configuration for toggling physical addressing Hemant Agrawal
2017-04-11 13:49 ` [PATCH v12 21/22] net/dpaa2: enable DMA Mapping during device scanning Hemant Agrawal
2017-04-11 13:49 ` [PATCH v12 22/22] net/dpaa2: enable frame queue based dequeuing Hemant Agrawal
2017-04-12 13:52 ` [PATCH v12 00/22] NXP DPAA2 PMD Ferruh Yigit
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