From: York Sun <york.sun@nxp.com>
To: u-boot@lists.denx.de
Subject: [U-Boot] [PATCH 04/24] crypto: Move SYS_FSL_SEC_COMPAT into driver Kconfig
Date: Wed, 28 Dec 2016 08:43:30 -0800 [thread overview]
Message-ID: <1482943430-10231-5-git-send-email-york.sun@nxp.com> (raw)
In-Reply-To: <1482943430-10231-1-git-send-email-york.sun@nxp.com>
Instead of define CONFIG_SYS_FSL_SEC_COMPAT in header files for PowerPC
and ARM SoCs, move it to Kconfig under the driver.
Signed-off-by: York Sun <york.sun@nxp.com>
---
arch/arm/Kconfig | 4 ++
arch/arm/cpu/armv7/ls102xa/Kconfig | 2 +
arch/arm/cpu/armv8/fsl-layerscape/Kconfig | 4 ++
arch/arm/include/asm/arch-fsl-layerscape/config.h | 2 -
arch/arm/include/asm/arch-ls102xa/config.h | 1 -
arch/powerpc/Kconfig | 2 +
arch/powerpc/cpu/mpc85xx/Kconfig | 70 +++++++++++++++++++++++
arch/powerpc/include/asm/config.h | 1 -
arch/powerpc/include/asm/config_mpc85xx.h | 30 ----------
drivers/crypto/fsl/Kconfig | 33 +++++++++++
include/configs/mx6_common.h | 1 -
include/configs/mx7_common.h | 1 -
scripts/config_whitelist.txt | 1 -
13 files changed, 115 insertions(+), 37 deletions(-)
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 587f288..ff601ea 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -464,10 +464,14 @@ config ARCH_MESON
config ARCH_MX7
bool "Freescale MX7"
select CPU_V7
+ select SYS_FSL_HAS_SEC if SECURE_BOOT
+ select SYS_FSL_SEC_COMPAT_4
config ARCH_MX6
bool "Freescale MX6"
select CPU_V7
+ select SYS_FSL_HAS_SEC if SECURE_BOOT
+ select SYS_FSL_SEC_COMPAT_4
config ARCH_MX5
bool "Freescale MX5"
diff --git a/arch/arm/cpu/armv7/ls102xa/Kconfig b/arch/arm/cpu/armv7/ls102xa/Kconfig
index f94568a..e233aa4 100644
--- a/arch/arm/cpu/armv7/ls102xa/Kconfig
+++ b/arch/arm/cpu/armv7/ls102xa/Kconfig
@@ -5,6 +5,8 @@ config ARCH_LS1021A
select SYS_HAS_SERDES
select SYS_FSL_DDR_BE
select SYS_FSL_DDR_VER_50
+ select SYS_FSL_HAS_SEC
+ select SYS_FSL_SEC_COMPAT_5
menu "LS102xA architecture"
depends on ARCH_LS1021A
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
index cc0dc88..17b470d 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
+++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
@@ -29,10 +29,14 @@ config ARCH_LS2080A
select SYS_FSL_DDR_LE
select SYS_FSL_DDR_VER_50
select SYS_FSL_HAS_DP_DDR
+ select SYS_FSL_HAS_SEC
+ select SYS_FSL_SEC_COMPAT_5
select SYS_FSL_SRDS_2
config FSL_LSCH2
bool
+ select SYS_FSL_HAS_SEC
+ select SYS_FSL_SEC_COMPAT_5
select SYS_FSL_SRDS_1
select SYS_HAS_SERDES
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h b/arch/arm/include/asm/arch-fsl-layerscape/config.h
index c50894a..f4f9eaa 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/config.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h
@@ -57,7 +57,6 @@
/* SEC */
#define CONFIG_SYS_FSL_SEC_LE
-#define CONFIG_SYS_FSL_SEC_COMPAT 5
/* Security Monitor */
#define CONFIG_SYS_FSL_SEC_MON_LE
@@ -135,7 +134,6 @@
#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1
#elif defined(CONFIG_FSL_LSCH2)
-#define CONFIG_SYS_FSL_SEC_COMPAT 5
#define CONFIG_SYS_FSL_OCRAM_BASE 0x10000000 /* initial RAM */
#define CONFIG_SYS_FSL_OCRAM_SIZE 0x00200000 /* 2M */
diff --git a/arch/arm/include/asm/arch-ls102xa/config.h b/arch/arm/include/asm/arch-ls102xa/config.h
index ec65cc0..97c69e9 100644
--- a/arch/arm/include/asm/arch-ls102xa/config.h
+++ b/arch/arm/include/asm/arch-ls102xa/config.h
@@ -114,7 +114,6 @@
#define DCU_LAYER_MAX_NUM 16
#ifdef CONFIG_LS102XA
-#define CONFIG_SYS_FSL_SEC_COMPAT 5
#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
#define CONFIG_SYS_FSL_ERRATUM_A008378
#define CONFIG_SYS_FSL_ERRATUM_A009663
diff --git a/arch/powerpc/Kconfig b/arch/powerpc/Kconfig
index 18451d3..9fc1d5c 100644
--- a/arch/powerpc/Kconfig
+++ b/arch/powerpc/Kconfig
@@ -23,6 +23,8 @@ config MPC8260
config MPC83xx
bool "MPC83xx"
select CREATE_ARCH_SYMLINK
+ select SYS_FSL_HAS_SEC
+ select SYS_FSL_SEC_COMPAT_2
config MPC85xx
bool "MPC85xx"
diff --git a/arch/powerpc/cpu/mpc85xx/Kconfig b/arch/powerpc/cpu/mpc85xx/Kconfig
index 7f04a09..1287ab6 100644
--- a/arch/powerpc/cpu/mpc85xx/Kconfig
+++ b/arch/powerpc/cpu/mpc85xx/Kconfig
@@ -325,29 +325,41 @@ config ARCH_B4420
bool
select E500MC
select FSL_LAW
+ select SYS_FSL_HAS_SEC
+ select SYS_FSL_SEC_COMPAT_4
config ARCH_B4860
bool
select E500MC
select FSL_LAW
+ select SYS_FSL_HAS_SEC
+ select SYS_FSL_SEC_COMPAT_4
config ARCH_BSC9131
bool
select FSL_LAW
+ select SYS_FSL_HAS_SEC
+ select SYS_FSL_SEC_COMPAT_4
config ARCH_BSC9132
bool
select FSL_LAW
+ select SYS_FSL_HAS_SEC
+ select SYS_FSL_SEC_COMPAT_4
select SYS_PPC_E500_USE_DEBUG_TLB
config ARCH_C29X
bool
select FSL_LAW
+ select SYS_FSL_HAS_SEC
+ select SYS_FSL_SEC_COMPAT_6
select SYS_PPC_E500_USE_DEBUG_TLB
config ARCH_MPC8536
bool
select FSL_LAW
+ select SYS_FSL_HAS_SEC
+ select SYS_FSL_SEC_COMPAT_2
select SYS_PPC_E500_USE_DEBUG_TLB
config ARCH_MPC8540
@@ -357,20 +369,28 @@ config ARCH_MPC8540
config ARCH_MPC8541
bool
select FSL_LAW
+ select SYS_FSL_HAS_SEC
+ select SYS_FSL_SEC_COMPAT_2
config ARCH_MPC8544
bool
select FSL_LAW
+ select SYS_FSL_HAS_SEC
+ select SYS_FSL_SEC_COMPAT_2
select SYS_PPC_E500_USE_DEBUG_TLB
config ARCH_MPC8548
bool
select FSL_LAW
+ select SYS_FSL_HAS_SEC
+ select SYS_FSL_SEC_COMPAT_2
select SYS_PPC_E500_USE_DEBUG_TLB
config ARCH_MPC8555
bool
select FSL_LAW
+ select SYS_FSL_HAS_SEC
+ select SYS_FSL_SEC_COMPAT_2
config ARCH_MPC8560
bool
@@ -379,83 +399,117 @@ config ARCH_MPC8560
config ARCH_MPC8568
bool
select FSL_LAW
+ select SYS_FSL_HAS_SEC
+ select SYS_FSL_SEC_COMPAT_2
config ARCH_MPC8569
bool
select FSL_LAW
+ select SYS_FSL_HAS_SEC
+ select SYS_FSL_SEC_COMPAT_2
config ARCH_MPC8572
bool
select FSL_LAW
+ select SYS_FSL_HAS_SEC
+ select SYS_FSL_SEC_COMPAT_2
config ARCH_P1010
bool
select FSL_LAW
+ select SYS_FSL_HAS_SEC
+ select SYS_FSL_SEC_COMPAT_4
select SYS_PPC_E500_USE_DEBUG_TLB
config ARCH_P1011
bool
select FSL_LAW
+ select SYS_FSL_HAS_SEC
+ select SYS_FSL_SEC_COMPAT_2
select SYS_PPC_E500_USE_DEBUG_TLB
config ARCH_P1020
bool
select FSL_LAW
+ select SYS_FSL_HAS_SEC
+ select SYS_FSL_SEC_COMPAT_2
select SYS_PPC_E500_USE_DEBUG_TLB
config ARCH_P1021
bool
select FSL_LAW
+ select SYS_FSL_HAS_SEC
+ select SYS_FSL_SEC_COMPAT_2
select SYS_PPC_E500_USE_DEBUG_TLB
config ARCH_P1022
bool
select FSL_LAW
+ select SYS_FSL_HAS_SEC
+ select SYS_FSL_SEC_COMPAT_2
select SYS_PPC_E500_USE_DEBUG_TLB
config ARCH_P1023
bool
select FSL_LAW
+ select SYS_FSL_HAS_SEC
+ select SYS_FSL_SEC_COMPAT_4
config ARCH_P1024
bool
select FSL_LAW
+ select SYS_FSL_HAS_SEC
+ select SYS_FSL_SEC_COMPAT_2
select SYS_PPC_E500_USE_DEBUG_TLB
config ARCH_P1025
bool
select FSL_LAW
+ select SYS_FSL_HAS_SEC
+ select SYS_FSL_SEC_COMPAT_2
select SYS_PPC_E500_USE_DEBUG_TLB
config ARCH_P2020
bool
select FSL_LAW
+ select SYS_FSL_HAS_SEC
+ select SYS_FSL_SEC_COMPAT_2
select SYS_PPC_E500_USE_DEBUG_TLB
config ARCH_P2041
bool
select E500MC
select FSL_LAW
+ select SYS_FSL_HAS_SEC
+ select SYS_FSL_SEC_COMPAT_4
config ARCH_P3041
bool
select E500MC
select FSL_LAW
+ select SYS_FSL_HAS_SEC
+ select SYS_FSL_SEC_COMPAT_4
config ARCH_P4080
bool
select E500MC
select FSL_LAW
+ select SYS_FSL_HAS_SEC
+ select SYS_FSL_SEC_COMPAT_4
config ARCH_P5020
bool
select E500MC
select FSL_LAW
+ select SYS_FSL_HAS_SEC
+ select SYS_FSL_SEC_COMPAT_4
config ARCH_P5040
bool
select E500MC
select FSL_LAW
+ select SYS_FSL_HAS_SEC
+ select SYS_FSL_SEC_COMPAT_4
config ARCH_QEMU_E500
bool
@@ -464,41 +518,57 @@ config ARCH_T1023
bool
select E500MC
select FSL_LAW
+ select SYS_FSL_HAS_SEC
+ select SYS_FSL_SEC_COMPAT_5
config ARCH_T1024
bool
select E500MC
select FSL_LAW
+ select SYS_FSL_HAS_SEC
+ select SYS_FSL_SEC_COMPAT_5
config ARCH_T1040
bool
select E500MC
select FSL_LAW
+ select SYS_FSL_HAS_SEC
+ select SYS_FSL_SEC_COMPAT_5
config ARCH_T1042
bool
select E500MC
select FSL_LAW
+ select SYS_FSL_HAS_SEC
+ select SYS_FSL_SEC_COMPAT_5
config ARCH_T2080
bool
select E500MC
select FSL_LAW
+ select SYS_FSL_HAS_SEC
+ select SYS_FSL_SEC_COMPAT_4
config ARCH_T2081
bool
select E500MC
select FSL_LAW
+ select SYS_FSL_HAS_SEC
+ select SYS_FSL_SEC_COMPAT_4
config ARCH_T4160
bool
select E500MC
select FSL_LAW
+ select SYS_FSL_HAS_SEC
+ select SYS_FSL_SEC_COMPAT_4
config ARCH_T4240
bool
select E500MC
select FSL_LAW
+ select SYS_FSL_HAS_SEC
+ select SYS_FSL_SEC_COMPAT_4
config BOOKE
bool
diff --git a/arch/powerpc/include/asm/config.h b/arch/powerpc/include/asm/config.h
index 9d3a3b4..9b7bcb0 100644
--- a/arch/powerpc/include/asm/config.h
+++ b/arch/powerpc/include/asm/config.h
@@ -72,7 +72,6 @@
*/
#if defined(CONFIG_MPC83xx)
#define CONFIG_SYS_FSL_SEC_BE
-#define CONFIG_SYS_FSL_SEC_COMPAT 2
#endif
/* Since so many PPC SOCs have a semi-common LBC, define this here */
diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h
index cbaba36..7131b61 100644
--- a/arch/powerpc/include/asm/config_mpc85xx.h
+++ b/arch/powerpc/include/asm/config_mpc85xx.h
@@ -25,7 +25,6 @@
#define CONFIG_SYS_FSL_SEC_MON_BE
#if defined(CONFIG_ARCH_MPC8536)
-#define CONFIG_SYS_FSL_SEC_COMPAT 2
#define CONFIG_SYS_FSL_ERRATUM_A004508
#define CONFIG_SYS_FSL_ERRATUM_A005125
@@ -34,16 +33,13 @@
#elif defined(CONFIG_ARCH_MPC8541)
#define CONFIG_SYS_FSL_DDRC_GEN1
-#define CONFIG_SYS_FSL_SEC_COMPAT 2
#elif defined(CONFIG_ARCH_MPC8544)
#define CONFIG_SYS_FSL_DDRC_GEN2
-#define CONFIG_SYS_FSL_SEC_COMPAT 2
#define CONFIG_SYS_FSL_ERRATUM_A005125
#elif defined(CONFIG_ARCH_MPC8548)
#define CONFIG_SYS_FSL_DDRC_GEN2
-#define CONFIG_SYS_FSL_SEC_COMPAT 2
#define CONFIG_SYS_FSL_ERRATUM_NMG_DDR120
#define CONFIG_SYS_FSL_ERRATUM_NMG_LBC103
#define CONFIG_SYS_FSL_ERRATUM_NMG_ETSEC129
@@ -58,14 +54,12 @@
#elif defined(CONFIG_ARCH_MPC8555)
#define CONFIG_SYS_FSL_DDRC_GEN1
-#define CONFIG_SYS_FSL_SEC_COMPAT 2
#elif defined(CONFIG_ARCH_MPC8560)
#define CONFIG_SYS_FSL_DDRC_GEN1
#elif defined(CONFIG_ARCH_MPC8568)
#define CONFIG_SYS_FSL_DDRC_GEN2
-#define CONFIG_SYS_FSL_SEC_COMPAT 2
#define QE_MURAM_SIZE 0x10000UL
#define MAX_QE_RISC 2
#define QE_NUM_OF_SNUM 28
@@ -76,7 +70,6 @@
#define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
#elif defined(CONFIG_ARCH_MPC8569)
-#define CONFIG_SYS_FSL_SEC_COMPAT 2
#define QE_MURAM_SIZE 0x20000UL
#define MAX_QE_RISC 4
#define QE_NUM_OF_SNUM 46
@@ -89,7 +82,6 @@
#define CONFIG_SYS_FSL_ERRATUM_A005125
#elif defined(CONFIG_ARCH_MPC8572)
-#define CONFIG_SYS_FSL_SEC_COMPAT 2
#define CONFIG_SYS_FSL_ERRATUM_DDR_115
#define CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134
#define CONFIG_SYS_FSL_ERRATUM_A004508
@@ -98,7 +90,6 @@
#elif defined(CONFIG_ARCH_P1010)
#define CONFIG_FSL_SDHC_V2_3
#define CONFIG_TSECV2
-#define CONFIG_SYS_FSL_SEC_COMPAT 4
#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
#define CONFIG_NUM_DDR_CONTROLLERS 1
#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
@@ -123,7 +114,6 @@
#elif defined(CONFIG_ARCH_P1011)
#define CONFIG_TSECV2
#define CONFIG_FSL_PCIE_DISABLE_ASPM
-#define CONFIG_SYS_FSL_SEC_COMPAT 2
#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
@@ -133,7 +123,6 @@
#elif defined(CONFIG_ARCH_P1020)
#define CONFIG_TSECV2
#define CONFIG_FSL_PCIE_DISABLE_ASPM
-#define CONFIG_SYS_FSL_SEC_COMPAT 2
#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
#define CONFIG_SYS_FSL_ERRATUM_A004508
@@ -145,7 +134,6 @@
#elif defined(CONFIG_ARCH_P1021)
#define CONFIG_TSECV2
#define CONFIG_FSL_PCIE_DISABLE_ASPM
-#define CONFIG_SYS_FSL_SEC_COMPAT 2
#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
#define QE_MURAM_SIZE 0x6000UL
@@ -157,7 +145,6 @@
#elif defined(CONFIG_ARCH_P1022)
#define CONFIG_TSECV2
-#define CONFIG_SYS_FSL_SEC_COMPAT 2
#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
@@ -167,7 +154,6 @@
#define CONFIG_SYS_FSL_ERRATUM_A004477
#elif defined(CONFIG_ARCH_P1023)
-#define CONFIG_SYS_FSL_SEC_COMPAT 4
#define CONFIG_SYS_NUM_FMAN 1
#define CONFIG_SYS_NUM_FM1_DTSEC 2
#define CONFIG_NUM_DDR_CONTROLLERS 1
@@ -185,7 +171,6 @@
#elif defined(CONFIG_ARCH_P1024)
#define CONFIG_TSECV2
#define CONFIG_FSL_PCIE_DISABLE_ASPM
-#define CONFIG_SYS_FSL_SEC_COMPAT 2
#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
@@ -197,7 +182,6 @@
#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
#define CONFIG_TSECV2
#define CONFIG_FSL_PCIE_DISABLE_ASPM
-#define CONFIG_SYS_FSL_SEC_COMPAT 2
#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
#define QE_MURAM_SIZE 0x6000UL
@@ -207,7 +191,6 @@
#define CONFIG_SYS_FSL_ERRATUM_A005125
#elif defined(CONFIG_ARCH_P2020)
-#define CONFIG_SYS_FSL_SEC_COMPAT 2
#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
#define CONFIG_SYS_FSL_ERRATUM_ESDHC_A001
#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
@@ -224,7 +207,6 @@
#define CONFIG_SYS_FSL_QORIQ_CHASSIS1
#define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
#define CONFIG_SYS_FSL_NUM_CC_PLLS 2
-#define CONFIG_SYS_FSL_SEC_COMPAT 4
#define CONFIG_SYS_NUM_FMAN 1
#define CONFIG_SYS_NUM_FM1_DTSEC 5
#define CONFIG_SYS_NUM_FM1_10GEC 1
@@ -259,7 +241,6 @@
#define CONFIG_SYS_FSL_QORIQ_CHASSIS1
#define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
#define CONFIG_SYS_FSL_NUM_CC_PLLS 2
-#define CONFIG_SYS_FSL_SEC_COMPAT 4
#define CONFIG_SYS_NUM_FMAN 1
#define CONFIG_SYS_NUM_FM1_DTSEC 5
#define CONFIG_SYS_NUM_FM1_10GEC 1
@@ -296,7 +277,6 @@
#define CONFIG_SYS_FSL_QORIQ_CHASSIS1
#define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
#define CONFIG_SYS_FSL_NUM_CC_PLLS 4
-#define CONFIG_SYS_FSL_SEC_COMPAT 4
#define CONFIG_SYS_NUM_FMAN 2
#define CONFIG_SYS_NUM_FM1_DTSEC 4
#define CONFIG_SYS_NUM_FM2_DTSEC 4
@@ -345,7 +325,6 @@
#define CONFIG_SYS_FSL_QORIQ_CHASSIS1
#define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
#define CONFIG_SYS_FSL_NUM_CC_PLLS 2
-#define CONFIG_SYS_FSL_SEC_COMPAT 4
#define CONFIG_SYS_NUM_FMAN 1
#define CONFIG_SYS_NUM_FM1_DTSEC 5
#define CONFIG_SYS_NUM_FM1_10GEC 1
@@ -378,7 +357,6 @@
#define CONFIG_SYS_FSL_QORIQ_CHASSIS1
#define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
#define CONFIG_SYS_FSL_NUM_CC_PLLS 3
-#define CONFIG_SYS_FSL_SEC_COMPAT 4
#define CONFIG_SYS_NUM_FMAN 2
#define CONFIG_SYS_NUM_FM1_DTSEC 5
#define CONFIG_SYS_NUM_FM1_10GEC 1
@@ -407,7 +385,6 @@
#elif defined(CONFIG_ARCH_BSC9131)
#define CONFIG_FSL_SDHC_V2_3
#define CONFIG_TSECV2
-#define CONFIG_SYS_FSL_SEC_COMPAT 4
#define CONFIG_NUM_DDR_CONTROLLERS 1
#define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_4
#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
@@ -423,7 +400,6 @@
#elif defined(CONFIG_ARCH_BSC9132)
#define CONFIG_FSL_SDHC_V2_3
#define CONFIG_TSECV2
-#define CONFIG_SYS_FSL_SEC_COMPAT 4
#define CONFIG_NUM_DDR_CONTROLLERS 2
#define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_6
#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
@@ -473,7 +449,6 @@
#define CONFIG_SYS_FSL_SRDS_2
#define CONFIG_SYS_FSL_SRDS_3
#define CONFIG_SYS_FSL_SRDS_4
-#define CONFIG_SYS_FSL_SEC_COMPAT 4
#define CONFIG_SYS_NUM_FMAN 2
#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
#define CONFIG_SYS_PME_CLK 0
@@ -515,7 +490,6 @@
#define CONFIG_SYS_MAPLE
#define CONFIG_SYS_CPRI
#define CONFIG_SYS_FSL_NUM_CC_PLLS 5
-#define CONFIG_SYS_FSL_SEC_COMPAT 4
#define CONFIG_SYS_NUM_FMAN 1
#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
#define CONFIG_SYS_FM1_CLK 0
@@ -578,7 +552,6 @@ defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022)
#define CONFIG_SYS_FSL_NUM_CC_PLLS 2
#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 1, 1 }
#define CONFIG_SYS_FSL_SRDS_1
-#define CONFIG_SYS_FSL_SEC_COMPAT 5
#define CONFIG_SYS_NUM_FMAN 1
#define CONFIG_SYS_NUM_FM1_DTSEC 5
#define CONFIG_NUM_DDR_CONTROLLERS 1
@@ -624,7 +597,6 @@ defined(CONFIG_PPC_T1014) || defined(CONFIG_PPC_T1013)
#define CONFIG_SYS_FSL_NUM_CC_PLL 2
#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 1, 1 }
#define CONFIG_SYS_FSL_SRDS_1
-#define CONFIG_SYS_FSL_SEC_COMPAT 5
#define CONFIG_SYS_NUM_FMAN 1
#define CONFIG_SYS_NUM_FM1_DTSEC 4
#define CONFIG_SYS_NUM_FM1_10GEC 1
@@ -661,7 +633,6 @@ defined(CONFIG_PPC_T1014) || defined(CONFIG_PPC_T1013)
#define CONFIG_SYS_FSL_CORES_PER_CLUSTER 4
#define CONFIG_SYS_FSL_NUM_CC_PLLS 2
#define CONFIG_SYS_FSL_QMAN_V3
-#define CONFIG_SYS_FSL_SEC_COMPAT 4
#define CONFIG_SYS_NUM_FMAN 1
#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 4, 4, 4 }
#define CONFIG_SYS_FSL_SRDS_1
@@ -709,7 +680,6 @@ defined(CONFIG_PPC_T1014) || defined(CONFIG_PPC_T1013)
#elif defined(CONFIG_ARCH_C29X)
#define CONFIG_FSL_SDHC_V2_3
#define CONFIG_TSECV2_1
-#define CONFIG_SYS_FSL_SEC_COMPAT 6
#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
#define CONFIG_NUM_DDR_CONTROLLERS 1
#define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_6
diff --git a/drivers/crypto/fsl/Kconfig b/drivers/crypto/fsl/Kconfig
index 86b2f2f..510a108 100644
--- a/drivers/crypto/fsl/Kconfig
+++ b/drivers/crypto/fsl/Kconfig
@@ -4,3 +4,36 @@ config FSL_CAAM
Enables the Freescale's Cryptographic Accelerator and Assurance
Module (CAAM), also known as the SEC version 4 (SEC4). The driver uses
Job Ring as interface to communicate with CAAM.
+
+config SYS_FSL_HAS_SEC
+ bool
+ help
+ Enable Freescale Secure Boot and Trusted Architecture
+
+config SYS_FSL_SEC_COMPAT_2
+ bool
+ help
+ Secure boot and trust architecture compatible version 2
+
+config SYS_FSL_SEC_COMPAT_4
+ bool
+ help
+ Secure boot and trust architecture compatible version 4
+
+config SYS_FSL_SEC_COMPAT_5
+ bool
+ help
+ Secure boot and trust architecture compatible version 5
+
+config SYS_FSL_SEC_COMPAT_6
+ bool
+ help
+ Secure boot and trust architecture compatible version 6
+
+config SYS_FSL_SEC_COMPAT
+ int "Freescale Secure Boot compatibility"
+ depends on SYS_FSL_HAS_SEC
+ default 2 if SYS_FSL_SEC_COMPAT_2
+ default 4 if SYS_FSL_SEC_COMPAT_4
+ default 5 if SYS_FSL_SEC_COMPAT_5
+ default 6 if SYS_FSL_SEC_COMPAT_6
diff --git a/include/configs/mx6_common.h b/include/configs/mx6_common.h
index d28654b..8ee7aaf 100644
--- a/include/configs/mx6_common.h
+++ b/include/configs/mx6_common.h
@@ -94,7 +94,6 @@
/* Secure boot (HAB) support */
#ifdef CONFIG_SECURE_BOOT
#define CONFIG_CSF_SIZE 0x2000
-#define CONFIG_SYS_FSL_SEC_COMPAT 4
#define CONFIG_FSL_CAAM
#define CONFIG_CMD_DEKBLOB
#define CONFIG_SYS_FSL_SEC_LE
diff --git a/include/configs/mx7_common.h b/include/configs/mx7_common.h
index 0645228..bd98925 100644
--- a/include/configs/mx7_common.h
+++ b/include/configs/mx7_common.h
@@ -75,7 +75,6 @@
/* Secure boot (HAB) support */
#ifdef CONFIG_SECURE_BOOT
#define CONFIG_CSF_SIZE 0x2000
-#define CONFIG_SYS_FSL_SEC_COMPAT 4
#define CONFIG_FSL_CAAM
#define CONFIG_CMD_DEKBLOB
#define CONFIG_SYS_FSL_SEC_LE
diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt
index 2f33c2e..fa54921 100644
--- a/scripts/config_whitelist.txt
+++ b/scripts/config_whitelist.txt
@@ -5548,7 +5548,6 @@ CONFIG_SYS_FSL_SCFG_PIXCLKCR_OFFSET
CONFIG_SYS_FSL_SCFG_PIXCLK_ADDR
CONFIG_SYS_FSL_SEC_ADDR
CONFIG_SYS_FSL_SEC_BE
-CONFIG_SYS_FSL_SEC_COMPAT
CONFIG_SYS_FSL_SEC_IDX_OFFSET
CONFIG_SYS_FSL_SEC_LE
CONFIG_SYS_FSL_SEC_MON_BE
--
2.7.4
next prev parent reply other threads:[~2016-12-28 16:43 UTC|newest]
Thread overview: 52+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-12-28 16:43 [U-Boot] [PATCH 00/24] Lift mpc85xx config options to Kconfig York Sun
2016-12-28 16:43 ` [U-Boot] [PATCH 01/24] powerpc: E500: Move CONFIG_E500 and CONFIG_E500MC " York Sun
2017-01-05 13:28 ` [U-Boot] [U-Boot, " Tom Rini
2016-12-28 16:43 ` [U-Boot] [PATCH 02/24] powerpc: mpc85xx: Move CONFIG_SYS_NUM_TLBCAMS " York Sun
2017-01-05 13:28 ` [U-Boot] [U-Boot, " Tom Rini
2016-12-28 16:43 ` [U-Boot] [PATCH 03/24] powerpc: mpc85xx: Move CONFIG_SYS_PPC_E500_DEBUG_TLB " York Sun
2017-01-05 13:28 ` [U-Boot] [U-Boot, " Tom Rini
2016-12-28 16:43 ` York Sun [this message]
2017-01-05 13:28 ` [U-Boot] [U-Boot, 04/24] crypto: Move SYS_FSL_SEC_COMPAT into driver Kconfig Tom Rini
2016-12-28 16:43 ` [U-Boot] [PATCH 05/24] crypto: Move CONFIG_SYS_FSL_SEC_LE and _BE to Kconfig York Sun
2017-01-05 13:28 ` [U-Boot] [U-Boot, " Tom Rini
2016-12-28 16:43 ` [U-Boot] [PATCH 06/24] powerpc: mpc85xx: Remove variant SoCs T1020/T1022/T1013/T1014 York Sun
2017-01-05 13:28 ` [U-Boot] [U-Boot, " Tom Rini
2016-12-28 16:43 ` [U-Boot] [PATCH 07/24] powerpc: T1023RDB: Remove macro CONFIG_T1023RDB York Sun
2017-01-05 13:28 ` [U-Boot] [U-Boot, " Tom Rini
2016-12-28 16:43 ` [U-Boot] [PATCH 08/24] powerpc: T1024RDB: Remove macro CONFIG_T1024RDB York Sun
2017-01-05 13:29 ` [U-Boot] [U-Boot, " Tom Rini
2016-12-28 16:43 ` [U-Boot] [PATCH 09/24] powerpc: T1040QDS: Remove macro CONFIG_T1040QDS York Sun
2017-01-05 13:29 ` [U-Boot] [U-Boot, " Tom Rini
2016-12-28 16:43 ` [U-Boot] [PATCH 10/24] powerpc: T2080QDS: Remove macro T2080QDS York Sun
2017-01-05 13:29 ` [U-Boot] [U-Boot, " Tom Rini
2016-12-28 16:43 ` [U-Boot] [PATCH 11/24] powerpc: T2080RDB: Remove macro CONFIG_T2080RDB York Sun
2017-01-05 13:29 ` [U-Boot] [U-Boot, " Tom Rini
2016-12-28 16:43 ` [U-Boot] [PATCH 12/24] powerpc: T2081QDS: Remove macro T2081QDS York Sun
2017-01-05 13:29 ` [U-Boot] [U-Boot, " Tom Rini
2016-12-28 16:43 ` [U-Boot] [PATCH 13/24] powerpc: T104xQDS: Remove macro CONFIG_T104xD4QDS York Sun
2017-01-05 13:29 ` [U-Boot] [U-Boot, " Tom Rini
2016-12-28 16:43 ` [U-Boot] [PATCH 14/24] fsl_ddr: Move DDR config options to driver Kconfig York Sun
2017-01-05 13:29 ` [U-Boot] [U-Boot, " Tom Rini
2016-12-28 16:43 ` [U-Boot] [PATCH 15/24] arm: layerscape: Move CONFIG_SYS_FSL_ERRATUM_* to Kconfig York Sun
2017-01-05 13:29 ` [U-Boot] [U-Boot, " Tom Rini
2016-12-28 16:43 ` [U-Boot] [PATCH 16/24] mmc: move CONFIG_SYS_FSL_ERRATUM_ESDHC* " York Sun
2017-01-05 13:29 ` [U-Boot] [U-Boot, " Tom Rini
2016-12-28 16:43 ` [U-Boot] [PATCH 17/24] powerpc: mpc85xx: Move CONFIG_SYS_FSL_ERRATUM_* " York Sun
2017-01-05 13:29 ` [U-Boot] [U-Boot, " Tom Rini
2016-12-28 16:43 ` [U-Boot] [PATCH 18/24] ddr: fsl: Move macro CONFIG_NUM_DDR_CONTROLLERS " York Sun
2017-01-05 13:29 ` [U-Boot] [U-Boot, " Tom Rini
2016-12-28 16:43 ` [U-Boot] [PATCH 19/24] ddr: fsl: Merge macro CONFIG_NUM_DDR_CONTROLLERS and CONFIG_SYS_NUM_DDR_CTRLS York Sun
2017-01-05 13:29 ` [U-Boot] [U-Boot, " Tom Rini
2016-12-28 16:43 ` [U-Boot] [PATCH 20/24] ddr: fsl: Move CONFIG_SYS_FSL_DDR_VER to Kconfig York Sun
2017-01-05 13:29 ` [U-Boot] [U-Boot, " Tom Rini
2016-12-28 16:43 ` [U-Boot] [PATCH 21/24] powerpc: mpc85xx: Remove unused ifdef in config header York Sun
2017-01-05 13:30 ` [U-Boot] [U-Boot, " Tom Rini
2016-12-28 16:43 ` [U-Boot] [PATCH 22/24] powerpc: E6500: Move macro CONFIG_E6500 to Kconfig York Sun
2017-01-05 13:30 ` [U-Boot] [U-Boot, " Tom Rini
2016-12-28 16:43 ` [U-Boot] [PATCH 23/24] powerpc: mpc85xx: Move CONFIG_SYS_FSL_QORIQ_CHASSIS* " York Sun
2017-01-05 13:30 ` [U-Boot] [U-Boot, " Tom Rini
2016-12-28 16:43 ` [U-Boot] [PATCH 24/24] powerpc: mpc85xx: Move macro CONFIG_SYS_PPC64 " York Sun
2017-01-05 13:30 ` [U-Boot] [U-Boot, " Tom Rini
2017-01-05 13:28 ` [U-Boot] [PATCH 00/24] Lift mpc85xx config options " Tom Rini
2017-01-05 16:28 ` york sun
2017-01-05 17:34 ` york sun
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=1482943430-10231-5-git-send-email-york.sun@nxp.com \
--to=york.sun@nxp.com \
--cc=u-boot@lists.denx.de \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.