From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753078AbcL3G0e (ORCPT ); Fri, 30 Dec 2016 01:26:34 -0500 Received: from mailgw01.mediatek.com ([210.61.82.183]:31607 "EHLO mailgw01.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1752162AbcL3G0d (ORCPT ); Fri, 30 Dec 2016 01:26:33 -0500 From: Bibby Hsieh To: David Airlie , Matthias Brugger , Daniel Vetter , , CC: Yingjoe Chen , Cawa Cheng , Daniel Kurtz , Bibby Hsieh , Philipp Zabel , YT Shen , Thierry Reding , CK Hu , Mao Huang , , , Sascha Hauer Subject: [PATCH v2] drm/mediatek: Support UYVY and YUYV format for overlay Date: Fri, 30 Dec 2016 14:26:23 +0800 Message-ID: <1483079183-38637-1-git-send-email-bibby.hsieh@mediatek.com> X-Mailer: git-send-email 1.9.1 MIME-Version: 1.0 Content-Type: text/plain X-MTK: N Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org MT8173 overlay can support UYVY and YUYV format, we add the format in DRM driver. Signed-off-by: Bibby Hsieh Reviewed-by: Daniel Kurtz --- drivers/gpu/drm/mediatek/mtk_disp_ovl.c | 21 +++++++++++++++++++++ drivers/gpu/drm/mediatek/mtk_drm_plane.c | 2 ++ 2 files changed, 23 insertions(+) diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c index c703102..de05845 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c @@ -40,10 +40,13 @@ #define OVL_RDMA_MEM_GMC 0x40402020 #define OVL_CON_BYTE_SWAP BIT(24) +#define OVL_CON_MTX_YUV_TO_RGB (6 << 16) #define OVL_CON_CLRFMT_RGB565 (0 << 12) #define OVL_CON_CLRFMT_RGB888 (1 << 12) #define OVL_CON_CLRFMT_RGBA8888 (2 << 12) #define OVL_CON_CLRFMT_ARGB8888 (3 << 12) +#define OVL_CON_CLRFMT_UYVY (4 << 12) +#define OVL_CON_CLRFMT_YUYV (5 << 12) #define OVL_CON_AEN BIT(8) #define OVL_CON_ALPHA 0xff @@ -162,6 +165,21 @@ static unsigned int ovl_fmt_convert(unsigned int fmt) case DRM_FORMAT_XBGR8888: case DRM_FORMAT_ABGR8888: return OVL_CON_CLRFMT_RGBA8888 | OVL_CON_BYTE_SWAP; + case DRM_FORMAT_UYVY: + return OVL_CON_CLRFMT_UYVY; + case DRM_FORMAT_YUYV: + return OVL_CON_CLRFMT_YUYV; + } +} + +static bool ovl_yuv_space(unsigned int fmt) +{ + switch (fmt) { + case DRM_FORMAT_UYVY: + case DRM_FORMAT_YUYV: + return true; + default: + return false; } } @@ -183,6 +201,9 @@ static void mtk_ovl_layer_config(struct mtk_ddp_comp *comp, unsigned int idx, if (idx != 0) con |= OVL_CON_AEN | OVL_CON_ALPHA; + if (ovl_yuv_space(fmt)) + con |= OVL_CON_MTX_YUV_TO_RGB; + writel_relaxed(con, comp->regs + DISP_REG_OVL_CON(idx)); writel_relaxed(pitch, comp->regs + DISP_REG_OVL_PITCH(idx)); writel_relaxed(src_size, comp->regs + DISP_REG_OVL_SRC_SIZE(idx)); diff --git a/drivers/gpu/drm/mediatek/mtk_drm_plane.c b/drivers/gpu/drm/mediatek/mtk_drm_plane.c index c461a23..8c02d1d 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_plane.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_plane.c @@ -28,6 +28,8 @@ DRM_FORMAT_XRGB8888, DRM_FORMAT_ARGB8888, DRM_FORMAT_RGB565, + DRM_FORMAT_UYVY, + DRM_FORMAT_YUYV, }; static void mtk_plane_reset(struct drm_plane *plane) -- 1.9.1 From mboxrd@z Thu Jan 1 00:00:00 1970 From: Bibby Hsieh Subject: [PATCH v2] drm/mediatek: Support UYVY and YUYV format for overlay Date: Fri, 30 Dec 2016 14:26:23 +0800 Message-ID: <1483079183-38637-1-git-send-email-bibby.hsieh@mediatek.com> Mime-Version: 1.0 Content-Type: text/plain Return-path: Sender: linux-kernel-owner@vger.kernel.org To: David Airlie , Matthias Brugger , Daniel Vetter , dri-devel@lists.freedesktop.org, linux-mediatek@lists.infradead.org Cc: Yingjoe Chen , Cawa Cheng , Daniel Kurtz , Bibby Hsieh , Philipp Zabel , YT Shen , Thierry Reding , CK Hu , Mao Huang , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Sascha Hauer List-Id: linux-mediatek@lists.infradead.org MT8173 overlay can support UYVY and YUYV format, we add the format in DRM driver. Signed-off-by: Bibby Hsieh Reviewed-by: Daniel Kurtz --- drivers/gpu/drm/mediatek/mtk_disp_ovl.c | 21 +++++++++++++++++++++ drivers/gpu/drm/mediatek/mtk_drm_plane.c | 2 ++ 2 files changed, 23 insertions(+) diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c index c703102..de05845 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c @@ -40,10 +40,13 @@ #define OVL_RDMA_MEM_GMC 0x40402020 #define OVL_CON_BYTE_SWAP BIT(24) +#define OVL_CON_MTX_YUV_TO_RGB (6 << 16) #define OVL_CON_CLRFMT_RGB565 (0 << 12) #define OVL_CON_CLRFMT_RGB888 (1 << 12) #define OVL_CON_CLRFMT_RGBA8888 (2 << 12) #define OVL_CON_CLRFMT_ARGB8888 (3 << 12) +#define OVL_CON_CLRFMT_UYVY (4 << 12) +#define OVL_CON_CLRFMT_YUYV (5 << 12) #define OVL_CON_AEN BIT(8) #define OVL_CON_ALPHA 0xff @@ -162,6 +165,21 @@ static unsigned int ovl_fmt_convert(unsigned int fmt) case DRM_FORMAT_XBGR8888: case DRM_FORMAT_ABGR8888: return OVL_CON_CLRFMT_RGBA8888 | OVL_CON_BYTE_SWAP; + case DRM_FORMAT_UYVY: + return OVL_CON_CLRFMT_UYVY; + case DRM_FORMAT_YUYV: + return OVL_CON_CLRFMT_YUYV; + } +} + +static bool ovl_yuv_space(unsigned int fmt) +{ + switch (fmt) { + case DRM_FORMAT_UYVY: + case DRM_FORMAT_YUYV: + return true; + default: + return false; } } @@ -183,6 +201,9 @@ static void mtk_ovl_layer_config(struct mtk_ddp_comp *comp, unsigned int idx, if (idx != 0) con |= OVL_CON_AEN | OVL_CON_ALPHA; + if (ovl_yuv_space(fmt)) + con |= OVL_CON_MTX_YUV_TO_RGB; + writel_relaxed(con, comp->regs + DISP_REG_OVL_CON(idx)); writel_relaxed(pitch, comp->regs + DISP_REG_OVL_PITCH(idx)); writel_relaxed(src_size, comp->regs + DISP_REG_OVL_SRC_SIZE(idx)); diff --git a/drivers/gpu/drm/mediatek/mtk_drm_plane.c b/drivers/gpu/drm/mediatek/mtk_drm_plane.c index c461a23..8c02d1d 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_plane.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_plane.c @@ -28,6 +28,8 @@ DRM_FORMAT_XRGB8888, DRM_FORMAT_ARGB8888, DRM_FORMAT_RGB565, + DRM_FORMAT_UYVY, + DRM_FORMAT_YUYV, }; static void mtk_plane_reset(struct drm_plane *plane) -- 1.9.1 From mboxrd@z Thu Jan 1 00:00:00 1970 From: bibby.hsieh@mediatek.com (Bibby Hsieh) Date: Fri, 30 Dec 2016 14:26:23 +0800 Subject: [PATCH v2] drm/mediatek: Support UYVY and YUYV format for overlay Message-ID: <1483079183-38637-1-git-send-email-bibby.hsieh@mediatek.com> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org MT8173 overlay can support UYVY and YUYV format, we add the format in DRM driver. Signed-off-by: Bibby Hsieh Reviewed-by: Daniel Kurtz --- drivers/gpu/drm/mediatek/mtk_disp_ovl.c | 21 +++++++++++++++++++++ drivers/gpu/drm/mediatek/mtk_drm_plane.c | 2 ++ 2 files changed, 23 insertions(+) diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c index c703102..de05845 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c @@ -40,10 +40,13 @@ #define OVL_RDMA_MEM_GMC 0x40402020 #define OVL_CON_BYTE_SWAP BIT(24) +#define OVL_CON_MTX_YUV_TO_RGB (6 << 16) #define OVL_CON_CLRFMT_RGB565 (0 << 12) #define OVL_CON_CLRFMT_RGB888 (1 << 12) #define OVL_CON_CLRFMT_RGBA8888 (2 << 12) #define OVL_CON_CLRFMT_ARGB8888 (3 << 12) +#define OVL_CON_CLRFMT_UYVY (4 << 12) +#define OVL_CON_CLRFMT_YUYV (5 << 12) #define OVL_CON_AEN BIT(8) #define OVL_CON_ALPHA 0xff @@ -162,6 +165,21 @@ static unsigned int ovl_fmt_convert(unsigned int fmt) case DRM_FORMAT_XBGR8888: case DRM_FORMAT_ABGR8888: return OVL_CON_CLRFMT_RGBA8888 | OVL_CON_BYTE_SWAP; + case DRM_FORMAT_UYVY: + return OVL_CON_CLRFMT_UYVY; + case DRM_FORMAT_YUYV: + return OVL_CON_CLRFMT_YUYV; + } +} + +static bool ovl_yuv_space(unsigned int fmt) +{ + switch (fmt) { + case DRM_FORMAT_UYVY: + case DRM_FORMAT_YUYV: + return true; + default: + return false; } } @@ -183,6 +201,9 @@ static void mtk_ovl_layer_config(struct mtk_ddp_comp *comp, unsigned int idx, if (idx != 0) con |= OVL_CON_AEN | OVL_CON_ALPHA; + if (ovl_yuv_space(fmt)) + con |= OVL_CON_MTX_YUV_TO_RGB; + writel_relaxed(con, comp->regs + DISP_REG_OVL_CON(idx)); writel_relaxed(pitch, comp->regs + DISP_REG_OVL_PITCH(idx)); writel_relaxed(src_size, comp->regs + DISP_REG_OVL_SRC_SIZE(idx)); diff --git a/drivers/gpu/drm/mediatek/mtk_drm_plane.c b/drivers/gpu/drm/mediatek/mtk_drm_plane.c index c461a23..8c02d1d 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_plane.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_plane.c @@ -28,6 +28,8 @@ DRM_FORMAT_XRGB8888, DRM_FORMAT_ARGB8888, DRM_FORMAT_RGB565, + DRM_FORMAT_UYVY, + DRM_FORMAT_YUYV, }; static void mtk_plane_reset(struct drm_plane *plane) -- 1.9.1