[PATCH v2 0/6] Add some DT nodes for Mediatek MT2701

[PATCH v2 0/6] Add some DT nodes for Mediatek MT2701

[Erin Lo]

This patch series based on v4.10-rc2, include MT2701 spi/iommu/nand/auxadc/ethernet/thermal controller DT nodes.

Dependent on "Add clock and power domain DT nodes for Mediatek MT2701"[1].

Change in v2:
1. Add spi/auxadc pin setting
2. Add ethernet node and pin setting
3. Add thermal controller node

[1] http://lists.infradead.org/pipermail/linux-mediatek/2016-December/007637.html

Dawei Chien (1):
  arm: dts: mt2701: Add thermal device node.

Honghui Zhang (1):
  arm: dts: mt2701: Add iommu/smi device node

Leilk Liu (1):
  arm: dts: mt2701: Add spi device node

Sean Wang (1):
  arm: dts: mt2701: Add ethernet device node.

Xiaolei Li (1):
  arm: dts: mt2701: Add nand device node

Zhiyong Tao (1):
  arm: dts: mt2701: Add auxadc device node.

 arch/arm/boot/dts/mt2701-evb.dts |  94 +++++++++++++++++++
 arch/arm/boot/dts/mt2701.dtsi    | 189 +++++++++++++++++++++++++++++++++++++++
 2 files changed, 283 insertions(+)

--
1.9.1

[PATCH v2 0/6] Add some DT nodes for Mediatek MT2701

[Erin Lo]

This patch series based on v4.10-rc2, include MT2701 spi/iommu/nand/auxadc/ethernet/thermal controller DT nodes.

Dependent on "Add clock and power domain DT nodes for Mediatek MT2701"[1].

Change in v2:
1. Add spi/auxadc pin setting
2. Add ethernet node and pin setting
3. Add thermal controller node

[1] http://lists.infradead.org/pipermail/linux-mediatek/2016-December/007637.html

Dawei Chien (1):
  arm: dts: mt2701: Add thermal device node.

Honghui Zhang (1):
  arm: dts: mt2701: Add iommu/smi device node

Leilk Liu (1):
  arm: dts: mt2701: Add spi device node

Sean Wang (1):
  arm: dts: mt2701: Add ethernet device node.

Xiaolei Li (1):
  arm: dts: mt2701: Add nand device node

Zhiyong Tao (1):
  arm: dts: mt2701: Add auxadc device node.

 arch/arm/boot/dts/mt2701-evb.dts |  94 +++++++++++++++++++
 arch/arm/boot/dts/mt2701.dtsi    | 189 +++++++++++++++++++++++++++++++++++++++
 2 files changed, 283 insertions(+)

--
1.9.1

[PATCH v2 0/6] Add some DT nodes for Mediatek MT2701

[Erin Lo]

This patch series based on v4.10-rc2, include MT2701 spi/iommu/nand/auxadc/ethernet/thermal controller DT nodes.

Dependent on "Add clock and power domain DT nodes for Mediatek MT2701"[1].

Change in v2:
1. Add spi/auxadc pin setting
2. Add ethernet node and pin setting
3. Add thermal controller node

[1] http://lists.infradead.org/pipermail/linux-mediatek/2016-December/007637.html

Dawei Chien (1):
  arm: dts: mt2701: Add thermal device node.

Honghui Zhang (1):
  arm: dts: mt2701: Add iommu/smi device node

Leilk Liu (1):
  arm: dts: mt2701: Add spi device node

Sean Wang (1):
  arm: dts: mt2701: Add ethernet device node.

Xiaolei Li (1):
  arm: dts: mt2701: Add nand device node

Zhiyong Tao (1):
  arm: dts: mt2701: Add auxadc device node.

 arch/arm/boot/dts/mt2701-evb.dts |  94 +++++++++++++++++++
 arch/arm/boot/dts/mt2701.dtsi    | 189 +++++++++++++++++++++++++++++++++++++++
 2 files changed, 283 insertions(+)

--
1.9.1

[PATCH v2 1/6] arm: dts: mt2701: Add spi device node

[Erin Lo]

From: Leilk Liu <leilk.liu@mediatek.com>

Add spi device node for MT2701.

Signed-off-by: Leilk Liu <leilk.liu@mediatek.com>
Signed-off-by: Erin Lo <erin.lo@mediatek.com>
---
 arch/arm/boot/dts/mt2701-evb.dts | 50 ++++++++++++++++++++++++++++++++++++++++
 arch/arm/boot/dts/mt2701.dtsi    | 39 +++++++++++++++++++++++++++++++
 2 files changed, 89 insertions(+)

diff --git a/arch/arm/boot/dts/mt2701-evb.dts b/arch/arm/boot/dts/mt2701-evb.dts
index 082ca88..879f1eb 100644
--- a/arch/arm/boot/dts/mt2701-evb.dts
+++ b/arch/arm/boot/dts/mt2701-evb.dts
@@ -24,6 +24,56 @@
 	};
 };
 
+&pio {
+	spi_pins_a: spi0@0 {
+		pins_spi {
+			pinmux = <MT2701_PIN_53_SPI0_CSN__FUNC_SPI0_CS>,
+				 <MT2701_PIN_54_SPI0_CK__FUNC_SPI0_CK>,
+				 <MT2701_PIN_55_SPI0_MI__FUNC_SPI0_MI>,
+				 <MT2701_PIN_56_SPI0_MO__FUNC_SPI0_MO>;
+			bias-disable;
+		};
+	};
+
+	spi_pins_b: spi1@0 {
+		pins_spi {
+			pinmux = <MT2701_PIN_7_SPI1_CSN__FUNC_SPI1_CS>,
+				 <MT2701_PIN_8_SPI1_MI__FUNC_SPI1_MI>,
+				 <MT2701_PIN_9_SPI1_MO__FUNC_SPI1_MO>,
+				 <MT2701_PIN_199_SPI1_CLK__FUNC_SPI1_CK>;
+			bias-disable;
+		};
+	};
+
+	spi_pins_c: spi2@0 {
+		pins_spi {
+			pinmux = <MT2701_PIN_101_SPI2_CSN__FUNC_SPI2_CS>,
+				 <MT2701_PIN_102_SPI2_MI__FUNC_SPI2_MI>,
+				 <MT2701_PIN_103_SPI2_MO__FUNC_SPI2_MO>,
+				 <MT2701_PIN_104_SPI2_CLK__FUNC_SPI2_CK>;
+			bias-disable;
+		};
+	};
+};
+
+&spi0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&spi_pins_a>;
+	status = "disabled";
+};
+
+&spi1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&spi_pins_b>;
+	status = "disabled";
+};
+
+&spi2 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&spi_pins_c>;
+	status = "disabled";
+};
+
 &uart0 {
 	status = "okay";
 };
diff --git a/arch/arm/boot/dts/mt2701.dtsi b/arch/arm/boot/dts/mt2701.dtsi
index bdf8954..eb4c6fd 100644
--- a/arch/arm/boot/dts/mt2701.dtsi
+++ b/arch/arm/boot/dts/mt2701.dtsi
@@ -227,6 +227,45 @@
 		status = "disabled";
 	};
 
+	spi0: spi@1100a000 {
+		compatible = "mediatek,mt2701-spi";
+		#address-cells = <1>;
+		#size-cells = <0>;
+		reg = <0 0x1100a000 0 0x100>;
+		interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_LOW>;
+		clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
+			 <&topckgen CLK_TOP_SPI0_SEL>,
+			 <&pericfg CLK_PERI_SPI0>;
+		clock-names = "parent-clk", "sel-clk", "spi-clk";
+		status = "disabled";
+	};
+
+	spi1: spi@11016000 {
+		compatible = "mediatek,mt2701-spi";
+		#address-cells = <1>;
+		#size-cells = <0>;
+		reg = <0 0x11016000 0 0x100>;
+		interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_LOW>;
+		clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
+			 <&topckgen CLK_TOP_SPI1_SEL>,
+			 <&pericfg CLK_PERI_SPI1>;
+		clock-names = "parent-clk", "sel-clk", "spi-clk";
+		status = "disabled";
+	};
+
+	spi2: spi@11017000 {
+		compatible = "mediatek,mt2701-spi";
+		#address-cells = <1>;
+		#size-cells = <0>;
+		reg = <0 0x11017000 0 0x1000>;
+		interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_LOW>;
+		clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
+			 <&topckgen CLK_TOP_SPI2_SEL>,
+			 <&pericfg CLK_PERI_SPI2>;
+		clock-names = "parent-clk", "sel-clk", "spi-clk";
+		status = "disabled";
+	};
+
 	mmsys: syscon@14000000 {
 		compatible = "mediatek,mt2701-mmsys", "syscon";
 		reg = <0 0x14000000 0 0x1000>;
-- 
1.9.1

[PATCH v2 1/6] arm: dts: mt2701: Add spi device node

[Erin Lo]

From: Leilk Liu <leilk.liu-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org>

Add spi device node for MT2701.

Signed-off-by: Leilk Liu <leilk.liu-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org>
Signed-off-by: Erin Lo <erin.lo-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org>
---
 arch/arm/boot/dts/mt2701-evb.dts | 50 ++++++++++++++++++++++++++++++++++++++++
 arch/arm/boot/dts/mt2701.dtsi    | 39 +++++++++++++++++++++++++++++++
 2 files changed, 89 insertions(+)

diff --git a/arch/arm/boot/dts/mt2701-evb.dts b/arch/arm/boot/dts/mt2701-evb.dts
index 082ca88..879f1eb 100644
--- a/arch/arm/boot/dts/mt2701-evb.dts
+++ b/arch/arm/boot/dts/mt2701-evb.dts
@@ -24,6 +24,56 @@
 	};
 };
 
+&pio {
+	spi_pins_a: spi0@0 {
+		pins_spi {
+			pinmux = <MT2701_PIN_53_SPI0_CSN__FUNC_SPI0_CS>,
+				 <MT2701_PIN_54_SPI0_CK__FUNC_SPI0_CK>,
+				 <MT2701_PIN_55_SPI0_MI__FUNC_SPI0_MI>,
+				 <MT2701_PIN_56_SPI0_MO__FUNC_SPI0_MO>;
+			bias-disable;
+		};
+	};
+
+	spi_pins_b: spi1@0 {
+		pins_spi {
+			pinmux = <MT2701_PIN_7_SPI1_CSN__FUNC_SPI1_CS>,
+				 <MT2701_PIN_8_SPI1_MI__FUNC_SPI1_MI>,
+				 <MT2701_PIN_9_SPI1_MO__FUNC_SPI1_MO>,
+				 <MT2701_PIN_199_SPI1_CLK__FUNC_SPI1_CK>;
+			bias-disable;
+		};
+	};
+
+	spi_pins_c: spi2@0 {
+		pins_spi {
+			pinmux = <MT2701_PIN_101_SPI2_CSN__FUNC_SPI2_CS>,
+				 <MT2701_PIN_102_SPI2_MI__FUNC_SPI2_MI>,
+				 <MT2701_PIN_103_SPI2_MO__FUNC_SPI2_MO>,
+				 <MT2701_PIN_104_SPI2_CLK__FUNC_SPI2_CK>;
+			bias-disable;
+		};
+	};
+};
+
+&spi0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&spi_pins_a>;
+	status = "disabled";
+};
+
+&spi1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&spi_pins_b>;
+	status = "disabled";
+};
+
+&spi2 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&spi_pins_c>;
+	status = "disabled";
+};
+
 &uart0 {
 	status = "okay";
 };
diff --git a/arch/arm/boot/dts/mt2701.dtsi b/arch/arm/boot/dts/mt2701.dtsi
index bdf8954..eb4c6fd 100644
--- a/arch/arm/boot/dts/mt2701.dtsi
+++ b/arch/arm/boot/dts/mt2701.dtsi
@@ -227,6 +227,45 @@
 		status = "disabled";
 	};
 
+	spi0: spi@1100a000 {
+		compatible = "mediatek,mt2701-spi";
+		#address-cells = <1>;
+		#size-cells = <0>;
+		reg = <0 0x1100a000 0 0x100>;
+		interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_LOW>;
+		clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
+			 <&topckgen CLK_TOP_SPI0_SEL>,
+			 <&pericfg CLK_PERI_SPI0>;
+		clock-names = "parent-clk", "sel-clk", "spi-clk";
+		status = "disabled";
+	};
+
+	spi1: spi@11016000 {
+		compatible = "mediatek,mt2701-spi";
+		#address-cells = <1>;
+		#size-cells = <0>;
+		reg = <0 0x11016000 0 0x100>;
+		interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_LOW>;
+		clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
+			 <&topckgen CLK_TOP_SPI1_SEL>,
+			 <&pericfg CLK_PERI_SPI1>;
+		clock-names = "parent-clk", "sel-clk", "spi-clk";
+		status = "disabled";
+	};
+
+	spi2: spi@11017000 {
+		compatible = "mediatek,mt2701-spi";
+		#address-cells = <1>;
+		#size-cells = <0>;
+		reg = <0 0x11017000 0 0x1000>;
+		interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_LOW>;
+		clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
+			 <&topckgen CLK_TOP_SPI2_SEL>,
+			 <&pericfg CLK_PERI_SPI2>;
+		clock-names = "parent-clk", "sel-clk", "spi-clk";
+		status = "disabled";
+	};
+
 	mmsys: syscon@14000000 {
 		compatible = "mediatek,mt2701-mmsys", "syscon";
 		reg = <0 0x14000000 0 0x1000>;
-- 
1.9.1

[PATCH v2 1/6] arm: dts: mt2701: Add spi device node

[Erin Lo]

From: Leilk Liu <leilk.liu@mediatek.com>

Add spi device node for MT2701.

Signed-off-by: Leilk Liu <leilk.liu@mediatek.com>
Signed-off-by: Erin Lo <erin.lo@mediatek.com>
---
 arch/arm/boot/dts/mt2701-evb.dts | 50 ++++++++++++++++++++++++++++++++++++++++
 arch/arm/boot/dts/mt2701.dtsi    | 39 +++++++++++++++++++++++++++++++
 2 files changed, 89 insertions(+)

diff --git a/arch/arm/boot/dts/mt2701-evb.dts b/arch/arm/boot/dts/mt2701-evb.dts
index 082ca88..879f1eb 100644
--- a/arch/arm/boot/dts/mt2701-evb.dts
+++ b/arch/arm/boot/dts/mt2701-evb.dts
@@ -24,6 +24,56 @@
 	};
 };
 
+&pio {
+	spi_pins_a: spi0 at 0 {
+		pins_spi {
+			pinmux = <MT2701_PIN_53_SPI0_CSN__FUNC_SPI0_CS>,
+				 <MT2701_PIN_54_SPI0_CK__FUNC_SPI0_CK>,
+				 <MT2701_PIN_55_SPI0_MI__FUNC_SPI0_MI>,
+				 <MT2701_PIN_56_SPI0_MO__FUNC_SPI0_MO>;
+			bias-disable;
+		};
+	};
+
+	spi_pins_b: spi1 at 0 {
+		pins_spi {
+			pinmux = <MT2701_PIN_7_SPI1_CSN__FUNC_SPI1_CS>,
+				 <MT2701_PIN_8_SPI1_MI__FUNC_SPI1_MI>,
+				 <MT2701_PIN_9_SPI1_MO__FUNC_SPI1_MO>,
+				 <MT2701_PIN_199_SPI1_CLK__FUNC_SPI1_CK>;
+			bias-disable;
+		};
+	};
+
+	spi_pins_c: spi2 at 0 {
+		pins_spi {
+			pinmux = <MT2701_PIN_101_SPI2_CSN__FUNC_SPI2_CS>,
+				 <MT2701_PIN_102_SPI2_MI__FUNC_SPI2_MI>,
+				 <MT2701_PIN_103_SPI2_MO__FUNC_SPI2_MO>,
+				 <MT2701_PIN_104_SPI2_CLK__FUNC_SPI2_CK>;
+			bias-disable;
+		};
+	};
+};
+
+&spi0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&spi_pins_a>;
+	status = "disabled";
+};
+
+&spi1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&spi_pins_b>;
+	status = "disabled";
+};
+
+&spi2 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&spi_pins_c>;
+	status = "disabled";
+};
+
 &uart0 {
 	status = "okay";
 };
diff --git a/arch/arm/boot/dts/mt2701.dtsi b/arch/arm/boot/dts/mt2701.dtsi
index bdf8954..eb4c6fd 100644
--- a/arch/arm/boot/dts/mt2701.dtsi
+++ b/arch/arm/boot/dts/mt2701.dtsi
@@ -227,6 +227,45 @@
 		status = "disabled";
 	};
 
+	spi0: spi at 1100a000 {
+		compatible = "mediatek,mt2701-spi";
+		#address-cells = <1>;
+		#size-cells = <0>;
+		reg = <0 0x1100a000 0 0x100>;
+		interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_LOW>;
+		clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
+			 <&topckgen CLK_TOP_SPI0_SEL>,
+			 <&pericfg CLK_PERI_SPI0>;
+		clock-names = "parent-clk", "sel-clk", "spi-clk";
+		status = "disabled";
+	};
+
+	spi1: spi at 11016000 {
+		compatible = "mediatek,mt2701-spi";
+		#address-cells = <1>;
+		#size-cells = <0>;
+		reg = <0 0x11016000 0 0x100>;
+		interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_LOW>;
+		clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
+			 <&topckgen CLK_TOP_SPI1_SEL>,
+			 <&pericfg CLK_PERI_SPI1>;
+		clock-names = "parent-clk", "sel-clk", "spi-clk";
+		status = "disabled";
+	};
+
+	spi2: spi at 11017000 {
+		compatible = "mediatek,mt2701-spi";
+		#address-cells = <1>;
+		#size-cells = <0>;
+		reg = <0 0x11017000 0 0x1000>;
+		interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_LOW>;
+		clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
+			 <&topckgen CLK_TOP_SPI2_SEL>,
+			 <&pericfg CLK_PERI_SPI2>;
+		clock-names = "parent-clk", "sel-clk", "spi-clk";
+		status = "disabled";
+	};
+
 	mmsys: syscon at 14000000 {
 		compatible = "mediatek,mt2701-mmsys", "syscon";
 		reg = <0 0x14000000 0 0x1000>;
-- 
1.9.1

[PATCH v2 2/6] arm: dts: mt2701: Add iommu/smi device node

[Erin Lo]

From: Honghui Zhang <honghui.zhang@mediatek.com>

Add the device node of iommu and smi for MT2701.

Signed-off-by: Honghui Zhang <honghui.zhang@mediatek.com>
Signed-off-by: Erin Lo <erin.lo@mediatek.com>
---
 arch/arm/boot/dts/mt2701.dtsi | 54 +++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 54 insertions(+)

diff --git a/arch/arm/boot/dts/mt2701.dtsi b/arch/arm/boot/dts/mt2701.dtsi
index eb4c6fd..87be52c 100644
--- a/arch/arm/boot/dts/mt2701.dtsi
+++ b/arch/arm/boot/dts/mt2701.dtsi
@@ -17,6 +17,7 @@
 #include <dt-bindings/interrupt-controller/irq.h>
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 #include <dt-bindings/reset/mt2701-resets.h>
+#include <dt-bindings/memory/mt2701-larb-port.h>
 #include "skeleton64.dtsi"
 #include "mt2701-pinfunc.h"
 
@@ -161,6 +162,16 @@
 		clock-names = "system-clk", "rtc-clk";
 	};
 
+	smi_common: smi@1000c000 {
+		compatible = "mediatek,mt2701-smi-common";
+		reg = <0 0x1000c000 0 0x1000>;
+		clocks = <&infracfg CLK_INFRA_SMI>,
+			 <&mmsys CLK_MM_SMI_COMMON>,
+			 <&infracfg CLK_INFRA_SMI>;
+		clock-names = "apb", "smi", "async";
+		power-domains = <&scpsys MT2701_POWER_DOMAIN_DISP>;
+	};
+
 	sysirq: interrupt-controller@10200100 {
 		compatible = "mediatek,mt2701-sysirq",
 			     "mediatek,mt6577-sysirq";
@@ -170,6 +181,16 @@
 		reg = <0 0x10200100 0 0x1c>;
 	};
 
+	iommu: mmsys_iommu@10205000 {
+		compatible = "mediatek,mt2701-m4u";
+		reg = <0 0x10205000 0 0x1000>;
+		interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_LOW>;
+		clocks = <&infracfg CLK_INFRA_M4U>;
+		clock-names = "bclk";
+		mediatek,larbs = <&larb0 &larb1 &larb2>;
+		#iommu-cells = <1>;
+	};
+
 	apmixedsys: syscon@10209000 {
 		compatible = "mediatek,mt2701-apmixedsys", "syscon";
 		reg = <0 0x10209000 0 0x1000>;
@@ -272,18 +293,51 @@
 		#clock-cells = <1>;
 	};
 
+	larb0: larb@14010000 {
+		compatible = "mediatek,mt2701-smi-larb";
+		reg = <0 0x14010000 0 0x1000>;
+		mediatek,smi = <&smi_common>;
+		mediatek,larbidx = <0>;
+		clocks = <&mmsys CLK_MM_SMI_LARB0>,
+			 <&mmsys CLK_MM_SMI_LARB0>;
+		clock-names = "apb", "smi";
+		power-domains = <&scpsys MT2701_POWER_DOMAIN_DISP>;
+	};
+
 	imgsys: syscon@15000000 {
 		compatible = "mediatek,mt2701-imgsys", "syscon";
 		reg = <0 0x15000000 0 0x1000>;
 		#clock-cells = <1>;
 	};
 
+	larb2: larb@15001000 {
+		compatible = "mediatek,mt2701-smi-larb";
+		reg = <0 0x15001000 0 0x1000>;
+		mediatek,smi = <&smi_common>;
+		mediatek,larbidx = <2>;
+		clocks = <&imgsys CLK_IMG_SMI_COMM>,
+			 <&imgsys CLK_IMG_SMI_COMM>;
+		clock-names = "apb", "smi";
+		power-domains = <&scpsys MT2701_POWER_DOMAIN_ISP>;
+	};
+
 	vdecsys: syscon@16000000 {
 		compatible = "mediatek,mt2701-vdecsys", "syscon";
 		reg = <0 0x16000000 0 0x1000>;
 		#clock-cells = <1>;
 	};
 
+	larb1: larb@16010000 {
+		compatible = "mediatek,mt2701-smi-larb";
+		reg = <0 0x16010000 0 0x1000>;
+		mediatek,smi = <&smi_common>;
+		mediatek,larbidx = <1>;
+		clocks = <&vdecsys CLK_VDEC_CKGEN>,
+			 <&vdecsys CLK_VDEC_LARB>;
+		clock-names = "apb", "smi";
+		power-domains = <&scpsys MT2701_POWER_DOMAIN_VDEC>;
+	};
+
 	hifsys: syscon@1a000000 {
 		compatible = "mediatek,mt2701-hifsys", "syscon";
 		reg = <0 0x1a000000 0 0x1000>;
-- 
1.9.1

[PATCH v2 2/6] arm: dts: mt2701: Add iommu/smi device node

[Erin Lo]

From: Honghui Zhang <honghui.zhang-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org>

Add the device node of iommu and smi for MT2701.

Signed-off-by: Honghui Zhang <honghui.zhang-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org>
Signed-off-by: Erin Lo <erin.lo-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org>
---
 arch/arm/boot/dts/mt2701.dtsi | 54 +++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 54 insertions(+)

diff --git a/arch/arm/boot/dts/mt2701.dtsi b/arch/arm/boot/dts/mt2701.dtsi
index eb4c6fd..87be52c 100644
--- a/arch/arm/boot/dts/mt2701.dtsi
+++ b/arch/arm/boot/dts/mt2701.dtsi
@@ -17,6 +17,7 @@
 #include <dt-bindings/interrupt-controller/irq.h>
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 #include <dt-bindings/reset/mt2701-resets.h>
+#include <dt-bindings/memory/mt2701-larb-port.h>
 #include "skeleton64.dtsi"
 #include "mt2701-pinfunc.h"
 
@@ -161,6 +162,16 @@
 		clock-names = "system-clk", "rtc-clk";
 	};
 
+	smi_common: smi@1000c000 {
+		compatible = "mediatek,mt2701-smi-common";
+		reg = <0 0x1000c000 0 0x1000>;
+		clocks = <&infracfg CLK_INFRA_SMI>,
+			 <&mmsys CLK_MM_SMI_COMMON>,
+			 <&infracfg CLK_INFRA_SMI>;
+		clock-names = "apb", "smi", "async";
+		power-domains = <&scpsys MT2701_POWER_DOMAIN_DISP>;
+	};
+
 	sysirq: interrupt-controller@10200100 {
 		compatible = "mediatek,mt2701-sysirq",
 			     "mediatek,mt6577-sysirq";
@@ -170,6 +181,16 @@
 		reg = <0 0x10200100 0 0x1c>;
 	};
 
+	iommu: mmsys_iommu@10205000 {
+		compatible = "mediatek,mt2701-m4u";
+		reg = <0 0x10205000 0 0x1000>;
+		interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_LOW>;
+		clocks = <&infracfg CLK_INFRA_M4U>;
+		clock-names = "bclk";
+		mediatek,larbs = <&larb0 &larb1 &larb2>;
+		#iommu-cells = <1>;
+	};
+
 	apmixedsys: syscon@10209000 {
 		compatible = "mediatek,mt2701-apmixedsys", "syscon";
 		reg = <0 0x10209000 0 0x1000>;
@@ -272,18 +293,51 @@
 		#clock-cells = <1>;
 	};
 
+	larb0: larb@14010000 {
+		compatible = "mediatek,mt2701-smi-larb";
+		reg = <0 0x14010000 0 0x1000>;
+		mediatek,smi = <&smi_common>;
+		mediatek,larbidx = <0>;
+		clocks = <&mmsys CLK_MM_SMI_LARB0>,
+			 <&mmsys CLK_MM_SMI_LARB0>;
+		clock-names = "apb", "smi";
+		power-domains = <&scpsys MT2701_POWER_DOMAIN_DISP>;
+	};
+
 	imgsys: syscon@15000000 {
 		compatible = "mediatek,mt2701-imgsys", "syscon";
 		reg = <0 0x15000000 0 0x1000>;
 		#clock-cells = <1>;
 	};
 
+	larb2: larb@15001000 {
+		compatible = "mediatek,mt2701-smi-larb";
+		reg = <0 0x15001000 0 0x1000>;
+		mediatek,smi = <&smi_common>;
+		mediatek,larbidx = <2>;
+		clocks = <&imgsys CLK_IMG_SMI_COMM>,
+			 <&imgsys CLK_IMG_SMI_COMM>;
+		clock-names = "apb", "smi";
+		power-domains = <&scpsys MT2701_POWER_DOMAIN_ISP>;
+	};
+
 	vdecsys: syscon@16000000 {
 		compatible = "mediatek,mt2701-vdecsys", "syscon";
 		reg = <0 0x16000000 0 0x1000>;
 		#clock-cells = <1>;
 	};
 
+	larb1: larb@16010000 {
+		compatible = "mediatek,mt2701-smi-larb";
+		reg = <0 0x16010000 0 0x1000>;
+		mediatek,smi = <&smi_common>;
+		mediatek,larbidx = <1>;
+		clocks = <&vdecsys CLK_VDEC_CKGEN>,
+			 <&vdecsys CLK_VDEC_LARB>;
+		clock-names = "apb", "smi";
+		power-domains = <&scpsys MT2701_POWER_DOMAIN_VDEC>;
+	};
+
 	hifsys: syscon@1a000000 {
 		compatible = "mediatek,mt2701-hifsys", "syscon";
 		reg = <0 0x1a000000 0 0x1000>;
-- 
1.9.1

[PATCH v2 2/6] arm: dts: mt2701: Add iommu/smi device node

[Erin Lo]

From: Honghui Zhang <honghui.zhang@mediatek.com>

Add the device node of iommu and smi for MT2701.

Signed-off-by: Honghui Zhang <honghui.zhang@mediatek.com>
Signed-off-by: Erin Lo <erin.lo@mediatek.com>
---
 arch/arm/boot/dts/mt2701.dtsi | 54 +++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 54 insertions(+)

diff --git a/arch/arm/boot/dts/mt2701.dtsi b/arch/arm/boot/dts/mt2701.dtsi
index eb4c6fd..87be52c 100644
--- a/arch/arm/boot/dts/mt2701.dtsi
+++ b/arch/arm/boot/dts/mt2701.dtsi
@@ -17,6 +17,7 @@
 #include <dt-bindings/interrupt-controller/irq.h>
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 #include <dt-bindings/reset/mt2701-resets.h>
+#include <dt-bindings/memory/mt2701-larb-port.h>
 #include "skeleton64.dtsi"
 #include "mt2701-pinfunc.h"
 
@@ -161,6 +162,16 @@
 		clock-names = "system-clk", "rtc-clk";
 	};
 
+	smi_common: smi at 1000c000 {
+		compatible = "mediatek,mt2701-smi-common";
+		reg = <0 0x1000c000 0 0x1000>;
+		clocks = <&infracfg CLK_INFRA_SMI>,
+			 <&mmsys CLK_MM_SMI_COMMON>,
+			 <&infracfg CLK_INFRA_SMI>;
+		clock-names = "apb", "smi", "async";
+		power-domains = <&scpsys MT2701_POWER_DOMAIN_DISP>;
+	};
+
 	sysirq: interrupt-controller at 10200100 {
 		compatible = "mediatek,mt2701-sysirq",
 			     "mediatek,mt6577-sysirq";
@@ -170,6 +181,16 @@
 		reg = <0 0x10200100 0 0x1c>;
 	};
 
+	iommu: mmsys_iommu at 10205000 {
+		compatible = "mediatek,mt2701-m4u";
+		reg = <0 0x10205000 0 0x1000>;
+		interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_LOW>;
+		clocks = <&infracfg CLK_INFRA_M4U>;
+		clock-names = "bclk";
+		mediatek,larbs = <&larb0 &larb1 &larb2>;
+		#iommu-cells = <1>;
+	};
+
 	apmixedsys: syscon at 10209000 {
 		compatible = "mediatek,mt2701-apmixedsys", "syscon";
 		reg = <0 0x10209000 0 0x1000>;
@@ -272,18 +293,51 @@
 		#clock-cells = <1>;
 	};
 
+	larb0: larb at 14010000 {
+		compatible = "mediatek,mt2701-smi-larb";
+		reg = <0 0x14010000 0 0x1000>;
+		mediatek,smi = <&smi_common>;
+		mediatek,larbidx = <0>;
+		clocks = <&mmsys CLK_MM_SMI_LARB0>,
+			 <&mmsys CLK_MM_SMI_LARB0>;
+		clock-names = "apb", "smi";
+		power-domains = <&scpsys MT2701_POWER_DOMAIN_DISP>;
+	};
+
 	imgsys: syscon at 15000000 {
 		compatible = "mediatek,mt2701-imgsys", "syscon";
 		reg = <0 0x15000000 0 0x1000>;
 		#clock-cells = <1>;
 	};
 
+	larb2: larb at 15001000 {
+		compatible = "mediatek,mt2701-smi-larb";
+		reg = <0 0x15001000 0 0x1000>;
+		mediatek,smi = <&smi_common>;
+		mediatek,larbidx = <2>;
+		clocks = <&imgsys CLK_IMG_SMI_COMM>,
+			 <&imgsys CLK_IMG_SMI_COMM>;
+		clock-names = "apb", "smi";
+		power-domains = <&scpsys MT2701_POWER_DOMAIN_ISP>;
+	};
+
 	vdecsys: syscon at 16000000 {
 		compatible = "mediatek,mt2701-vdecsys", "syscon";
 		reg = <0 0x16000000 0 0x1000>;
 		#clock-cells = <1>;
 	};
 
+	larb1: larb at 16010000 {
+		compatible = "mediatek,mt2701-smi-larb";
+		reg = <0 0x16010000 0 0x1000>;
+		mediatek,smi = <&smi_common>;
+		mediatek,larbidx = <1>;
+		clocks = <&vdecsys CLK_VDEC_CKGEN>,
+			 <&vdecsys CLK_VDEC_LARB>;
+		clock-names = "apb", "smi";
+		power-domains = <&scpsys MT2701_POWER_DOMAIN_VDEC>;
+	};
+
 	hifsys: syscon at 1a000000 {
 		compatible = "mediatek,mt2701-hifsys", "syscon";
 		reg = <0 0x1a000000 0 0x1000>;
-- 
1.9.1

[PATCH v2 3/6] arm: dts: mt2701: Add nand device node

[Erin Lo]

From: Xiaolei Li <xiaolei.li@mediatek.com>

Add mt2701 nand device node, include nfi and bch ecc.

Signed-off-by: Xiaolei Li <xiaolei.li@mediatek.com>
Signed-off-by: Erin Lo <erin.lo@mediatek.com>
---
 arch/arm/boot/dts/mt2701.dtsi | 22 ++++++++++++++++++++++
 1 file changed, 22 insertions(+)

diff --git a/arch/arm/boot/dts/mt2701.dtsi b/arch/arm/boot/dts/mt2701.dtsi
index 87be52c..1182c43 100644
--- a/arch/arm/boot/dts/mt2701.dtsi
+++ b/arch/arm/boot/dts/mt2701.dtsi
@@ -261,6 +261,28 @@
 		status = "disabled";
 	};
 
+	nandc: nfi@1100d000 {
+		compatible = "mediatek,mt2701-nfc";
+		reg = <0 0x1100d000 0 0x1000>;
+		interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_LOW>;
+		clocks = <&pericfg CLK_PERI_NFI>,
+			 <&pericfg CLK_PERI_NFI_PAD>;
+		clock-names = "nfi_clk", "pad_clk";
+		status = "disabled";
+		ecc-engine = <&bch>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+	};
+
+	bch: ecc@1100e000 {
+		compatible = "mediatek,mt2701-ecc";
+		reg = <0 0x1100e000 0 0x1000>;
+		interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_LOW>;
+		clocks = <&pericfg CLK_PERI_NFI_ECC>;
+		clock-names = "nfiecc_clk";
+		status = "disabled";
+	};
+
 	spi1: spi@11016000 {
 		compatible = "mediatek,mt2701-spi";
 		#address-cells = <1>;
-- 
1.9.1

[PATCH v2 3/6] arm: dts: mt2701: Add nand device node

[Erin Lo]

From: Xiaolei Li <xiaolei.li@mediatek.com>

Add mt2701 nand device node, include nfi and bch ecc.

Signed-off-by: Xiaolei Li <xiaolei.li@mediatek.com>
Signed-off-by: Erin Lo <erin.lo@mediatek.com>
---
 arch/arm/boot/dts/mt2701.dtsi | 22 ++++++++++++++++++++++
 1 file changed, 22 insertions(+)

diff --git a/arch/arm/boot/dts/mt2701.dtsi b/arch/arm/boot/dts/mt2701.dtsi
index 87be52c..1182c43 100644
--- a/arch/arm/boot/dts/mt2701.dtsi
+++ b/arch/arm/boot/dts/mt2701.dtsi
@@ -261,6 +261,28 @@
 		status = "disabled";
 	};
 
+	nandc: nfi@1100d000 {
+		compatible = "mediatek,mt2701-nfc";
+		reg = <0 0x1100d000 0 0x1000>;
+		interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_LOW>;
+		clocks = <&pericfg CLK_PERI_NFI>,
+			 <&pericfg CLK_PERI_NFI_PAD>;
+		clock-names = "nfi_clk", "pad_clk";
+		status = "disabled";
+		ecc-engine = <&bch>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+	};
+
+	bch: ecc@1100e000 {
+		compatible = "mediatek,mt2701-ecc";
+		reg = <0 0x1100e000 0 0x1000>;
+		interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_LOW>;
+		clocks = <&pericfg CLK_PERI_NFI_ECC>;
+		clock-names = "nfiecc_clk";
+		status = "disabled";
+	};
+
 	spi1: spi@11016000 {
 		compatible = "mediatek,mt2701-spi";
 		#address-cells = <1>;
-- 
1.9.1

[PATCH v2 3/6] arm: dts: mt2701: Add nand device node

[Erin Lo]

From: Xiaolei Li <xiaolei.li@mediatek.com>

Add mt2701 nand device node, include nfi and bch ecc.

Signed-off-by: Xiaolei Li <xiaolei.li@mediatek.com>
Signed-off-by: Erin Lo <erin.lo@mediatek.com>
---
 arch/arm/boot/dts/mt2701.dtsi | 22 ++++++++++++++++++++++
 1 file changed, 22 insertions(+)

diff --git a/arch/arm/boot/dts/mt2701.dtsi b/arch/arm/boot/dts/mt2701.dtsi
index 87be52c..1182c43 100644
--- a/arch/arm/boot/dts/mt2701.dtsi
+++ b/arch/arm/boot/dts/mt2701.dtsi
@@ -261,6 +261,28 @@
 		status = "disabled";
 	};
 
+	nandc: nfi at 1100d000 {
+		compatible = "mediatek,mt2701-nfc";
+		reg = <0 0x1100d000 0 0x1000>;
+		interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_LOW>;
+		clocks = <&pericfg CLK_PERI_NFI>,
+			 <&pericfg CLK_PERI_NFI_PAD>;
+		clock-names = "nfi_clk", "pad_clk";
+		status = "disabled";
+		ecc-engine = <&bch>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+	};
+
+	bch: ecc at 1100e000 {
+		compatible = "mediatek,mt2701-ecc";
+		reg = <0 0x1100e000 0 0x1000>;
+		interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_LOW>;
+		clocks = <&pericfg CLK_PERI_NFI_ECC>;
+		clock-names = "nfiecc_clk";
+		status = "disabled";
+	};
+
 	spi1: spi at 11016000 {
 		compatible = "mediatek,mt2701-spi";
 		#address-cells = <1>;
-- 
1.9.1

[PATCH v2 4/6] arm: dts: mt2701: Add auxadc device node.

[Erin Lo]

From: Zhiyong Tao <zhiyong.tao@mediatek.com>

Add auxadc device node for MT2701.

Signed-off-by: Zhiyong Tao <zhiyong.tao@mediatek.com>
Signed-off-by: Erin Lo <erin.lo@mediatek.com>
---
 arch/arm/boot/dts/mt2701-evb.dts | 4 ++++
 arch/arm/boot/dts/mt2701.dtsi    | 9 +++++++++
 2 files changed, 13 insertions(+)

diff --git a/arch/arm/boot/dts/mt2701-evb.dts b/arch/arm/boot/dts/mt2701-evb.dts
index 879f1eb..a483798 100644
--- a/arch/arm/boot/dts/mt2701-evb.dts
+++ b/arch/arm/boot/dts/mt2701-evb.dts
@@ -24,6 +24,10 @@
 	};
 };
 
+&auxadc {
+	status = "okay";
+};
+
 &pio {
 	spi_pins_a: spi0@0 {
 		pins_spi {
diff --git a/arch/arm/boot/dts/mt2701.dtsi b/arch/arm/boot/dts/mt2701.dtsi
index 1182c43..4f52019 100644
--- a/arch/arm/boot/dts/mt2701.dtsi
+++ b/arch/arm/boot/dts/mt2701.dtsi
@@ -208,6 +208,15 @@
 		      <0 0x10216000 0 0x2000>;
 	};
 
+	auxadc: adc@11001000 {
+		compatible = "mediatek,mt2701-auxadc";
+		reg = <0 0x11001000 0 0x1000>;
+		clocks = <&pericfg CLK_PERI_AUXADC>;
+		clock-names = "main";
+		#io-channel-cells = <1>;
+		status = "disabled";
+	};
+
 	uart0: serial@11002000 {
 		compatible = "mediatek,mt2701-uart",
 			     "mediatek,mt6577-uart";
-- 
1.9.1

[PATCH v2 4/6] arm: dts: mt2701: Add auxadc device node.

[Erin Lo]

From: Zhiyong Tao <zhiyong.tao-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org>

Add auxadc device node for MT2701.

Signed-off-by: Zhiyong Tao <zhiyong.tao-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org>
Signed-off-by: Erin Lo <erin.lo-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org>
---
 arch/arm/boot/dts/mt2701-evb.dts | 4 ++++
 arch/arm/boot/dts/mt2701.dtsi    | 9 +++++++++
 2 files changed, 13 insertions(+)

diff --git a/arch/arm/boot/dts/mt2701-evb.dts b/arch/arm/boot/dts/mt2701-evb.dts
index 879f1eb..a483798 100644
--- a/arch/arm/boot/dts/mt2701-evb.dts
+++ b/arch/arm/boot/dts/mt2701-evb.dts
@@ -24,6 +24,10 @@
 	};
 };
 
+&auxadc {
+	status = "okay";
+};
+
 &pio {
 	spi_pins_a: spi0@0 {
 		pins_spi {
diff --git a/arch/arm/boot/dts/mt2701.dtsi b/arch/arm/boot/dts/mt2701.dtsi
index 1182c43..4f52019 100644
--- a/arch/arm/boot/dts/mt2701.dtsi
+++ b/arch/arm/boot/dts/mt2701.dtsi
@@ -208,6 +208,15 @@
 		      <0 0x10216000 0 0x2000>;
 	};
 
+	auxadc: adc@11001000 {
+		compatible = "mediatek,mt2701-auxadc";
+		reg = <0 0x11001000 0 0x1000>;
+		clocks = <&pericfg CLK_PERI_AUXADC>;
+		clock-names = "main";
+		#io-channel-cells = <1>;
+		status = "disabled";
+	};
+
 	uart0: serial@11002000 {
 		compatible = "mediatek,mt2701-uart",
 			     "mediatek,mt6577-uart";
-- 
1.9.1

[PATCH v2 4/6] arm: dts: mt2701: Add auxadc device node.

[Erin Lo]

From: Zhiyong Tao <zhiyong.tao@mediatek.com>

Add auxadc device node for MT2701.

Signed-off-by: Zhiyong Tao <zhiyong.tao@mediatek.com>
Signed-off-by: Erin Lo <erin.lo@mediatek.com>
---
 arch/arm/boot/dts/mt2701-evb.dts | 4 ++++
 arch/arm/boot/dts/mt2701.dtsi    | 9 +++++++++
 2 files changed, 13 insertions(+)

diff --git a/arch/arm/boot/dts/mt2701-evb.dts b/arch/arm/boot/dts/mt2701-evb.dts
index 879f1eb..a483798 100644
--- a/arch/arm/boot/dts/mt2701-evb.dts
+++ b/arch/arm/boot/dts/mt2701-evb.dts
@@ -24,6 +24,10 @@
 	};
 };
 
+&auxadc {
+	status = "okay";
+};
+
 &pio {
 	spi_pins_a: spi0 at 0 {
 		pins_spi {
diff --git a/arch/arm/boot/dts/mt2701.dtsi b/arch/arm/boot/dts/mt2701.dtsi
index 1182c43..4f52019 100644
--- a/arch/arm/boot/dts/mt2701.dtsi
+++ b/arch/arm/boot/dts/mt2701.dtsi
@@ -208,6 +208,15 @@
 		      <0 0x10216000 0 0x2000>;
 	};
 
+	auxadc: adc at 11001000 {
+		compatible = "mediatek,mt2701-auxadc";
+		reg = <0 0x11001000 0 0x1000>;
+		clocks = <&pericfg CLK_PERI_AUXADC>;
+		clock-names = "main";
+		#io-channel-cells = <1>;
+		status = "disabled";
+	};
+
 	uart0: serial at 11002000 {
 		compatible = "mediatek,mt2701-uart",
 			     "mediatek,mt6577-uart";
-- 
1.9.1

[PATCH v2 5/6] arm: dts: mt2701: Add ethernet device node.

[Erin Lo]

From: Sean Wang <sean.wang@mediatek.com>

Add ethernet device node for MT2701.

Signed-off-by: Sean Wang <sean.wang@mediatek.com>
Signed-off-by: Erin Lo <erin.lo@mediatek.com>
---
 arch/arm/boot/dts/mt2701-evb.dts | 40 ++++++++++++++++++++++++++++++++++++++++
 arch/arm/boot/dts/mt2701.dtsi    | 22 ++++++++++++++++++++++
 2 files changed, 62 insertions(+)

diff --git a/arch/arm/boot/dts/mt2701-evb.dts b/arch/arm/boot/dts/mt2701-evb.dts
index a483798..40abd3b 100644
--- a/arch/arm/boot/dts/mt2701-evb.dts
+++ b/arch/arm/boot/dts/mt2701-evb.dts
@@ -28,7 +28,47 @@
 	status = "okay";
 };
 
+&eth {
+	mac-address = [00 00 00 00 00 00];
+	status = "okay";
+	pinctrl-names = "default";
+	pinctrl-0 = <&gmac1_pins>;
+	gmac1: mac@1 {
+		compatible = "mediatek,eth-mac";
+		reg = <1>;
+		phy-handle = <&phy5>;
+	};
+
+	mdio-bus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		phy5: ethernet-phy@5 {
+			reg = <5>;
+			phy-mode = "rgmii-rxid";
+		};
+	};
+};
+
 &pio {
+	gmac1_pins: eth@0 {
+		pins_eth {
+			pinmux = <MT2701_PIN_275_MDC__FUNC_MDC>,
+				 <MT2701_PIN_276_MDIO__FUNC_MDIO>,
+				 <MT2701_PIN_262_G2_TXEN__FUNC_G2_TXEN>,
+				 <MT2701_PIN_263_G2_TXD3__FUNC_G2_TXD3>,
+				 <MT2701_PIN_264_G2_TXD2__FUNC_G2_TXD2>,
+				 <MT2701_PIN_265_G2_TXD1__FUNC_G2_TXD1>,
+				 <MT2701_PIN_266_G2_TXD0__FUNC_G2_TXD0>,
+				 <MT2701_PIN_267_G2_TXC__FUNC_G2_TXC>,
+				 <MT2701_PIN_268_G2_RXC__FUNC_G2_RXC>,
+				 <MT2701_PIN_269_G2_RXD0__FUNC_G2_RXD0>,
+				 <MT2701_PIN_270_G2_RXD1__FUNC_G2_RXD1>,
+				 <MT2701_PIN_271_G2_RXD2__FUNC_G2_RXD2>,
+				 <MT2701_PIN_272_G2_RXD3__FUNC_G2_RXD3>,
+				 <MT2701_PIN_274_G2_RXDV__FUNC_G2_RXDV>;
+		};
+	};
+
 	spi_pins_a: spi0@0 {
 		pins_spi {
 			pinmux = <MT2701_PIN_53_SPI0_CSN__FUNC_SPI0_CS>,
diff --git a/arch/arm/boot/dts/mt2701.dtsi b/arch/arm/boot/dts/mt2701.dtsi
index 4f52019..3847f70 100644
--- a/arch/arm/boot/dts/mt2701.dtsi
+++ b/arch/arm/boot/dts/mt2701.dtsi
@@ -381,6 +381,28 @@
 		#clock-cells = <1>;
 	};
 
+	eth: ethernet@1b100000 {
+		compatible = "mediatek,mt7623-eth";
+		reg = <0 0x1b100000 0 0x20000>;
+		interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_LOW>,
+			     <GIC_SPI 199 IRQ_TYPE_LEVEL_LOW>,
+			     <GIC_SPI 198 IRQ_TYPE_LEVEL_LOW>;
+		clocks = <&topckgen CLK_TOP_ETHIF_SEL>,
+			 <&apmixedsys CLK_APMIXED_TRGPLL>,
+			 <&ethsys CLK_ETHSYS_ESW>,
+			 <&ethsys CLK_ETHSYS_GP2>,
+			 <&ethsys CLK_ETHSYS_GP1>;
+		clock-names = "ethif", "trgpll", "esw", "gp2", "gp1";
+		power-domains = <&scpsys MT2701_POWER_DOMAIN_ETH>;
+		resets = <&watchdog MT2701_TOPRGU_ETHDMA_RST>;
+		reset-names = "eth";
+		mediatek,ethsys = <&ethsys>;
+		mediatek,pctl = <&syscfg_pctl_a>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		status = "disabled";
+	};
+
 	bdpsys: syscon@1c000000 {
 		compatible = "mediatek,mt2701-bdpsys", "syscon";
 		reg = <0 0x1c000000 0 0x1000>;
-- 
1.9.1

[PATCH v2 5/6] arm: dts: mt2701: Add ethernet device node.

[Erin Lo]

From: Sean Wang <sean.wang-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org>

Add ethernet device node for MT2701.

Signed-off-by: Sean Wang <sean.wang-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org>
Signed-off-by: Erin Lo <erin.lo-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org>
---
 arch/arm/boot/dts/mt2701-evb.dts | 40 ++++++++++++++++++++++++++++++++++++++++
 arch/arm/boot/dts/mt2701.dtsi    | 22 ++++++++++++++++++++++
 2 files changed, 62 insertions(+)

diff --git a/arch/arm/boot/dts/mt2701-evb.dts b/arch/arm/boot/dts/mt2701-evb.dts
index a483798..40abd3b 100644
--- a/arch/arm/boot/dts/mt2701-evb.dts
+++ b/arch/arm/boot/dts/mt2701-evb.dts
@@ -28,7 +28,47 @@
 	status = "okay";
 };
 
+&eth {
+	mac-address = [00 00 00 00 00 00];
+	status = "okay";
+	pinctrl-names = "default";
+	pinctrl-0 = <&gmac1_pins>;
+	gmac1: mac@1 {
+		compatible = "mediatek,eth-mac";
+		reg = <1>;
+		phy-handle = <&phy5>;
+	};
+
+	mdio-bus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		phy5: ethernet-phy@5 {
+			reg = <5>;
+			phy-mode = "rgmii-rxid";
+		};
+	};
+};
+
 &pio {
+	gmac1_pins: eth@0 {
+		pins_eth {
+			pinmux = <MT2701_PIN_275_MDC__FUNC_MDC>,
+				 <MT2701_PIN_276_MDIO__FUNC_MDIO>,
+				 <MT2701_PIN_262_G2_TXEN__FUNC_G2_TXEN>,
+				 <MT2701_PIN_263_G2_TXD3__FUNC_G2_TXD3>,
+				 <MT2701_PIN_264_G2_TXD2__FUNC_G2_TXD2>,
+				 <MT2701_PIN_265_G2_TXD1__FUNC_G2_TXD1>,
+				 <MT2701_PIN_266_G2_TXD0__FUNC_G2_TXD0>,
+				 <MT2701_PIN_267_G2_TXC__FUNC_G2_TXC>,
+				 <MT2701_PIN_268_G2_RXC__FUNC_G2_RXC>,
+				 <MT2701_PIN_269_G2_RXD0__FUNC_G2_RXD0>,
+				 <MT2701_PIN_270_G2_RXD1__FUNC_G2_RXD1>,
+				 <MT2701_PIN_271_G2_RXD2__FUNC_G2_RXD2>,
+				 <MT2701_PIN_272_G2_RXD3__FUNC_G2_RXD3>,
+				 <MT2701_PIN_274_G2_RXDV__FUNC_G2_RXDV>;
+		};
+	};
+
 	spi_pins_a: spi0@0 {
 		pins_spi {
 			pinmux = <MT2701_PIN_53_SPI0_CSN__FUNC_SPI0_CS>,
diff --git a/arch/arm/boot/dts/mt2701.dtsi b/arch/arm/boot/dts/mt2701.dtsi
index 4f52019..3847f70 100644
--- a/arch/arm/boot/dts/mt2701.dtsi
+++ b/arch/arm/boot/dts/mt2701.dtsi
@@ -381,6 +381,28 @@
 		#clock-cells = <1>;
 	};
 
+	eth: ethernet@1b100000 {
+		compatible = "mediatek,mt7623-eth";
+		reg = <0 0x1b100000 0 0x20000>;
+		interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_LOW>,
+			     <GIC_SPI 199 IRQ_TYPE_LEVEL_LOW>,
+			     <GIC_SPI 198 IRQ_TYPE_LEVEL_LOW>;
+		clocks = <&topckgen CLK_TOP_ETHIF_SEL>,
+			 <&apmixedsys CLK_APMIXED_TRGPLL>,
+			 <&ethsys CLK_ETHSYS_ESW>,
+			 <&ethsys CLK_ETHSYS_GP2>,
+			 <&ethsys CLK_ETHSYS_GP1>;
+		clock-names = "ethif", "trgpll", "esw", "gp2", "gp1";
+		power-domains = <&scpsys MT2701_POWER_DOMAIN_ETH>;
+		resets = <&watchdog MT2701_TOPRGU_ETHDMA_RST>;
+		reset-names = "eth";
+		mediatek,ethsys = <&ethsys>;
+		mediatek,pctl = <&syscfg_pctl_a>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		status = "disabled";
+	};
+
 	bdpsys: syscon@1c000000 {
 		compatible = "mediatek,mt2701-bdpsys", "syscon";
 		reg = <0 0x1c000000 0 0x1000>;
-- 
1.9.1

--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
More majordomo info at  http://vger.kernel.org/majordomo-info.html

[PATCH v2 5/6] arm: dts: mt2701: Add ethernet device node.

[Erin Lo]

From: Sean Wang <sean.wang@mediatek.com>

Add ethernet device node for MT2701.

Signed-off-by: Sean Wang <sean.wang@mediatek.com>
Signed-off-by: Erin Lo <erin.lo@mediatek.com>
---
 arch/arm/boot/dts/mt2701-evb.dts | 40 ++++++++++++++++++++++++++++++++++++++++
 arch/arm/boot/dts/mt2701.dtsi    | 22 ++++++++++++++++++++++
 2 files changed, 62 insertions(+)

diff --git a/arch/arm/boot/dts/mt2701-evb.dts b/arch/arm/boot/dts/mt2701-evb.dts
index a483798..40abd3b 100644
--- a/arch/arm/boot/dts/mt2701-evb.dts
+++ b/arch/arm/boot/dts/mt2701-evb.dts
@@ -28,7 +28,47 @@
 	status = "okay";
 };
 
+&eth {
+	mac-address = [00 00 00 00 00 00];
+	status = "okay";
+	pinctrl-names = "default";
+	pinctrl-0 = <&gmac1_pins>;
+	gmac1: mac at 1 {
+		compatible = "mediatek,eth-mac";
+		reg = <1>;
+		phy-handle = <&phy5>;
+	};
+
+	mdio-bus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		phy5: ethernet-phy at 5 {
+			reg = <5>;
+			phy-mode = "rgmii-rxid";
+		};
+	};
+};
+
 &pio {
+	gmac1_pins: eth at 0 {
+		pins_eth {
+			pinmux = <MT2701_PIN_275_MDC__FUNC_MDC>,
+				 <MT2701_PIN_276_MDIO__FUNC_MDIO>,
+				 <MT2701_PIN_262_G2_TXEN__FUNC_G2_TXEN>,
+				 <MT2701_PIN_263_G2_TXD3__FUNC_G2_TXD3>,
+				 <MT2701_PIN_264_G2_TXD2__FUNC_G2_TXD2>,
+				 <MT2701_PIN_265_G2_TXD1__FUNC_G2_TXD1>,
+				 <MT2701_PIN_266_G2_TXD0__FUNC_G2_TXD0>,
+				 <MT2701_PIN_267_G2_TXC__FUNC_G2_TXC>,
+				 <MT2701_PIN_268_G2_RXC__FUNC_G2_RXC>,
+				 <MT2701_PIN_269_G2_RXD0__FUNC_G2_RXD0>,
+				 <MT2701_PIN_270_G2_RXD1__FUNC_G2_RXD1>,
+				 <MT2701_PIN_271_G2_RXD2__FUNC_G2_RXD2>,
+				 <MT2701_PIN_272_G2_RXD3__FUNC_G2_RXD3>,
+				 <MT2701_PIN_274_G2_RXDV__FUNC_G2_RXDV>;
+		};
+	};
+
 	spi_pins_a: spi0 at 0 {
 		pins_spi {
 			pinmux = <MT2701_PIN_53_SPI0_CSN__FUNC_SPI0_CS>,
diff --git a/arch/arm/boot/dts/mt2701.dtsi b/arch/arm/boot/dts/mt2701.dtsi
index 4f52019..3847f70 100644
--- a/arch/arm/boot/dts/mt2701.dtsi
+++ b/arch/arm/boot/dts/mt2701.dtsi
@@ -381,6 +381,28 @@
 		#clock-cells = <1>;
 	};
 
+	eth: ethernet at 1b100000 {
+		compatible = "mediatek,mt7623-eth";
+		reg = <0 0x1b100000 0 0x20000>;
+		interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_LOW>,
+			     <GIC_SPI 199 IRQ_TYPE_LEVEL_LOW>,
+			     <GIC_SPI 198 IRQ_TYPE_LEVEL_LOW>;
+		clocks = <&topckgen CLK_TOP_ETHIF_SEL>,
+			 <&apmixedsys CLK_APMIXED_TRGPLL>,
+			 <&ethsys CLK_ETHSYS_ESW>,
+			 <&ethsys CLK_ETHSYS_GP2>,
+			 <&ethsys CLK_ETHSYS_GP1>;
+		clock-names = "ethif", "trgpll", "esw", "gp2", "gp1";
+		power-domains = <&scpsys MT2701_POWER_DOMAIN_ETH>;
+		resets = <&watchdog MT2701_TOPRGU_ETHDMA_RST>;
+		reset-names = "eth";
+		mediatek,ethsys = <&ethsys>;
+		mediatek,pctl = <&syscfg_pctl_a>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		status = "disabled";
+	};
+
 	bdpsys: syscon at 1c000000 {
 		compatible = "mediatek,mt2701-bdpsys", "syscon";
 		reg = <0 0x1c000000 0 0x1000>;
-- 
1.9.1

[PATCH v2 6/6] arm: dts: mt2701: Add thermal device node.

[Erin Lo]

From: Dawei Chien <dawei.chien@mediatek.com>

Add thermal controller device nodes for MT2701.

Signed-off-by: Dawei Chien <dawei.chien@mediatek.com>
Signed-off-by: Erin Lo <erin.lo@mediatek.com>
---
 arch/arm/boot/dts/mt2701.dtsi | 43 +++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 43 insertions(+)

diff --git a/arch/arm/boot/dts/mt2701.dtsi b/arch/arm/boot/dts/mt2701.dtsi
index 3847f70..c43d5f8 100644
--- a/arch/arm/boot/dts/mt2701.dtsi
+++ b/arch/arm/boot/dts/mt2701.dtsi
@@ -89,6 +89,36 @@
 		clock-output-names = "rtc32k";
 	};
 
+	thermal-zones {
+		cpu_thermal: cpu_thermal {
+			polling-delay-passive = <1000>; /* milliseconds */
+			polling-delay = <1000>; /* milliseconds */
+
+			thermal-sensors = <&thermal 0>;
+			sustainable-power = <1000>;
+
+			trips {
+				threshold: trip-point@0 {
+					temperature = <68000>;
+					hysteresis = <2000>;
+					type = "passive";
+				};
+
+				target: trip-point@1 {
+					temperature = <85000>;
+					hysteresis = <2000>;
+					type = "passive";
+				};
+
+				cpu_crit: cpu_crit@0 {
+					temperature = <115000>;
+					hysteresis = <2000>;
+					type = "critical";
+				};
+			};
+		};
+	};
+
 	timer {
 		compatible = "arm,armv7-timer";
 		interrupt-parent = <&gic>;
@@ -270,6 +300,19 @@
 		status = "disabled";
 	};
 
+	thermal: thermal@1100b000 {
+		#thermal-sensor-cells = <0>;
+		compatible = "mediatek,mt2701-thermal";
+		reg = <0 0x1100b000 0 0x1000>;
+		interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_LOW>;
+		clocks = <&pericfg CLK_PERI_THERM>, <&pericfg CLK_PERI_AUXADC>;
+		clock-names = "therm", "auxadc";
+		resets = <&pericfg 0x10>;
+		reset-names = "therm";
+		mediatek,auxadc = <&auxadc>;
+		mediatek,apmixedsys = <&apmixedsys>;
+	};
+
 	nandc: nfi@1100d000 {
 		compatible = "mediatek,mt2701-nfc";
 		reg = <0 0x1100d000 0 0x1000>;
-- 
1.9.1

[PATCH v2 6/6] arm: dts: mt2701: Add thermal device node.

[Erin Lo]

From: Dawei Chien <dawei.chien@mediatek.com>

Add thermal controller device nodes for MT2701.

Signed-off-by: Dawei Chien <dawei.chien@mediatek.com>
Signed-off-by: Erin Lo <erin.lo@mediatek.com>
---
 arch/arm/boot/dts/mt2701.dtsi | 43 +++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 43 insertions(+)

diff --git a/arch/arm/boot/dts/mt2701.dtsi b/arch/arm/boot/dts/mt2701.dtsi
index 3847f70..c43d5f8 100644
--- a/arch/arm/boot/dts/mt2701.dtsi
+++ b/arch/arm/boot/dts/mt2701.dtsi
@@ -89,6 +89,36 @@
 		clock-output-names = "rtc32k";
 	};
 
+	thermal-zones {
+		cpu_thermal: cpu_thermal {
+			polling-delay-passive = <1000>; /* milliseconds */
+			polling-delay = <1000>; /* milliseconds */
+
+			thermal-sensors = <&thermal 0>;
+			sustainable-power = <1000>;
+
+			trips {
+				threshold: trip-point@0 {
+					temperature = <68000>;
+					hysteresis = <2000>;
+					type = "passive";
+				};
+
+				target: trip-point@1 {
+					temperature = <85000>;
+					hysteresis = <2000>;
+					type = "passive";
+				};
+
+				cpu_crit: cpu_crit@0 {
+					temperature = <115000>;
+					hysteresis = <2000>;
+					type = "critical";
+				};
+			};
+		};
+	};
+
 	timer {
 		compatible = "arm,armv7-timer";
 		interrupt-parent = <&gic>;
@@ -270,6 +300,19 @@
 		status = "disabled";
 	};
 
+	thermal: thermal@1100b000 {
+		#thermal-sensor-cells = <0>;
+		compatible = "mediatek,mt2701-thermal";
+		reg = <0 0x1100b000 0 0x1000>;
+		interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_LOW>;
+		clocks = <&pericfg CLK_PERI_THERM>, <&pericfg CLK_PERI_AUXADC>;
+		clock-names = "therm", "auxadc";
+		resets = <&pericfg 0x10>;
+		reset-names = "therm";
+		mediatek,auxadc = <&auxadc>;
+		mediatek,apmixedsys = <&apmixedsys>;
+	};
+
 	nandc: nfi@1100d000 {
 		compatible = "mediatek,mt2701-nfc";
 		reg = <0 0x1100d000 0 0x1000>;
-- 
1.9.1

[PATCH v2 6/6] arm: dts: mt2701: Add thermal device node.

[Erin Lo]

From: Dawei Chien <dawei.chien@mediatek.com>

Add thermal controller device nodes for MT2701.

Signed-off-by: Dawei Chien <dawei.chien@mediatek.com>
Signed-off-by: Erin Lo <erin.lo@mediatek.com>
---
 arch/arm/boot/dts/mt2701.dtsi | 43 +++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 43 insertions(+)

diff --git a/arch/arm/boot/dts/mt2701.dtsi b/arch/arm/boot/dts/mt2701.dtsi
index 3847f70..c43d5f8 100644
--- a/arch/arm/boot/dts/mt2701.dtsi
+++ b/arch/arm/boot/dts/mt2701.dtsi
@@ -89,6 +89,36 @@
 		clock-output-names = "rtc32k";
 	};
 
+	thermal-zones {
+		cpu_thermal: cpu_thermal {
+			polling-delay-passive = <1000>; /* milliseconds */
+			polling-delay = <1000>; /* milliseconds */
+
+			thermal-sensors = <&thermal 0>;
+			sustainable-power = <1000>;
+
+			trips {
+				threshold: trip-point at 0 {
+					temperature = <68000>;
+					hysteresis = <2000>;
+					type = "passive";
+				};
+
+				target: trip-point at 1 {
+					temperature = <85000>;
+					hysteresis = <2000>;
+					type = "passive";
+				};
+
+				cpu_crit: cpu_crit at 0 {
+					temperature = <115000>;
+					hysteresis = <2000>;
+					type = "critical";
+				};
+			};
+		};
+	};
+
 	timer {
 		compatible = "arm,armv7-timer";
 		interrupt-parent = <&gic>;
@@ -270,6 +300,19 @@
 		status = "disabled";
 	};
 
+	thermal: thermal at 1100b000 {
+		#thermal-sensor-cells = <0>;
+		compatible = "mediatek,mt2701-thermal";
+		reg = <0 0x1100b000 0 0x1000>;
+		interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_LOW>;
+		clocks = <&pericfg CLK_PERI_THERM>, <&pericfg CLK_PERI_AUXADC>;
+		clock-names = "therm", "auxadc";
+		resets = <&pericfg 0x10>;
+		reset-names = "therm";
+		mediatek,auxadc = <&auxadc>;
+		mediatek,apmixedsys = <&apmixedsys>;
+	};
+
 	nandc: nfi at 1100d000 {
 		compatible = "mediatek,mt2701-nfc";
 		reg = <0 0x1100d000 0 0x1000>;
-- 
1.9.1

Re: [PATCH v2 2/6] arm: dts: mt2701: Add iommu/smi device node

[Matthias Brugger]

Hi Erin,

I just took the patch from Honghui he send in june.
Please see my comment inline.

On 13/01/17 09:42, Erin Lo wrote:
> From: Honghui Zhang <honghui.zhang@mediatek.com>
>
> Add the device node of iommu and smi for MT2701.
>
> Signed-off-by: Honghui Zhang <honghui.zhang@mediatek.com>
> Signed-off-by: Erin Lo <erin.lo@mediatek.com>
> ---
>  arch/arm/boot/dts/mt2701.dtsi | 54 +++++++++++++++++++++++++++++++++++++++++++
>  1 file changed, 54 insertions(+)
>
> diff --git a/arch/arm/boot/dts/mt2701.dtsi b/arch/arm/boot/dts/mt2701.dtsi
> index eb4c6fd..87be52c 100644
> --- a/arch/arm/boot/dts/mt2701.dtsi
> +++ b/arch/arm/boot/dts/mt2701.dtsi
> @@ -17,6 +17,7 @@
>  #include <dt-bindings/interrupt-controller/irq.h>
>  #include <dt-bindings/interrupt-controller/arm-gic.h>
>  #include <dt-bindings/reset/mt2701-resets.h>
> +#include <dt-bindings/memory/mt2701-larb-port.h>
>  #include "skeleton64.dtsi"
>  #include "mt2701-pinfunc.h"
>
> @@ -161,6 +162,16 @@
>  		clock-names = "system-clk", "rtc-clk";
>  	};
>
> +	smi_common: smi@1000c000 {
> +		compatible = "mediatek,mt2701-smi-common";
> +		reg = <0 0x1000c000 0 0x1000>;
> +		clocks = <&infracfg CLK_INFRA_SMI>,
> +			 <&mmsys CLK_MM_SMI_COMMON>,
> +			 <&infracfg CLK_INFRA_SMI>;
> +		clock-names = "apb", "smi", "async";
> +		power-domains = <&scpsys MT2701_POWER_DOMAIN_DISP>;
> +	};
> +
>  	sysirq: interrupt-controller@10200100 {
>  		compatible = "mediatek,mt2701-sysirq",
>  			     "mediatek,mt6577-sysirq";
> @@ -170,6 +181,16 @@
>  		reg = <0 0x10200100 0 0x1c>;
>  	};
>
> +	iommu: mmsys_iommu@10205000 {
> +		compatible = "mediatek,mt2701-m4u";
> +		reg = <0 0x10205000 0 0x1000>;
> +		interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_LOW>;
> +		clocks = <&infracfg CLK_INFRA_M4U>;
> +		clock-names = "bclk";
> +		mediatek,larbs = <&larb0 &larb1 &larb2>;
> +		#iommu-cells = <1>;
> +	};
> +
>  	apmixedsys: syscon@10209000 {
>  		compatible = "mediatek,mt2701-apmixedsys", "syscon";
>  		reg = <0 0x10209000 0 0x1000>;
> @@ -272,18 +293,51 @@
>  		#clock-cells = <1>;
>  	};
>
> +	larb0: larb@14010000 {
> +		compatible = "mediatek,mt2701-smi-larb";
> +		reg = <0 0x14010000 0 0x1000>;
> +		mediatek,smi = <&smi_common>;
> +		mediatek,larbidx = <0>;

Did I miss something? 'mediatek,larbidx' does not sound familiar to me.

Regards,
Matthias

> +		clocks = <&mmsys CLK_MM_SMI_LARB0>,
> +			 <&mmsys CLK_MM_SMI_LARB0>;
> +		clock-names = "apb", "smi";
> +		power-domains = <&scpsys MT2701_POWER_DOMAIN_DISP>;
> +	};
> +
>  	imgsys: syscon@15000000 {
>  		compatible = "mediatek,mt2701-imgsys", "syscon";
>  		reg = <0 0x15000000 0 0x1000>;
>  		#clock-cells = <1>;
>  	};
>
> +	larb2: larb@15001000 {
> +		compatible = "mediatek,mt2701-smi-larb";
> +		reg = <0 0x15001000 0 0x1000>;
> +		mediatek,smi = <&smi_common>;
> +		mediatek,larbidx = <2>;
> +		clocks = <&imgsys CLK_IMG_SMI_COMM>,
> +			 <&imgsys CLK_IMG_SMI_COMM>;
> +		clock-names = "apb", "smi";
> +		power-domains = <&scpsys MT2701_POWER_DOMAIN_ISP>;
> +	};
> +
>  	vdecsys: syscon@16000000 {
>  		compatible = "mediatek,mt2701-vdecsys", "syscon";
>  		reg = <0 0x16000000 0 0x1000>;
>  		#clock-cells = <1>;
>  	};
>
> +	larb1: larb@16010000 {
> +		compatible = "mediatek,mt2701-smi-larb";
> +		reg = <0 0x16010000 0 0x1000>;
> +		mediatek,smi = <&smi_common>;
> +		mediatek,larbidx = <1>;
> +		clocks = <&vdecsys CLK_VDEC_CKGEN>,
> +			 <&vdecsys CLK_VDEC_LARB>;
> +		clock-names = "apb", "smi";
> +		power-domains = <&scpsys MT2701_POWER_DOMAIN_VDEC>;
> +	};
> +
>  	hifsys: syscon@1a000000 {
>  		compatible = "mediatek,mt2701-hifsys", "syscon";
>  		reg = <0 0x1a000000 0 0x1000>;
>

[PATCH v2 2/6] arm: dts: mt2701: Add iommu/smi device node

[Matthias Brugger]

Hi Erin,

I just took the patch from Honghui he send in june.
Please see my comment inline.

On 13/01/17 09:42, Erin Lo wrote:
> From: Honghui Zhang <honghui.zhang@mediatek.com>
>
> Add the device node of iommu and smi for MT2701.
>
> Signed-off-by: Honghui Zhang <honghui.zhang@mediatek.com>
> Signed-off-by: Erin Lo <erin.lo@mediatek.com>
> ---
>  arch/arm/boot/dts/mt2701.dtsi | 54 +++++++++++++++++++++++++++++++++++++++++++
>  1 file changed, 54 insertions(+)
>
> diff --git a/arch/arm/boot/dts/mt2701.dtsi b/arch/arm/boot/dts/mt2701.dtsi
> index eb4c6fd..87be52c 100644
> --- a/arch/arm/boot/dts/mt2701.dtsi
> +++ b/arch/arm/boot/dts/mt2701.dtsi
> @@ -17,6 +17,7 @@
>  #include <dt-bindings/interrupt-controller/irq.h>
>  #include <dt-bindings/interrupt-controller/arm-gic.h>
>  #include <dt-bindings/reset/mt2701-resets.h>
> +#include <dt-bindings/memory/mt2701-larb-port.h>
>  #include "skeleton64.dtsi"
>  #include "mt2701-pinfunc.h"
>
> @@ -161,6 +162,16 @@
>  		clock-names = "system-clk", "rtc-clk";
>  	};
>
> +	smi_common: smi at 1000c000 {
> +		compatible = "mediatek,mt2701-smi-common";
> +		reg = <0 0x1000c000 0 0x1000>;
> +		clocks = <&infracfg CLK_INFRA_SMI>,
> +			 <&mmsys CLK_MM_SMI_COMMON>,
> +			 <&infracfg CLK_INFRA_SMI>;
> +		clock-names = "apb", "smi", "async";
> +		power-domains = <&scpsys MT2701_POWER_DOMAIN_DISP>;
> +	};
> +
>  	sysirq: interrupt-controller at 10200100 {
>  		compatible = "mediatek,mt2701-sysirq",
>  			     "mediatek,mt6577-sysirq";
> @@ -170,6 +181,16 @@
>  		reg = <0 0x10200100 0 0x1c>;
>  	};
>
> +	iommu: mmsys_iommu at 10205000 {
> +		compatible = "mediatek,mt2701-m4u";
> +		reg = <0 0x10205000 0 0x1000>;
> +		interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_LOW>;
> +		clocks = <&infracfg CLK_INFRA_M4U>;
> +		clock-names = "bclk";
> +		mediatek,larbs = <&larb0 &larb1 &larb2>;
> +		#iommu-cells = <1>;
> +	};
> +
>  	apmixedsys: syscon at 10209000 {
>  		compatible = "mediatek,mt2701-apmixedsys", "syscon";
>  		reg = <0 0x10209000 0 0x1000>;
> @@ -272,18 +293,51 @@
>  		#clock-cells = <1>;
>  	};
>
> +	larb0: larb at 14010000 {
> +		compatible = "mediatek,mt2701-smi-larb";
> +		reg = <0 0x14010000 0 0x1000>;
> +		mediatek,smi = <&smi_common>;
> +		mediatek,larbidx = <0>;

Did I miss something? 'mediatek,larbidx' does not sound familiar to me.

Regards,
Matthias

> +		clocks = <&mmsys CLK_MM_SMI_LARB0>,
> +			 <&mmsys CLK_MM_SMI_LARB0>;
> +		clock-names = "apb", "smi";
> +		power-domains = <&scpsys MT2701_POWER_DOMAIN_DISP>;
> +	};
> +
>  	imgsys: syscon at 15000000 {
>  		compatible = "mediatek,mt2701-imgsys", "syscon";
>  		reg = <0 0x15000000 0 0x1000>;
>  		#clock-cells = <1>;
>  	};
>
> +	larb2: larb at 15001000 {
> +		compatible = "mediatek,mt2701-smi-larb";
> +		reg = <0 0x15001000 0 0x1000>;
> +		mediatek,smi = <&smi_common>;
> +		mediatek,larbidx = <2>;
> +		clocks = <&imgsys CLK_IMG_SMI_COMM>,
> +			 <&imgsys CLK_IMG_SMI_COMM>;
> +		clock-names = "apb", "smi";
> +		power-domains = <&scpsys MT2701_POWER_DOMAIN_ISP>;
> +	};
> +
>  	vdecsys: syscon at 16000000 {
>  		compatible = "mediatek,mt2701-vdecsys", "syscon";
>  		reg = <0 0x16000000 0 0x1000>;
>  		#clock-cells = <1>;
>  	};
>
> +	larb1: larb at 16010000 {
> +		compatible = "mediatek,mt2701-smi-larb";
> +		reg = <0 0x16010000 0 0x1000>;
> +		mediatek,smi = <&smi_common>;
> +		mediatek,larbidx = <1>;
> +		clocks = <&vdecsys CLK_VDEC_CKGEN>,
> +			 <&vdecsys CLK_VDEC_LARB>;
> +		clock-names = "apb", "smi";
> +		power-domains = <&scpsys MT2701_POWER_DOMAIN_VDEC>;
> +	};
> +
>  	hifsys: syscon at 1a000000 {
>  		compatible = "mediatek,mt2701-hifsys", "syscon";
>  		reg = <0 0x1a000000 0 0x1000>;
>

Re: [PATCH v2 6/6] arm: dts: mt2701: Add thermal device node.

[Matthias Brugger]

On 13/01/17 09:42, Erin Lo wrote:
> From: Dawei Chien <dawei.chien@mediatek.com>
>
> Add thermal controller device nodes for MT2701.
>
> Signed-off-by: Dawei Chien <dawei.chien@mediatek.com>
> Signed-off-by: Erin Lo <erin.lo@mediatek.com>
> ---
>  arch/arm/boot/dts/mt2701.dtsi | 43 +++++++++++++++++++++++++++++++++++++++++++
>  1 file changed, 43 insertions(+)
>
> diff --git a/arch/arm/boot/dts/mt2701.dtsi b/arch/arm/boot/dts/mt2701.dtsi
> index 3847f70..c43d5f8 100644
> --- a/arch/arm/boot/dts/mt2701.dtsi
> +++ b/arch/arm/boot/dts/mt2701.dtsi
> @@ -89,6 +89,36 @@
>  		clock-output-names = "rtc32k";
>  	};
>
> +	thermal-zones {
> +		cpu_thermal: cpu_thermal {
> +			polling-delay-passive = <1000>; /* milliseconds */
> +			polling-delay = <1000>; /* milliseconds */
> +
> +			thermal-sensors = <&thermal 0>;
> +			sustainable-power = <1000>;
> +
> +			trips {
> +				threshold: trip-point@0 {
> +					temperature = <68000>;
> +					hysteresis = <2000>;
> +					type = "passive";
> +				};
> +
> +				target: trip-point@1 {
> +					temperature = <85000>;
> +					hysteresis = <2000>;
> +					type = "passive";
> +				};
> +
> +				cpu_crit: cpu_crit@0 {
> +					temperature = <115000>;
> +					hysteresis = <2000>;
> +					type = "critical";
> +				};
> +			};
> +		};
> +	};
> +
>  	timer {
>  		compatible = "arm,armv7-timer";
>  		interrupt-parent = <&gic>;
> @@ -270,6 +300,19 @@
>  		status = "disabled";
>  	};
>
> +	thermal: thermal@1100b000 {
> +		#thermal-sensor-cells = <0>;
> +		compatible = "mediatek,mt2701-thermal";
> +		reg = <0 0x1100b000 0 0x1000>;
> +		interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_LOW>;
> +		clocks = <&pericfg CLK_PERI_THERM>, <&pericfg CLK_PERI_AUXADC>;
> +		clock-names = "therm", "auxadc";
> +		resets = <&pericfg 0x10>;

should be MT2701_PERI_AUXADC_SW_RST, right?

> +		reset-names = "therm";
> +		mediatek,auxadc = <&auxadc>;
> +		mediatek,apmixedsys = <&apmixedsys>;
> +	};
> +
>  	nandc: nfi@1100d000 {
>  		compatible = "mediatek,mt2701-nfc";
>  		reg = <0 0x1100d000 0 0x1000>;
>

[PATCH v2 6/6] arm: dts: mt2701: Add thermal device node.

[Matthias Brugger]

On 13/01/17 09:42, Erin Lo wrote:
> From: Dawei Chien <dawei.chien@mediatek.com>
>
> Add thermal controller device nodes for MT2701.
>
> Signed-off-by: Dawei Chien <dawei.chien@mediatek.com>
> Signed-off-by: Erin Lo <erin.lo@mediatek.com>
> ---
>  arch/arm/boot/dts/mt2701.dtsi | 43 +++++++++++++++++++++++++++++++++++++++++++
>  1 file changed, 43 insertions(+)
>
> diff --git a/arch/arm/boot/dts/mt2701.dtsi b/arch/arm/boot/dts/mt2701.dtsi
> index 3847f70..c43d5f8 100644
> --- a/arch/arm/boot/dts/mt2701.dtsi
> +++ b/arch/arm/boot/dts/mt2701.dtsi
> @@ -89,6 +89,36 @@
>  		clock-output-names = "rtc32k";
>  	};
>
> +	thermal-zones {
> +		cpu_thermal: cpu_thermal {
> +			polling-delay-passive = <1000>; /* milliseconds */
> +			polling-delay = <1000>; /* milliseconds */
> +
> +			thermal-sensors = <&thermal 0>;
> +			sustainable-power = <1000>;
> +
> +			trips {
> +				threshold: trip-point at 0 {
> +					temperature = <68000>;
> +					hysteresis = <2000>;
> +					type = "passive";
> +				};
> +
> +				target: trip-point at 1 {
> +					temperature = <85000>;
> +					hysteresis = <2000>;
> +					type = "passive";
> +				};
> +
> +				cpu_crit: cpu_crit at 0 {
> +					temperature = <115000>;
> +					hysteresis = <2000>;
> +					type = "critical";
> +				};
> +			};
> +		};
> +	};
> +
>  	timer {
>  		compatible = "arm,armv7-timer";
>  		interrupt-parent = <&gic>;
> @@ -270,6 +300,19 @@
>  		status = "disabled";
>  	};
>
> +	thermal: thermal at 1100b000 {
> +		#thermal-sensor-cells = <0>;
> +		compatible = "mediatek,mt2701-thermal";
> +		reg = <0 0x1100b000 0 0x1000>;
> +		interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_LOW>;
> +		clocks = <&pericfg CLK_PERI_THERM>, <&pericfg CLK_PERI_AUXADC>;
> +		clock-names = "therm", "auxadc";
> +		resets = <&pericfg 0x10>;

should be MT2701_PERI_AUXADC_SW_RST, right?

> +		reset-names = "therm";
> +		mediatek,auxadc = <&auxadc>;
> +		mediatek,apmixedsys = <&apmixedsys>;
> +	};
> +
>  	nandc: nfi at 1100d000 {
>  		compatible = "mediatek,mt2701-nfc";
>  		reg = <0 0x1100d000 0 0x1000>;
>

Re: [PATCH v2 1/6] arm: dts: mt2701: Add spi device node

[Matthias Brugger]

On 13/01/17 09:42, Erin Lo wrote:
> From: Leilk Liu <leilk.liu@mediatek.com>
>
> Add spi device node for MT2701.
>
> Signed-off-by: Leilk Liu <leilk.liu@mediatek.com>
> Signed-off-by: Erin Lo <erin.lo@mediatek.com>
> ---
>  arch/arm/boot/dts/mt2701-evb.dts | 50 ++++++++++++++++++++++++++++++++++++++++
>  arch/arm/boot/dts/mt2701.dtsi    | 39 +++++++++++++++++++++++++++++++
>  2 files changed, 89 insertions(+)
>

Applied to v4.10-next/dts32

> diff --git a/arch/arm/boot/dts/mt2701-evb.dts b/arch/arm/boot/dts/mt2701-evb.dts
> index 082ca88..879f1eb 100644
> --- a/arch/arm/boot/dts/mt2701-evb.dts
> +++ b/arch/arm/boot/dts/mt2701-evb.dts
> @@ -24,6 +24,56 @@
>  	};
>  };
>
> +&pio {
> +	spi_pins_a: spi0@0 {
> +		pins_spi {
> +			pinmux = <MT2701_PIN_53_SPI0_CSN__FUNC_SPI0_CS>,
> +				 <MT2701_PIN_54_SPI0_CK__FUNC_SPI0_CK>,
> +				 <MT2701_PIN_55_SPI0_MI__FUNC_SPI0_MI>,
> +				 <MT2701_PIN_56_SPI0_MO__FUNC_SPI0_MO>;
> +			bias-disable;
> +		};
> +	};
> +
> +	spi_pins_b: spi1@0 {
> +		pins_spi {
> +			pinmux = <MT2701_PIN_7_SPI1_CSN__FUNC_SPI1_CS>,
> +				 <MT2701_PIN_8_SPI1_MI__FUNC_SPI1_MI>,
> +				 <MT2701_PIN_9_SPI1_MO__FUNC_SPI1_MO>,
> +				 <MT2701_PIN_199_SPI1_CLK__FUNC_SPI1_CK>;
> +			bias-disable;
> +		};
> +	};
> +
> +	spi_pins_c: spi2@0 {
> +		pins_spi {
> +			pinmux = <MT2701_PIN_101_SPI2_CSN__FUNC_SPI2_CS>,
> +				 <MT2701_PIN_102_SPI2_MI__FUNC_SPI2_MI>,
> +				 <MT2701_PIN_103_SPI2_MO__FUNC_SPI2_MO>,
> +				 <MT2701_PIN_104_SPI2_CLK__FUNC_SPI2_CK>;
> +			bias-disable;
> +		};
> +	};
> +};
> +
> +&spi0 {
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&spi_pins_a>;
> +	status = "disabled";
> +};
> +
> +&spi1 {
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&spi_pins_b>;
> +	status = "disabled";
> +};
> +
> +&spi2 {
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&spi_pins_c>;
> +	status = "disabled";
> +};
> +
>  &uart0 {
>  	status = "okay";
>  };
> diff --git a/arch/arm/boot/dts/mt2701.dtsi b/arch/arm/boot/dts/mt2701.dtsi
> index bdf8954..eb4c6fd 100644
> --- a/arch/arm/boot/dts/mt2701.dtsi
> +++ b/arch/arm/boot/dts/mt2701.dtsi
> @@ -227,6 +227,45 @@
>  		status = "disabled";
>  	};
>
> +	spi0: spi@1100a000 {
> +		compatible = "mediatek,mt2701-spi";
> +		#address-cells = <1>;
> +		#size-cells = <0>;
> +		reg = <0 0x1100a000 0 0x100>;
> +		interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_LOW>;
> +		clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
> +			 <&topckgen CLK_TOP_SPI0_SEL>,
> +			 <&pericfg CLK_PERI_SPI0>;
> +		clock-names = "parent-clk", "sel-clk", "spi-clk";
> +		status = "disabled";
> +	};
> +
> +	spi1: spi@11016000 {
> +		compatible = "mediatek,mt2701-spi";
> +		#address-cells = <1>;
> +		#size-cells = <0>;
> +		reg = <0 0x11016000 0 0x100>;
> +		interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_LOW>;
> +		clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
> +			 <&topckgen CLK_TOP_SPI1_SEL>,
> +			 <&pericfg CLK_PERI_SPI1>;
> +		clock-names = "parent-clk", "sel-clk", "spi-clk";
> +		status = "disabled";
> +	};
> +
> +	spi2: spi@11017000 {
> +		compatible = "mediatek,mt2701-spi";
> +		#address-cells = <1>;
> +		#size-cells = <0>;
> +		reg = <0 0x11017000 0 0x1000>;
> +		interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_LOW>;
> +		clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
> +			 <&topckgen CLK_TOP_SPI2_SEL>,
> +			 <&pericfg CLK_PERI_SPI2>;
> +		clock-names = "parent-clk", "sel-clk", "spi-clk";
> +		status = "disabled";
> +	};
> +
>  	mmsys: syscon@14000000 {
>  		compatible = "mediatek,mt2701-mmsys", "syscon";
>  		reg = <0 0x14000000 0 0x1000>;
>

Re: [PATCH v2 1/6] arm: dts: mt2701: Add spi device node

[Matthias Brugger]

On 13/01/17 09:42, Erin Lo wrote:
> From: Leilk Liu <leilk.liu-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org>
>
> Add spi device node for MT2701.
>
> Signed-off-by: Leilk Liu <leilk.liu-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org>
> Signed-off-by: Erin Lo <erin.lo-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org>
> ---
>  arch/arm/boot/dts/mt2701-evb.dts | 50 ++++++++++++++++++++++++++++++++++++++++
>  arch/arm/boot/dts/mt2701.dtsi    | 39 +++++++++++++++++++++++++++++++
>  2 files changed, 89 insertions(+)
>

Applied to v4.10-next/dts32

> diff --git a/arch/arm/boot/dts/mt2701-evb.dts b/arch/arm/boot/dts/mt2701-evb.dts
> index 082ca88..879f1eb 100644
> --- a/arch/arm/boot/dts/mt2701-evb.dts
> +++ b/arch/arm/boot/dts/mt2701-evb.dts
> @@ -24,6 +24,56 @@
>  	};
>  };
>
> +&pio {
> +	spi_pins_a: spi0@0 {
> +		pins_spi {
> +			pinmux = <MT2701_PIN_53_SPI0_CSN__FUNC_SPI0_CS>,
> +				 <MT2701_PIN_54_SPI0_CK__FUNC_SPI0_CK>,
> +				 <MT2701_PIN_55_SPI0_MI__FUNC_SPI0_MI>,
> +				 <MT2701_PIN_56_SPI0_MO__FUNC_SPI0_MO>;
> +			bias-disable;
> +		};
> +	};
> +
> +	spi_pins_b: spi1@0 {
> +		pins_spi {
> +			pinmux = <MT2701_PIN_7_SPI1_CSN__FUNC_SPI1_CS>,
> +				 <MT2701_PIN_8_SPI1_MI__FUNC_SPI1_MI>,
> +				 <MT2701_PIN_9_SPI1_MO__FUNC_SPI1_MO>,
> +				 <MT2701_PIN_199_SPI1_CLK__FUNC_SPI1_CK>;
> +			bias-disable;
> +		};
> +	};
> +
> +	spi_pins_c: spi2@0 {
> +		pins_spi {
> +			pinmux = <MT2701_PIN_101_SPI2_CSN__FUNC_SPI2_CS>,
> +				 <MT2701_PIN_102_SPI2_MI__FUNC_SPI2_MI>,
> +				 <MT2701_PIN_103_SPI2_MO__FUNC_SPI2_MO>,
> +				 <MT2701_PIN_104_SPI2_CLK__FUNC_SPI2_CK>;
> +			bias-disable;
> +		};
> +	};
> +};
> +
> +&spi0 {
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&spi_pins_a>;
> +	status = "disabled";
> +};
> +
> +&spi1 {
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&spi_pins_b>;
> +	status = "disabled";
> +};
> +
> +&spi2 {
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&spi_pins_c>;
> +	status = "disabled";
> +};
> +
>  &uart0 {
>  	status = "okay";
>  };
> diff --git a/arch/arm/boot/dts/mt2701.dtsi b/arch/arm/boot/dts/mt2701.dtsi
> index bdf8954..eb4c6fd 100644
> --- a/arch/arm/boot/dts/mt2701.dtsi
> +++ b/arch/arm/boot/dts/mt2701.dtsi
> @@ -227,6 +227,45 @@
>  		status = "disabled";
>  	};
>
> +	spi0: spi@1100a000 {
> +		compatible = "mediatek,mt2701-spi";
> +		#address-cells = <1>;
> +		#size-cells = <0>;
> +		reg = <0 0x1100a000 0 0x100>;
> +		interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_LOW>;
> +		clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
> +			 <&topckgen CLK_TOP_SPI0_SEL>,
> +			 <&pericfg CLK_PERI_SPI0>;
> +		clock-names = "parent-clk", "sel-clk", "spi-clk";
> +		status = "disabled";
> +	};
> +
> +	spi1: spi@11016000 {
> +		compatible = "mediatek,mt2701-spi";
> +		#address-cells = <1>;
> +		#size-cells = <0>;
> +		reg = <0 0x11016000 0 0x100>;
> +		interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_LOW>;
> +		clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
> +			 <&topckgen CLK_TOP_SPI1_SEL>,
> +			 <&pericfg CLK_PERI_SPI1>;
> +		clock-names = "parent-clk", "sel-clk", "spi-clk";
> +		status = "disabled";
> +	};
> +
> +	spi2: spi@11017000 {
> +		compatible = "mediatek,mt2701-spi";
> +		#address-cells = <1>;
> +		#size-cells = <0>;
> +		reg = <0 0x11017000 0 0x1000>;
> +		interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_LOW>;
> +		clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
> +			 <&topckgen CLK_TOP_SPI2_SEL>,
> +			 <&pericfg CLK_PERI_SPI2>;
> +		clock-names = "parent-clk", "sel-clk", "spi-clk";
> +		status = "disabled";
> +	};
> +
>  	mmsys: syscon@14000000 {
>  		compatible = "mediatek,mt2701-mmsys", "syscon";
>  		reg = <0 0x14000000 0 0x1000>;
>
--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
More majordomo info at  http://vger.kernel.org/majordomo-info.html

[PATCH v2 1/6] arm: dts: mt2701: Add spi device node

[Matthias Brugger]

On 13/01/17 09:42, Erin Lo wrote:
> From: Leilk Liu <leilk.liu@mediatek.com>
>
> Add spi device node for MT2701.
>
> Signed-off-by: Leilk Liu <leilk.liu@mediatek.com>
> Signed-off-by: Erin Lo <erin.lo@mediatek.com>
> ---
>  arch/arm/boot/dts/mt2701-evb.dts | 50 ++++++++++++++++++++++++++++++++++++++++
>  arch/arm/boot/dts/mt2701.dtsi    | 39 +++++++++++++++++++++++++++++++
>  2 files changed, 89 insertions(+)
>

Applied to v4.10-next/dts32

> diff --git a/arch/arm/boot/dts/mt2701-evb.dts b/arch/arm/boot/dts/mt2701-evb.dts
> index 082ca88..879f1eb 100644
> --- a/arch/arm/boot/dts/mt2701-evb.dts
> +++ b/arch/arm/boot/dts/mt2701-evb.dts
> @@ -24,6 +24,56 @@
>  	};
>  };
>
> +&pio {
> +	spi_pins_a: spi0 at 0 {
> +		pins_spi {
> +			pinmux = <MT2701_PIN_53_SPI0_CSN__FUNC_SPI0_CS>,
> +				 <MT2701_PIN_54_SPI0_CK__FUNC_SPI0_CK>,
> +				 <MT2701_PIN_55_SPI0_MI__FUNC_SPI0_MI>,
> +				 <MT2701_PIN_56_SPI0_MO__FUNC_SPI0_MO>;
> +			bias-disable;
> +		};
> +	};
> +
> +	spi_pins_b: spi1 at 0 {
> +		pins_spi {
> +			pinmux = <MT2701_PIN_7_SPI1_CSN__FUNC_SPI1_CS>,
> +				 <MT2701_PIN_8_SPI1_MI__FUNC_SPI1_MI>,
> +				 <MT2701_PIN_9_SPI1_MO__FUNC_SPI1_MO>,
> +				 <MT2701_PIN_199_SPI1_CLK__FUNC_SPI1_CK>;
> +			bias-disable;
> +		};
> +	};
> +
> +	spi_pins_c: spi2 at 0 {
> +		pins_spi {
> +			pinmux = <MT2701_PIN_101_SPI2_CSN__FUNC_SPI2_CS>,
> +				 <MT2701_PIN_102_SPI2_MI__FUNC_SPI2_MI>,
> +				 <MT2701_PIN_103_SPI2_MO__FUNC_SPI2_MO>,
> +				 <MT2701_PIN_104_SPI2_CLK__FUNC_SPI2_CK>;
> +			bias-disable;
> +		};
> +	};
> +};
> +
> +&spi0 {
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&spi_pins_a>;
> +	status = "disabled";
> +};
> +
> +&spi1 {
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&spi_pins_b>;
> +	status = "disabled";
> +};
> +
> +&spi2 {
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&spi_pins_c>;
> +	status = "disabled";
> +};
> +
>  &uart0 {
>  	status = "okay";
>  };
> diff --git a/arch/arm/boot/dts/mt2701.dtsi b/arch/arm/boot/dts/mt2701.dtsi
> index bdf8954..eb4c6fd 100644
> --- a/arch/arm/boot/dts/mt2701.dtsi
> +++ b/arch/arm/boot/dts/mt2701.dtsi
> @@ -227,6 +227,45 @@
>  		status = "disabled";
>  	};
>
> +	spi0: spi at 1100a000 {
> +		compatible = "mediatek,mt2701-spi";
> +		#address-cells = <1>;
> +		#size-cells = <0>;
> +		reg = <0 0x1100a000 0 0x100>;
> +		interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_LOW>;
> +		clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
> +			 <&topckgen CLK_TOP_SPI0_SEL>,
> +			 <&pericfg CLK_PERI_SPI0>;
> +		clock-names = "parent-clk", "sel-clk", "spi-clk";
> +		status = "disabled";
> +	};
> +
> +	spi1: spi at 11016000 {
> +		compatible = "mediatek,mt2701-spi";
> +		#address-cells = <1>;
> +		#size-cells = <0>;
> +		reg = <0 0x11016000 0 0x100>;
> +		interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_LOW>;
> +		clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
> +			 <&topckgen CLK_TOP_SPI1_SEL>,
> +			 <&pericfg CLK_PERI_SPI1>;
> +		clock-names = "parent-clk", "sel-clk", "spi-clk";
> +		status = "disabled";
> +	};
> +
> +	spi2: spi at 11017000 {
> +		compatible = "mediatek,mt2701-spi";
> +		#address-cells = <1>;
> +		#size-cells = <0>;
> +		reg = <0 0x11017000 0 0x1000>;
> +		interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_LOW>;
> +		clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
> +			 <&topckgen CLK_TOP_SPI2_SEL>,
> +			 <&pericfg CLK_PERI_SPI2>;
> +		clock-names = "parent-clk", "sel-clk", "spi-clk";
> +		status = "disabled";
> +	};
> +
>  	mmsys: syscon at 14000000 {
>  		compatible = "mediatek,mt2701-mmsys", "syscon";
>  		reg = <0 0x14000000 0 0x1000>;
>

Re: [PATCH v2 3/6] arm: dts: mt2701: Add nand device node

[Matthias Brugger]

On 13/01/17 09:42, Erin Lo wrote:
> From: Xiaolei Li <xiaolei.li@mediatek.com>
>
> Add mt2701 nand device node, include nfi and bch ecc.
>
> Signed-off-by: Xiaolei Li <xiaolei.li@mediatek.com>
> Signed-off-by: Erin Lo <erin.lo@mediatek.com>
> ---
>  arch/arm/boot/dts/mt2701.dtsi | 22 ++++++++++++++++++++++
>  1 file changed, 22 insertions(+)
>

Applied to v4.10-next/dts32

> diff --git a/arch/arm/boot/dts/mt2701.dtsi b/arch/arm/boot/dts/mt2701.dtsi
> index 87be52c..1182c43 100644
> --- a/arch/arm/boot/dts/mt2701.dtsi
> +++ b/arch/arm/boot/dts/mt2701.dtsi
> @@ -261,6 +261,28 @@
>  		status = "disabled";
>  	};
>
> +	nandc: nfi@1100d000 {
> +		compatible = "mediatek,mt2701-nfc";
> +		reg = <0 0x1100d000 0 0x1000>;
> +		interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_LOW>;
> +		clocks = <&pericfg CLK_PERI_NFI>,
> +			 <&pericfg CLK_PERI_NFI_PAD>;
> +		clock-names = "nfi_clk", "pad_clk";
> +		status = "disabled";
> +		ecc-engine = <&bch>;
> +		#address-cells = <1>;
> +		#size-cells = <0>;
> +	};
> +
> +	bch: ecc@1100e000 {
> +		compatible = "mediatek,mt2701-ecc";
> +		reg = <0 0x1100e000 0 0x1000>;
> +		interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_LOW>;
> +		clocks = <&pericfg CLK_PERI_NFI_ECC>;
> +		clock-names = "nfiecc_clk";
> +		status = "disabled";
> +	};
> +
>  	spi1: spi@11016000 {
>  		compatible = "mediatek,mt2701-spi";
>  		#address-cells = <1>;
>

[PATCH v2 3/6] arm: dts: mt2701: Add nand device node

[Matthias Brugger]

On 13/01/17 09:42, Erin Lo wrote:
> From: Xiaolei Li <xiaolei.li@mediatek.com>
>
> Add mt2701 nand device node, include nfi and bch ecc.
>
> Signed-off-by: Xiaolei Li <xiaolei.li@mediatek.com>
> Signed-off-by: Erin Lo <erin.lo@mediatek.com>
> ---
>  arch/arm/boot/dts/mt2701.dtsi | 22 ++++++++++++++++++++++
>  1 file changed, 22 insertions(+)
>

Applied to v4.10-next/dts32

> diff --git a/arch/arm/boot/dts/mt2701.dtsi b/arch/arm/boot/dts/mt2701.dtsi
> index 87be52c..1182c43 100644
> --- a/arch/arm/boot/dts/mt2701.dtsi
> +++ b/arch/arm/boot/dts/mt2701.dtsi
> @@ -261,6 +261,28 @@
>  		status = "disabled";
>  	};
>
> +	nandc: nfi at 1100d000 {
> +		compatible = "mediatek,mt2701-nfc";
> +		reg = <0 0x1100d000 0 0x1000>;
> +		interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_LOW>;
> +		clocks = <&pericfg CLK_PERI_NFI>,
> +			 <&pericfg CLK_PERI_NFI_PAD>;
> +		clock-names = "nfi_clk", "pad_clk";
> +		status = "disabled";
> +		ecc-engine = <&bch>;
> +		#address-cells = <1>;
> +		#size-cells = <0>;
> +	};
> +
> +	bch: ecc at 1100e000 {
> +		compatible = "mediatek,mt2701-ecc";
> +		reg = <0 0x1100e000 0 0x1000>;
> +		interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_LOW>;
> +		clocks = <&pericfg CLK_PERI_NFI_ECC>;
> +		clock-names = "nfiecc_clk";
> +		status = "disabled";
> +	};
> +
>  	spi1: spi at 11016000 {
>  		compatible = "mediatek,mt2701-spi";
>  		#address-cells = <1>;
>

Re: [PATCH v2 4/6] arm: dts: mt2701: Add auxadc device node.

[Matthias Brugger]

On 13/01/17 09:42, Erin Lo wrote:
> From: Zhiyong Tao <zhiyong.tao@mediatek.com>
>
> Add auxadc device node for MT2701.
>
> Signed-off-by: Zhiyong Tao <zhiyong.tao@mediatek.com>
> Signed-off-by: Erin Lo <erin.lo@mediatek.com>
> ---
>  arch/arm/boot/dts/mt2701-evb.dts | 4 ++++
>  arch/arm/boot/dts/mt2701.dtsi    | 9 +++++++++
>  2 files changed, 13 insertions(+)
>

Applied to v4.10-next/dts32

> diff --git a/arch/arm/boot/dts/mt2701-evb.dts b/arch/arm/boot/dts/mt2701-evb.dts
> index 879f1eb..a483798 100644
> --- a/arch/arm/boot/dts/mt2701-evb.dts
> +++ b/arch/arm/boot/dts/mt2701-evb.dts
> @@ -24,6 +24,10 @@
>  	};
>  };
>
> +&auxadc {
> +	status = "okay";
> +};
> +
>  &pio {
>  	spi_pins_a: spi0@0 {
>  		pins_spi {
> diff --git a/arch/arm/boot/dts/mt2701.dtsi b/arch/arm/boot/dts/mt2701.dtsi
> index 1182c43..4f52019 100644
> --- a/arch/arm/boot/dts/mt2701.dtsi
> +++ b/arch/arm/boot/dts/mt2701.dtsi
> @@ -208,6 +208,15 @@
>  		      <0 0x10216000 0 0x2000>;
>  	};
>
> +	auxadc: adc@11001000 {
> +		compatible = "mediatek,mt2701-auxadc";
> +		reg = <0 0x11001000 0 0x1000>;
> +		clocks = <&pericfg CLK_PERI_AUXADC>;
> +		clock-names = "main";
> +		#io-channel-cells = <1>;
> +		status = "disabled";
> +	};
> +
>  	uart0: serial@11002000 {
>  		compatible = "mediatek,mt2701-uart",
>  			     "mediatek,mt6577-uart";
>

[PATCH v2 4/6] arm: dts: mt2701: Add auxadc device node.

[Matthias Brugger]

On 13/01/17 09:42, Erin Lo wrote:
> From: Zhiyong Tao <zhiyong.tao@mediatek.com>
>
> Add auxadc device node for MT2701.
>
> Signed-off-by: Zhiyong Tao <zhiyong.tao@mediatek.com>
> Signed-off-by: Erin Lo <erin.lo@mediatek.com>
> ---
>  arch/arm/boot/dts/mt2701-evb.dts | 4 ++++
>  arch/arm/boot/dts/mt2701.dtsi    | 9 +++++++++
>  2 files changed, 13 insertions(+)
>

Applied to v4.10-next/dts32

> diff --git a/arch/arm/boot/dts/mt2701-evb.dts b/arch/arm/boot/dts/mt2701-evb.dts
> index 879f1eb..a483798 100644
> --- a/arch/arm/boot/dts/mt2701-evb.dts
> +++ b/arch/arm/boot/dts/mt2701-evb.dts
> @@ -24,6 +24,10 @@
>  	};
>  };
>
> +&auxadc {
> +	status = "okay";
> +};
> +
>  &pio {
>  	spi_pins_a: spi0 at 0 {
>  		pins_spi {
> diff --git a/arch/arm/boot/dts/mt2701.dtsi b/arch/arm/boot/dts/mt2701.dtsi
> index 1182c43..4f52019 100644
> --- a/arch/arm/boot/dts/mt2701.dtsi
> +++ b/arch/arm/boot/dts/mt2701.dtsi
> @@ -208,6 +208,15 @@
>  		      <0 0x10216000 0 0x2000>;
>  	};
>
> +	auxadc: adc at 11001000 {
> +		compatible = "mediatek,mt2701-auxadc";
> +		reg = <0 0x11001000 0 0x1000>;
> +		clocks = <&pericfg CLK_PERI_AUXADC>;
> +		clock-names = "main";
> +		#io-channel-cells = <1>;
> +		status = "disabled";
> +	};
> +
>  	uart0: serial at 11002000 {
>  		compatible = "mediatek,mt2701-uart",
>  			     "mediatek,mt6577-uart";
>

Re: [PATCH v2 5/6] arm: dts: mt2701: Add ethernet device node.

[John Crispin]

Hi Erin,

small comment inline

On 13/01/2017 09:42, Erin Lo wrote:
> From: Sean Wang <sean.wang@mediatek.com>
> 
> Add ethernet device node for MT2701.
> 
> Signed-off-by: Sean Wang <sean.wang@mediatek.com>
> Signed-off-by: Erin Lo <erin.lo@mediatek.com>
> ---
>  arch/arm/boot/dts/mt2701-evb.dts | 40 ++++++++++++++++++++++++++++++++++++++++
>  arch/arm/boot/dts/mt2701.dtsi    | 22 ++++++++++++++++++++++
>  2 files changed, 62 insertions(+)
> 
> diff --git a/arch/arm/boot/dts/mt2701-evb.dts b/arch/arm/boot/dts/mt2701-evb.dts
> index a483798..40abd3b 100644
> --- a/arch/arm/boot/dts/mt2701-evb.dts
> +++ b/arch/arm/boot/dts/mt2701-evb.dts
> @@ -28,7 +28,47 @@
>  	status = "okay";
>  };
>  
> +&eth {
> +	mac-address = [00 00 00 00 00 00];
> +	status = "okay";
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&gmac1_pins>;
> +	gmac1: mac@1 {
> +		compatible = "mediatek,eth-mac";
> +		reg = <1>;
> +		phy-handle = <&phy5>;
> +	};
> +
> +	mdio-bus {
> +		#address-cells = <1>;
> +		#size-cells = <0>;
> +		phy5: ethernet-phy@5 {
> +			reg = <5>;
> +			phy-mode = "rgmii-rxid";
> +		};
> +	};
> +};
> +
>  &pio {
> +	gmac1_pins: eth@0 {
> +		pins_eth {
> +			pinmux = <MT2701_PIN_275_MDC__FUNC_MDC>,
> +				 <MT2701_PIN_276_MDIO__FUNC_MDIO>,
> +				 <MT2701_PIN_262_G2_TXEN__FUNC_G2_TXEN>,
> +				 <MT2701_PIN_263_G2_TXD3__FUNC_G2_TXD3>,
> +				 <MT2701_PIN_264_G2_TXD2__FUNC_G2_TXD2>,
> +				 <MT2701_PIN_265_G2_TXD1__FUNC_G2_TXD1>,
> +				 <MT2701_PIN_266_G2_TXD0__FUNC_G2_TXD0>,
> +				 <MT2701_PIN_267_G2_TXC__FUNC_G2_TXC>,
> +				 <MT2701_PIN_268_G2_RXC__FUNC_G2_RXC>,
> +				 <MT2701_PIN_269_G2_RXD0__FUNC_G2_RXD0>,
> +				 <MT2701_PIN_270_G2_RXD1__FUNC_G2_RXD1>,
> +				 <MT2701_PIN_271_G2_RXD2__FUNC_G2_RXD2>,
> +				 <MT2701_PIN_272_G2_RXD3__FUNC_G2_RXD3>,
> +				 <MT2701_PIN_274_G2_RXDV__FUNC_G2_RXDV>;
> +		};
> +	};
> +
>  	spi_pins_a: spi0@0 {
>  		pins_spi {
>  			pinmux = <MT2701_PIN_53_SPI0_CSN__FUNC_SPI0_CS>,
> diff --git a/arch/arm/boot/dts/mt2701.dtsi b/arch/arm/boot/dts/mt2701.dtsi
> index 4f52019..3847f70 100644
> --- a/arch/arm/boot/dts/mt2701.dtsi
> +++ b/arch/arm/boot/dts/mt2701.dtsi
> @@ -381,6 +381,28 @@
>  		#clock-cells = <1>;
>  	};
>  
> +	eth: ethernet@1b100000 {
> +		compatible = "mediatek,mt7623-eth";
> +		reg = <0 0x1b100000 0 0x20000>;
> +		interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_LOW>,
> +			     <GIC_SPI 199 IRQ_TYPE_LEVEL_LOW>,
> +			     <GIC_SPI 198 IRQ_TYPE_LEVEL_LOW>;
> +		clocks = <&topckgen CLK_TOP_ETHIF_SEL>,
> +			 <&apmixedsys CLK_APMIXED_TRGPLL>,
> +			 <&ethsys CLK_ETHSYS_ESW>,
> +			 <&ethsys CLK_ETHSYS_GP2>,
> +			 <&ethsys CLK_ETHSYS_GP1>;
> +		clock-names = "ethif", "trgpll", "esw", "gp2", "gp1";
> +		power-domains = <&scpsys MT2701_POWER_DOMAIN_ETH>;
> +		resets = <&watchdog MT2701_TOPRGU_ETHDMA_RST>;

are you sure this is correct ? on mt7623 we point the reset at ethsys
and not the watchdog.

	John

> +		reset-names = "eth";
> +		mediatek,ethsys = <&ethsys>;
> +		mediatek,pctl = <&syscfg_pctl_a>;
> +		#address-cells = <1>;
> +		#size-cells = <0>;
> +		status = "disabled";
> +	};
> +
>  	bdpsys: syscon@1c000000 {
>  		compatible = "mediatek,mt2701-bdpsys", "syscon";
>  		reg = <0 0x1c000000 0 0x1000>;
> 

Re: [PATCH v2 5/6] arm: dts: mt2701: Add ethernet device node.

[John Crispin]

Hi Erin,

small comment inline

On 13/01/2017 09:42, Erin Lo wrote:
> From: Sean Wang <sean.wang-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org>
> 
> Add ethernet device node for MT2701.
> 
> Signed-off-by: Sean Wang <sean.wang-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org>
> Signed-off-by: Erin Lo <erin.lo-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org>
> ---
>  arch/arm/boot/dts/mt2701-evb.dts | 40 ++++++++++++++++++++++++++++++++++++++++
>  arch/arm/boot/dts/mt2701.dtsi    | 22 ++++++++++++++++++++++
>  2 files changed, 62 insertions(+)
> 
> diff --git a/arch/arm/boot/dts/mt2701-evb.dts b/arch/arm/boot/dts/mt2701-evb.dts
> index a483798..40abd3b 100644
> --- a/arch/arm/boot/dts/mt2701-evb.dts
> +++ b/arch/arm/boot/dts/mt2701-evb.dts
> @@ -28,7 +28,47 @@
>  	status = "okay";
>  };
>  
> +&eth {
> +	mac-address = [00 00 00 00 00 00];
> +	status = "okay";
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&gmac1_pins>;
> +	gmac1: mac@1 {
> +		compatible = "mediatek,eth-mac";
> +		reg = <1>;
> +		phy-handle = <&phy5>;
> +	};
> +
> +	mdio-bus {
> +		#address-cells = <1>;
> +		#size-cells = <0>;
> +		phy5: ethernet-phy@5 {
> +			reg = <5>;
> +			phy-mode = "rgmii-rxid";
> +		};
> +	};
> +};
> +
>  &pio {
> +	gmac1_pins: eth@0 {
> +		pins_eth {
> +			pinmux = <MT2701_PIN_275_MDC__FUNC_MDC>,
> +				 <MT2701_PIN_276_MDIO__FUNC_MDIO>,
> +				 <MT2701_PIN_262_G2_TXEN__FUNC_G2_TXEN>,
> +				 <MT2701_PIN_263_G2_TXD3__FUNC_G2_TXD3>,
> +				 <MT2701_PIN_264_G2_TXD2__FUNC_G2_TXD2>,
> +				 <MT2701_PIN_265_G2_TXD1__FUNC_G2_TXD1>,
> +				 <MT2701_PIN_266_G2_TXD0__FUNC_G2_TXD0>,
> +				 <MT2701_PIN_267_G2_TXC__FUNC_G2_TXC>,
> +				 <MT2701_PIN_268_G2_RXC__FUNC_G2_RXC>,
> +				 <MT2701_PIN_269_G2_RXD0__FUNC_G2_RXD0>,
> +				 <MT2701_PIN_270_G2_RXD1__FUNC_G2_RXD1>,
> +				 <MT2701_PIN_271_G2_RXD2__FUNC_G2_RXD2>,
> +				 <MT2701_PIN_272_G2_RXD3__FUNC_G2_RXD3>,
> +				 <MT2701_PIN_274_G2_RXDV__FUNC_G2_RXDV>;
> +		};
> +	};
> +
>  	spi_pins_a: spi0@0 {
>  		pins_spi {
>  			pinmux = <MT2701_PIN_53_SPI0_CSN__FUNC_SPI0_CS>,
> diff --git a/arch/arm/boot/dts/mt2701.dtsi b/arch/arm/boot/dts/mt2701.dtsi
> index 4f52019..3847f70 100644
> --- a/arch/arm/boot/dts/mt2701.dtsi
> +++ b/arch/arm/boot/dts/mt2701.dtsi
> @@ -381,6 +381,28 @@
>  		#clock-cells = <1>;
>  	};
>  
> +	eth: ethernet@1b100000 {
> +		compatible = "mediatek,mt7623-eth";
> +		reg = <0 0x1b100000 0 0x20000>;
> +		interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_LOW>,
> +			     <GIC_SPI 199 IRQ_TYPE_LEVEL_LOW>,
> +			     <GIC_SPI 198 IRQ_TYPE_LEVEL_LOW>;
> +		clocks = <&topckgen CLK_TOP_ETHIF_SEL>,
> +			 <&apmixedsys CLK_APMIXED_TRGPLL>,
> +			 <&ethsys CLK_ETHSYS_ESW>,
> +			 <&ethsys CLK_ETHSYS_GP2>,
> +			 <&ethsys CLK_ETHSYS_GP1>;
> +		clock-names = "ethif", "trgpll", "esw", "gp2", "gp1";
> +		power-domains = <&scpsys MT2701_POWER_DOMAIN_ETH>;
> +		resets = <&watchdog MT2701_TOPRGU_ETHDMA_RST>;

are you sure this is correct ? on mt7623 we point the reset at ethsys
and not the watchdog.

	John

> +		reset-names = "eth";
> +		mediatek,ethsys = <&ethsys>;
> +		mediatek,pctl = <&syscfg_pctl_a>;
> +		#address-cells = <1>;
> +		#size-cells = <0>;
> +		status = "disabled";
> +	};
> +
>  	bdpsys: syscon@1c000000 {
>  		compatible = "mediatek,mt2701-bdpsys", "syscon";
>  		reg = <0 0x1c000000 0 0x1000>;
> 
--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
More majordomo info at  http://vger.kernel.org/majordomo-info.html

[PATCH v2 5/6] arm: dts: mt2701: Add ethernet device node.

[John Crispin]

Hi Erin,

small comment inline

On 13/01/2017 09:42, Erin Lo wrote:
> From: Sean Wang <sean.wang@mediatek.com>
> 
> Add ethernet device node for MT2701.
> 
> Signed-off-by: Sean Wang <sean.wang@mediatek.com>
> Signed-off-by: Erin Lo <erin.lo@mediatek.com>
> ---
>  arch/arm/boot/dts/mt2701-evb.dts | 40 ++++++++++++++++++++++++++++++++++++++++
>  arch/arm/boot/dts/mt2701.dtsi    | 22 ++++++++++++++++++++++
>  2 files changed, 62 insertions(+)
> 
> diff --git a/arch/arm/boot/dts/mt2701-evb.dts b/arch/arm/boot/dts/mt2701-evb.dts
> index a483798..40abd3b 100644
> --- a/arch/arm/boot/dts/mt2701-evb.dts
> +++ b/arch/arm/boot/dts/mt2701-evb.dts
> @@ -28,7 +28,47 @@
>  	status = "okay";
>  };
>  
> +&eth {
> +	mac-address = [00 00 00 00 00 00];
> +	status = "okay";
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&gmac1_pins>;
> +	gmac1: mac at 1 {
> +		compatible = "mediatek,eth-mac";
> +		reg = <1>;
> +		phy-handle = <&phy5>;
> +	};
> +
> +	mdio-bus {
> +		#address-cells = <1>;
> +		#size-cells = <0>;
> +		phy5: ethernet-phy at 5 {
> +			reg = <5>;
> +			phy-mode = "rgmii-rxid";
> +		};
> +	};
> +};
> +
>  &pio {
> +	gmac1_pins: eth at 0 {
> +		pins_eth {
> +			pinmux = <MT2701_PIN_275_MDC__FUNC_MDC>,
> +				 <MT2701_PIN_276_MDIO__FUNC_MDIO>,
> +				 <MT2701_PIN_262_G2_TXEN__FUNC_G2_TXEN>,
> +				 <MT2701_PIN_263_G2_TXD3__FUNC_G2_TXD3>,
> +				 <MT2701_PIN_264_G2_TXD2__FUNC_G2_TXD2>,
> +				 <MT2701_PIN_265_G2_TXD1__FUNC_G2_TXD1>,
> +				 <MT2701_PIN_266_G2_TXD0__FUNC_G2_TXD0>,
> +				 <MT2701_PIN_267_G2_TXC__FUNC_G2_TXC>,
> +				 <MT2701_PIN_268_G2_RXC__FUNC_G2_RXC>,
> +				 <MT2701_PIN_269_G2_RXD0__FUNC_G2_RXD0>,
> +				 <MT2701_PIN_270_G2_RXD1__FUNC_G2_RXD1>,
> +				 <MT2701_PIN_271_G2_RXD2__FUNC_G2_RXD2>,
> +				 <MT2701_PIN_272_G2_RXD3__FUNC_G2_RXD3>,
> +				 <MT2701_PIN_274_G2_RXDV__FUNC_G2_RXDV>;
> +		};
> +	};
> +
>  	spi_pins_a: spi0 at 0 {
>  		pins_spi {
>  			pinmux = <MT2701_PIN_53_SPI0_CSN__FUNC_SPI0_CS>,
> diff --git a/arch/arm/boot/dts/mt2701.dtsi b/arch/arm/boot/dts/mt2701.dtsi
> index 4f52019..3847f70 100644
> --- a/arch/arm/boot/dts/mt2701.dtsi
> +++ b/arch/arm/boot/dts/mt2701.dtsi
> @@ -381,6 +381,28 @@
>  		#clock-cells = <1>;
>  	};
>  
> +	eth: ethernet at 1b100000 {
> +		compatible = "mediatek,mt7623-eth";
> +		reg = <0 0x1b100000 0 0x20000>;
> +		interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_LOW>,
> +			     <GIC_SPI 199 IRQ_TYPE_LEVEL_LOW>,
> +			     <GIC_SPI 198 IRQ_TYPE_LEVEL_LOW>;
> +		clocks = <&topckgen CLK_TOP_ETHIF_SEL>,
> +			 <&apmixedsys CLK_APMIXED_TRGPLL>,
> +			 <&ethsys CLK_ETHSYS_ESW>,
> +			 <&ethsys CLK_ETHSYS_GP2>,
> +			 <&ethsys CLK_ETHSYS_GP1>;
> +		clock-names = "ethif", "trgpll", "esw", "gp2", "gp1";
> +		power-domains = <&scpsys MT2701_POWER_DOMAIN_ETH>;
> +		resets = <&watchdog MT2701_TOPRGU_ETHDMA_RST>;

are you sure this is correct ? on mt7623 we point the reset at ethsys
and not the watchdog.

	John

> +		reset-names = "eth";
> +		mediatek,ethsys = <&ethsys>;
> +		mediatek,pctl = <&syscfg_pctl_a>;
> +		#address-cells = <1>;
> +		#size-cells = <0>;
> +		status = "disabled";
> +	};
> +
>  	bdpsys: syscon at 1c000000 {
>  		compatible = "mediatek,mt2701-bdpsys", "syscon";
>  		reg = <0 0x1c000000 0 0x1000>;
> 

Re: [PATCH v2 5/6] arm: dts: mt2701: Add ethernet device node.

[Sean Wang]

Hi John,

the watchdog driver should just be the driver that includes
reset functions called from driver and then send reset signal
to abnormal hw.. 

however luckily ETHDMA_RST provided from watchdog is not required
and even actually the latest driver didn't refer to the property
no longer. So i will remove it from dtsi in the next version 

  Sean


On Sat, 2017-01-14 at 11:32 +0100, John Crispin wrote:
> Hi Erin,
> 
> small comment inline
> 
> On 13/01/2017 09:42, Erin Lo wrote:
> > From: Sean Wang <sean.wang@mediatek.com>
> > 
> > Add ethernet device node for MT2701.
> > 
> > Signed-off-by: Sean Wang <sean.wang@mediatek.com>
> > Signed-off-by: Erin Lo <erin.lo@mediatek.com>
> > ---
> >  arch/arm/boot/dts/mt2701-evb.dts | 40 ++++++++++++++++++++++++++++++++++++++++
> >  arch/arm/boot/dts/mt2701.dtsi    | 22 ++++++++++++++++++++++
> >  2 files changed, 62 insertions(+)
> > 
> > diff --git a/arch/arm/boot/dts/mt2701-evb.dts b/arch/arm/boot/dts/mt2701-evb.dts
> > index a483798..40abd3b 100644
> > --- a/arch/arm/boot/dts/mt2701-evb.dts
> > +++ b/arch/arm/boot/dts/mt2701-evb.dts
> > @@ -28,7 +28,47 @@
> >  	status = "okay";
> >  };
> >  
> > +&eth {
> > +	mac-address = [00 00 00 00 00 00];
> > +	status = "okay";
> > +	pinctrl-names = "default";
> > +	pinctrl-0 = <&gmac1_pins>;
> > +	gmac1: mac@1 {
> > +		compatible = "mediatek,eth-mac";
> > +		reg = <1>;
> > +		phy-handle = <&phy5>;
> > +	};
> > +
> > +	mdio-bus {
> > +		#address-cells = <1>;
> > +		#size-cells = <0>;
> > +		phy5: ethernet-phy@5 {
> > +			reg = <5>;
> > +			phy-mode = "rgmii-rxid";
> > +		};
> > +	};
> > +};
> > +
> >  &pio {
> > +	gmac1_pins: eth@0 {
> > +		pins_eth {
> > +			pinmux = <MT2701_PIN_275_MDC__FUNC_MDC>,
> > +				 <MT2701_PIN_276_MDIO__FUNC_MDIO>,
> > +				 <MT2701_PIN_262_G2_TXEN__FUNC_G2_TXEN>,
> > +				 <MT2701_PIN_263_G2_TXD3__FUNC_G2_TXD3>,
> > +				 <MT2701_PIN_264_G2_TXD2__FUNC_G2_TXD2>,
> > +				 <MT2701_PIN_265_G2_TXD1__FUNC_G2_TXD1>,
> > +				 <MT2701_PIN_266_G2_TXD0__FUNC_G2_TXD0>,
> > +				 <MT2701_PIN_267_G2_TXC__FUNC_G2_TXC>,
> > +				 <MT2701_PIN_268_G2_RXC__FUNC_G2_RXC>,
> > +				 <MT2701_PIN_269_G2_RXD0__FUNC_G2_RXD0>,
> > +				 <MT2701_PIN_270_G2_RXD1__FUNC_G2_RXD1>,
> > +				 <MT2701_PIN_271_G2_RXD2__FUNC_G2_RXD2>,
> > +				 <MT2701_PIN_272_G2_RXD3__FUNC_G2_RXD3>,
> > +				 <MT2701_PIN_274_G2_RXDV__FUNC_G2_RXDV>;
> > +		};
> > +	};
> > +
> >  	spi_pins_a: spi0@0 {
> >  		pins_spi {
> >  			pinmux = <MT2701_PIN_53_SPI0_CSN__FUNC_SPI0_CS>,
> > diff --git a/arch/arm/boot/dts/mt2701.dtsi b/arch/arm/boot/dts/mt2701.dtsi
> > index 4f52019..3847f70 100644
> > --- a/arch/arm/boot/dts/mt2701.dtsi
> > +++ b/arch/arm/boot/dts/mt2701.dtsi
> > @@ -381,6 +381,28 @@
> >  		#clock-cells = <1>;
> >  	};
> >  
> > +	eth: ethernet@1b100000 {
> > +		compatible = "mediatek,mt7623-eth";
> > +		reg = <0 0x1b100000 0 0x20000>;
> > +		interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_LOW>,
> > +			     <GIC_SPI 199 IRQ_TYPE_LEVEL_LOW>,
> > +			     <GIC_SPI 198 IRQ_TYPE_LEVEL_LOW>;
> > +		clocks = <&topckgen CLK_TOP_ETHIF_SEL>,
> > +			 <&apmixedsys CLK_APMIXED_TRGPLL>,
> > +			 <&ethsys CLK_ETHSYS_ESW>,
> > +			 <&ethsys CLK_ETHSYS_GP2>,
> > +			 <&ethsys CLK_ETHSYS_GP1>;
> > +		clock-names = "ethif", "trgpll", "esw", "gp2", "gp1";
> > +		power-domains = <&scpsys MT2701_POWER_DOMAIN_ETH>;
> > +		resets = <&watchdog MT2701_TOPRGU_ETHDMA_RST>;
> 
> are you sure this is correct ? on mt7623 we point the reset at ethsys
> and not the watchdog.
> 
> 	John
> 
> > +		reset-names = "eth";
> > +		mediatek,ethsys = <&ethsys>;
> > +		mediatek,pctl = <&syscfg_pctl_a>;
> > +		#address-cells = <1>;
> > +		#size-cells = <0>;
> > +		status = "disabled";
> > +	};
> > +
> >  	bdpsys: syscon@1c000000 {
> >  		compatible = "mediatek,mt2701-bdpsys", "syscon";
> >  		reg = <0 0x1c000000 0 0x1000>;
> > 

Re: [PATCH v2 5/6] arm: dts: mt2701: Add ethernet device node.

[Sean Wang]

Hi John,

the watchdog driver should just be the driver that includes
reset functions called from driver and then send reset signal
to abnormal hw.. 

however luckily ETHDMA_RST provided from watchdog is not required
and even actually the latest driver didn't refer to the property
no longer. So i will remove it from dtsi in the next version 

  Sean


On Sat, 2017-01-14 at 11:32 +0100, John Crispin wrote:
> Hi Erin,
> 
> small comment inline
> 
> On 13/01/2017 09:42, Erin Lo wrote:
> > From: Sean Wang <sean.wang@mediatek.com>
> > 
> > Add ethernet device node for MT2701.
> > 
> > Signed-off-by: Sean Wang <sean.wang@mediatek.com>
> > Signed-off-by: Erin Lo <erin.lo@mediatek.com>
> > ---
> >  arch/arm/boot/dts/mt2701-evb.dts | 40 ++++++++++++++++++++++++++++++++++++++++
> >  arch/arm/boot/dts/mt2701.dtsi    | 22 ++++++++++++++++++++++
> >  2 files changed, 62 insertions(+)
> > 
> > diff --git a/arch/arm/boot/dts/mt2701-evb.dts b/arch/arm/boot/dts/mt2701-evb.dts
> > index a483798..40abd3b 100644
> > --- a/arch/arm/boot/dts/mt2701-evb.dts
> > +++ b/arch/arm/boot/dts/mt2701-evb.dts
> > @@ -28,7 +28,47 @@
> >  	status = "okay";
> >  };
> >  
> > +&eth {
> > +	mac-address = [00 00 00 00 00 00];
> > +	status = "okay";
> > +	pinctrl-names = "default";
> > +	pinctrl-0 = <&gmac1_pins>;
> > +	gmac1: mac@1 {
> > +		compatible = "mediatek,eth-mac";
> > +		reg = <1>;
> > +		phy-handle = <&phy5>;
> > +	};
> > +
> > +	mdio-bus {
> > +		#address-cells = <1>;
> > +		#size-cells = <0>;
> > +		phy5: ethernet-phy@5 {
> > +			reg = <5>;
> > +			phy-mode = "rgmii-rxid";
> > +		};
> > +	};
> > +};
> > +
> >  &pio {
> > +	gmac1_pins: eth@0 {
> > +		pins_eth {
> > +			pinmux = <MT2701_PIN_275_MDC__FUNC_MDC>,
> > +				 <MT2701_PIN_276_MDIO__FUNC_MDIO>,
> > +				 <MT2701_PIN_262_G2_TXEN__FUNC_G2_TXEN>,
> > +				 <MT2701_PIN_263_G2_TXD3__FUNC_G2_TXD3>,
> > +				 <MT2701_PIN_264_G2_TXD2__FUNC_G2_TXD2>,
> > +				 <MT2701_PIN_265_G2_TXD1__FUNC_G2_TXD1>,
> > +				 <MT2701_PIN_266_G2_TXD0__FUNC_G2_TXD0>,
> > +				 <MT2701_PIN_267_G2_TXC__FUNC_G2_TXC>,
> > +				 <MT2701_PIN_268_G2_RXC__FUNC_G2_RXC>,
> > +				 <MT2701_PIN_269_G2_RXD0__FUNC_G2_RXD0>,
> > +				 <MT2701_PIN_270_G2_RXD1__FUNC_G2_RXD1>,
> > +				 <MT2701_PIN_271_G2_RXD2__FUNC_G2_RXD2>,
> > +				 <MT2701_PIN_272_G2_RXD3__FUNC_G2_RXD3>,
> > +				 <MT2701_PIN_274_G2_RXDV__FUNC_G2_RXDV>;
> > +		};
> > +	};
> > +
> >  	spi_pins_a: spi0@0 {
> >  		pins_spi {
> >  			pinmux = <MT2701_PIN_53_SPI0_CSN__FUNC_SPI0_CS>,
> > diff --git a/arch/arm/boot/dts/mt2701.dtsi b/arch/arm/boot/dts/mt2701.dtsi
> > index 4f52019..3847f70 100644
> > --- a/arch/arm/boot/dts/mt2701.dtsi
> > +++ b/arch/arm/boot/dts/mt2701.dtsi
> > @@ -381,6 +381,28 @@
> >  		#clock-cells = <1>;
> >  	};
> >  
> > +	eth: ethernet@1b100000 {
> > +		compatible = "mediatek,mt7623-eth";
> > +		reg = <0 0x1b100000 0 0x20000>;
> > +		interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_LOW>,
> > +			     <GIC_SPI 199 IRQ_TYPE_LEVEL_LOW>,
> > +			     <GIC_SPI 198 IRQ_TYPE_LEVEL_LOW>;
> > +		clocks = <&topckgen CLK_TOP_ETHIF_SEL>,
> > +			 <&apmixedsys CLK_APMIXED_TRGPLL>,
> > +			 <&ethsys CLK_ETHSYS_ESW>,
> > +			 <&ethsys CLK_ETHSYS_GP2>,
> > +			 <&ethsys CLK_ETHSYS_GP1>;
> > +		clock-names = "ethif", "trgpll", "esw", "gp2", "gp1";
> > +		power-domains = <&scpsys MT2701_POWER_DOMAIN_ETH>;
> > +		resets = <&watchdog MT2701_TOPRGU_ETHDMA_RST>;
> 
> are you sure this is correct ? on mt7623 we point the reset at ethsys
> and not the watchdog.
> 
> 	John
> 
> > +		reset-names = "eth";
> > +		mediatek,ethsys = <&ethsys>;
> > +		mediatek,pctl = <&syscfg_pctl_a>;
> > +		#address-cells = <1>;
> > +		#size-cells = <0>;
> > +		status = "disabled";
> > +	};
> > +
> >  	bdpsys: syscon@1c000000 {
> >  		compatible = "mediatek,mt2701-bdpsys", "syscon";
> >  		reg = <0 0x1c000000 0 0x1000>;
> > 

[PATCH v2 5/6] arm: dts: mt2701: Add ethernet device node.

[Sean Wang]

Hi John,

the watchdog driver should just be the driver that includes
reset functions called from driver and then send reset signal
to abnormal hw.. 

however luckily ETHDMA_RST provided from watchdog is not required
and even actually the latest driver didn't refer to the property
no longer. So i will remove it from dtsi in the next version 

  Sean


On Sat, 2017-01-14 at 11:32 +0100, John Crispin wrote:
> Hi Erin,
> 
> small comment inline
> 
> On 13/01/2017 09:42, Erin Lo wrote:
> > From: Sean Wang <sean.wang@mediatek.com>
> > 
> > Add ethernet device node for MT2701.
> > 
> > Signed-off-by: Sean Wang <sean.wang@mediatek.com>
> > Signed-off-by: Erin Lo <erin.lo@mediatek.com>
> > ---
> >  arch/arm/boot/dts/mt2701-evb.dts | 40 ++++++++++++++++++++++++++++++++++++++++
> >  arch/arm/boot/dts/mt2701.dtsi    | 22 ++++++++++++++++++++++
> >  2 files changed, 62 insertions(+)
> > 
> > diff --git a/arch/arm/boot/dts/mt2701-evb.dts b/arch/arm/boot/dts/mt2701-evb.dts
> > index a483798..40abd3b 100644
> > --- a/arch/arm/boot/dts/mt2701-evb.dts
> > +++ b/arch/arm/boot/dts/mt2701-evb.dts
> > @@ -28,7 +28,47 @@
> >  	status = "okay";
> >  };
> >  
> > +&eth {
> > +	mac-address = [00 00 00 00 00 00];
> > +	status = "okay";
> > +	pinctrl-names = "default";
> > +	pinctrl-0 = <&gmac1_pins>;
> > +	gmac1: mac at 1 {
> > +		compatible = "mediatek,eth-mac";
> > +		reg = <1>;
> > +		phy-handle = <&phy5>;
> > +	};
> > +
> > +	mdio-bus {
> > +		#address-cells = <1>;
> > +		#size-cells = <0>;
> > +		phy5: ethernet-phy at 5 {
> > +			reg = <5>;
> > +			phy-mode = "rgmii-rxid";
> > +		};
> > +	};
> > +};
> > +
> >  &pio {
> > +	gmac1_pins: eth at 0 {
> > +		pins_eth {
> > +			pinmux = <MT2701_PIN_275_MDC__FUNC_MDC>,
> > +				 <MT2701_PIN_276_MDIO__FUNC_MDIO>,
> > +				 <MT2701_PIN_262_G2_TXEN__FUNC_G2_TXEN>,
> > +				 <MT2701_PIN_263_G2_TXD3__FUNC_G2_TXD3>,
> > +				 <MT2701_PIN_264_G2_TXD2__FUNC_G2_TXD2>,
> > +				 <MT2701_PIN_265_G2_TXD1__FUNC_G2_TXD1>,
> > +				 <MT2701_PIN_266_G2_TXD0__FUNC_G2_TXD0>,
> > +				 <MT2701_PIN_267_G2_TXC__FUNC_G2_TXC>,
> > +				 <MT2701_PIN_268_G2_RXC__FUNC_G2_RXC>,
> > +				 <MT2701_PIN_269_G2_RXD0__FUNC_G2_RXD0>,
> > +				 <MT2701_PIN_270_G2_RXD1__FUNC_G2_RXD1>,
> > +				 <MT2701_PIN_271_G2_RXD2__FUNC_G2_RXD2>,
> > +				 <MT2701_PIN_272_G2_RXD3__FUNC_G2_RXD3>,
> > +				 <MT2701_PIN_274_G2_RXDV__FUNC_G2_RXDV>;
> > +		};
> > +	};
> > +
> >  	spi_pins_a: spi0 at 0 {
> >  		pins_spi {
> >  			pinmux = <MT2701_PIN_53_SPI0_CSN__FUNC_SPI0_CS>,
> > diff --git a/arch/arm/boot/dts/mt2701.dtsi b/arch/arm/boot/dts/mt2701.dtsi
> > index 4f52019..3847f70 100644
> > --- a/arch/arm/boot/dts/mt2701.dtsi
> > +++ b/arch/arm/boot/dts/mt2701.dtsi
> > @@ -381,6 +381,28 @@
> >  		#clock-cells = <1>;
> >  	};
> >  
> > +	eth: ethernet at 1b100000 {
> > +		compatible = "mediatek,mt7623-eth";
> > +		reg = <0 0x1b100000 0 0x20000>;
> > +		interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_LOW>,
> > +			     <GIC_SPI 199 IRQ_TYPE_LEVEL_LOW>,
> > +			     <GIC_SPI 198 IRQ_TYPE_LEVEL_LOW>;
> > +		clocks = <&topckgen CLK_TOP_ETHIF_SEL>,
> > +			 <&apmixedsys CLK_APMIXED_TRGPLL>,
> > +			 <&ethsys CLK_ETHSYS_ESW>,
> > +			 <&ethsys CLK_ETHSYS_GP2>,
> > +			 <&ethsys CLK_ETHSYS_GP1>;
> > +		clock-names = "ethif", "trgpll", "esw", "gp2", "gp1";
> > +		power-domains = <&scpsys MT2701_POWER_DOMAIN_ETH>;
> > +		resets = <&watchdog MT2701_TOPRGU_ETHDMA_RST>;
> 
> are you sure this is correct ? on mt7623 we point the reset at ethsys
> and not the watchdog.
> 
> 	John
> 
> > +		reset-names = "eth";
> > +		mediatek,ethsys = <&ethsys>;
> > +		mediatek,pctl = <&syscfg_pctl_a>;
> > +		#address-cells = <1>;
> > +		#size-cells = <0>;
> > +		status = "disabled";
> > +	};
> > +
> >  	bdpsys: syscon at 1c000000 {
> >  		compatible = "mediatek,mt2701-bdpsys", "syscon";
> >  		reg = <0 0x1c000000 0 0x1000>;
> > 

Re: [PATCH v2 2/6] arm: dts: mt2701: Add iommu/smi device node

[Honghui Zhang]

On Fri, 2017-01-13 at 16:05 +0100, Matthias Brugger wrote:
> Hi Erin,
> 
> I just took the patch from Honghui he send in june.
> Please see my comment inline.
> 
> On 13/01/17 09:42, Erin Lo wrote:
> > From: Honghui Zhang <honghui.zhang@mediatek.com>
> >
> > Add the device node of iommu and smi for MT2701.
> >
> > Signed-off-by: Honghui Zhang <honghui.zhang@mediatek.com>
> > Signed-off-by: Erin Lo <erin.lo@mediatek.com>
> > ---
> >  arch/arm/boot/dts/mt2701.dtsi | 54 +++++++++++++++++++++++++++++++++++++++++++
> >  1 file changed, 54 insertions(+)
> >
> > diff --git a/arch/arm/boot/dts/mt2701.dtsi b/arch/arm/boot/dts/mt2701.dtsi
> > index eb4c6fd..87be52c 100644
> > --- a/arch/arm/boot/dts/mt2701.dtsi
> > +++ b/arch/arm/boot/dts/mt2701.dtsi
> > @@ -17,6 +17,7 @@
> >  #include <dt-bindings/interrupt-controller/irq.h>
> >  #include <dt-bindings/interrupt-controller/arm-gic.h>
> >  #include <dt-bindings/reset/mt2701-resets.h>
> > +#include <dt-bindings/memory/mt2701-larb-port.h>
> >  #include "skeleton64.dtsi"
> >  #include "mt2701-pinfunc.h"
> >
> > @@ -161,6 +162,16 @@
> >  		clock-names = "system-clk", "rtc-clk";
> >  	};
> >
> > +	smi_common: smi@1000c000 {
> > +		compatible = "mediatek,mt2701-smi-common";
> > +		reg = <0 0x1000c000 0 0x1000>;
> > +		clocks = <&infracfg CLK_INFRA_SMI>,
> > +			 <&mmsys CLK_MM_SMI_COMMON>,
> > +			 <&infracfg CLK_INFRA_SMI>;
> > +		clock-names = "apb", "smi", "async";
> > +		power-domains = <&scpsys MT2701_POWER_DOMAIN_DISP>;
> > +	};
> > +
> >  	sysirq: interrupt-controller@10200100 {
> >  		compatible = "mediatek,mt2701-sysirq",
> >  			     "mediatek,mt6577-sysirq";
> > @@ -170,6 +181,16 @@
> >  		reg = <0 0x10200100 0 0x1c>;
> >  	};
> >
> > +	iommu: mmsys_iommu@10205000 {
> > +		compatible = "mediatek,mt2701-m4u";
> > +		reg = <0 0x10205000 0 0x1000>;
> > +		interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_LOW>;
> > +		clocks = <&infracfg CLK_INFRA_M4U>;
> > +		clock-names = "bclk";
> > +		mediatek,larbs = <&larb0 &larb1 &larb2>;
> > +		#iommu-cells = <1>;
> > +	};
> > +
> >  	apmixedsys: syscon@10209000 {
> >  		compatible = "mediatek,mt2701-apmixedsys", "syscon";
> >  		reg = <0 0x10209000 0 0x1000>;
> > @@ -272,18 +293,51 @@
> >  		#clock-cells = <1>;
> >  	};
> >
> > +	larb0: larb@14010000 {
> > +		compatible = "mediatek,mt2701-smi-larb";
> > +		reg = <0 0x14010000 0 0x1000>;
> > +		mediatek,smi = <&smi_common>;
> > +		mediatek,larbidx = <0>;
> 
> Did I miss something? 'mediatek,larbidx' does not sound familiar to me.
> 

Hi, Mathias,
	It's my mistake, we found a bug need this to fix in smi driver,
but I mix those patches together and make it un-clear.

	I will send new patch serial to add the 'mediatek,larbidx' later since
you have applied the last one.

thanks very much.

> Regards,
> Matthias
> 
> > +		clocks = <&mmsys CLK_MM_SMI_LARB0>,
> > +			 <&mmsys CLK_MM_SMI_LARB0>;
> > +		clock-names = "apb", "smi";
> > +		power-domains = <&scpsys MT2701_POWER_DOMAIN_DISP>;
> > +	};
> > +
> >  	imgsys: syscon@15000000 {
> >  		compatible = "mediatek,mt2701-imgsys", "syscon";
> >  		reg = <0 0x15000000 0 0x1000>;
> >  		#clock-cells = <1>;
> >  	};
> >
> > +	larb2: larb@15001000 {
> > +		compatible = "mediatek,mt2701-smi-larb";
> > +		reg = <0 0x15001000 0 0x1000>;
> > +		mediatek,smi = <&smi_common>;
> > +		mediatek,larbidx = <2>;
> > +		clocks = <&imgsys CLK_IMG_SMI_COMM>,
> > +			 <&imgsys CLK_IMG_SMI_COMM>;
> > +		clock-names = "apb", "smi";
> > +		power-domains = <&scpsys MT2701_POWER_DOMAIN_ISP>;
> > +	};
> > +
> >  	vdecsys: syscon@16000000 {
> >  		compatible = "mediatek,mt2701-vdecsys", "syscon";
> >  		reg = <0 0x16000000 0 0x1000>;
> >  		#clock-cells = <1>;
> >  	};
> >
> > +	larb1: larb@16010000 {
> > +		compatible = "mediatek,mt2701-smi-larb";
> > +		reg = <0 0x16010000 0 0x1000>;
> > +		mediatek,smi = <&smi_common>;
> > +		mediatek,larbidx = <1>;
> > +		clocks = <&vdecsys CLK_VDEC_CKGEN>,
> > +			 <&vdecsys CLK_VDEC_LARB>;
> > +		clock-names = "apb", "smi";
> > +		power-domains = <&scpsys MT2701_POWER_DOMAIN_VDEC>;
> > +	};
> > +
> >  	hifsys: syscon@1a000000 {
> >  		compatible = "mediatek,mt2701-hifsys", "syscon";
> >  		reg = <0 0x1a000000 0 0x1000>;
> >

Re: [PATCH v2 2/6] arm: dts: mt2701: Add iommu/smi device node

[Honghui Zhang]

On Fri, 2017-01-13 at 16:05 +0100, Matthias Brugger wrote:
> Hi Erin,
> 
> I just took the patch from Honghui he send in june.
> Please see my comment inline.
> 
> On 13/01/17 09:42, Erin Lo wrote:
> > From: Honghui Zhang <honghui.zhang@mediatek.com>
> >
> > Add the device node of iommu and smi for MT2701.
> >
> > Signed-off-by: Honghui Zhang <honghui.zhang@mediatek.com>
> > Signed-off-by: Erin Lo <erin.lo@mediatek.com>
> > ---
> >  arch/arm/boot/dts/mt2701.dtsi | 54 +++++++++++++++++++++++++++++++++++++++++++
> >  1 file changed, 54 insertions(+)
> >
> > diff --git a/arch/arm/boot/dts/mt2701.dtsi b/arch/arm/boot/dts/mt2701.dtsi
> > index eb4c6fd..87be52c 100644
> > --- a/arch/arm/boot/dts/mt2701.dtsi
> > +++ b/arch/arm/boot/dts/mt2701.dtsi
> > @@ -17,6 +17,7 @@
> >  #include <dt-bindings/interrupt-controller/irq.h>
> >  #include <dt-bindings/interrupt-controller/arm-gic.h>
> >  #include <dt-bindings/reset/mt2701-resets.h>
> > +#include <dt-bindings/memory/mt2701-larb-port.h>
> >  #include "skeleton64.dtsi"
> >  #include "mt2701-pinfunc.h"
> >
> > @@ -161,6 +162,16 @@
> >  		clock-names = "system-clk", "rtc-clk";
> >  	};
> >
> > +	smi_common: smi@1000c000 {
> > +		compatible = "mediatek,mt2701-smi-common";
> > +		reg = <0 0x1000c000 0 0x1000>;
> > +		clocks = <&infracfg CLK_INFRA_SMI>,
> > +			 <&mmsys CLK_MM_SMI_COMMON>,
> > +			 <&infracfg CLK_INFRA_SMI>;
> > +		clock-names = "apb", "smi", "async";
> > +		power-domains = <&scpsys MT2701_POWER_DOMAIN_DISP>;
> > +	};
> > +
> >  	sysirq: interrupt-controller@10200100 {
> >  		compatible = "mediatek,mt2701-sysirq",
> >  			     "mediatek,mt6577-sysirq";
> > @@ -170,6 +181,16 @@
> >  		reg = <0 0x10200100 0 0x1c>;
> >  	};
> >
> > +	iommu: mmsys_iommu@10205000 {
> > +		compatible = "mediatek,mt2701-m4u";
> > +		reg = <0 0x10205000 0 0x1000>;
> > +		interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_LOW>;
> > +		clocks = <&infracfg CLK_INFRA_M4U>;
> > +		clock-names = "bclk";
> > +		mediatek,larbs = <&larb0 &larb1 &larb2>;
> > +		#iommu-cells = <1>;
> > +	};
> > +
> >  	apmixedsys: syscon@10209000 {
> >  		compatible = "mediatek,mt2701-apmixedsys", "syscon";
> >  		reg = <0 0x10209000 0 0x1000>;
> > @@ -272,18 +293,51 @@
> >  		#clock-cells = <1>;
> >  	};
> >
> > +	larb0: larb@14010000 {
> > +		compatible = "mediatek,mt2701-smi-larb";
> > +		reg = <0 0x14010000 0 0x1000>;
> > +		mediatek,smi = <&smi_common>;
> > +		mediatek,larbidx = <0>;
> 
> Did I miss something? 'mediatek,larbidx' does not sound familiar to me.
> 

Hi, Mathias,
	It's my mistake, we found a bug need this to fix in smi driver,
but I mix those patches together and make it un-clear.

	I will send new patch serial to add the 'mediatek,larbidx' later since
you have applied the last one.

thanks very much.

> Regards,
> Matthias
> 
> > +		clocks = <&mmsys CLK_MM_SMI_LARB0>,
> > +			 <&mmsys CLK_MM_SMI_LARB0>;
> > +		clock-names = "apb", "smi";
> > +		power-domains = <&scpsys MT2701_POWER_DOMAIN_DISP>;
> > +	};
> > +
> >  	imgsys: syscon@15000000 {
> >  		compatible = "mediatek,mt2701-imgsys", "syscon";
> >  		reg = <0 0x15000000 0 0x1000>;
> >  		#clock-cells = <1>;
> >  	};
> >
> > +	larb2: larb@15001000 {
> > +		compatible = "mediatek,mt2701-smi-larb";
> > +		reg = <0 0x15001000 0 0x1000>;
> > +		mediatek,smi = <&smi_common>;
> > +		mediatek,larbidx = <2>;
> > +		clocks = <&imgsys CLK_IMG_SMI_COMM>,
> > +			 <&imgsys CLK_IMG_SMI_COMM>;
> > +		clock-names = "apb", "smi";
> > +		power-domains = <&scpsys MT2701_POWER_DOMAIN_ISP>;
> > +	};
> > +
> >  	vdecsys: syscon@16000000 {
> >  		compatible = "mediatek,mt2701-vdecsys", "syscon";
> >  		reg = <0 0x16000000 0 0x1000>;
> >  		#clock-cells = <1>;
> >  	};
> >
> > +	larb1: larb@16010000 {
> > +		compatible = "mediatek,mt2701-smi-larb";
> > +		reg = <0 0x16010000 0 0x1000>;
> > +		mediatek,smi = <&smi_common>;
> > +		mediatek,larbidx = <1>;
> > +		clocks = <&vdecsys CLK_VDEC_CKGEN>,
> > +			 <&vdecsys CLK_VDEC_LARB>;
> > +		clock-names = "apb", "smi";
> > +		power-domains = <&scpsys MT2701_POWER_DOMAIN_VDEC>;
> > +	};
> > +
> >  	hifsys: syscon@1a000000 {
> >  		compatible = "mediatek,mt2701-hifsys", "syscon";
> >  		reg = <0 0x1a000000 0 0x1000>;
> >

[PATCH v2 2/6] arm: dts: mt2701: Add iommu/smi device node

[Honghui Zhang]

On Fri, 2017-01-13 at 16:05 +0100, Matthias Brugger wrote:
> Hi Erin,
> 
> I just took the patch from Honghui he send in june.
> Please see my comment inline.
> 
> On 13/01/17 09:42, Erin Lo wrote:
> > From: Honghui Zhang <honghui.zhang@mediatek.com>
> >
> > Add the device node of iommu and smi for MT2701.
> >
> > Signed-off-by: Honghui Zhang <honghui.zhang@mediatek.com>
> > Signed-off-by: Erin Lo <erin.lo@mediatek.com>
> > ---
> >  arch/arm/boot/dts/mt2701.dtsi | 54 +++++++++++++++++++++++++++++++++++++++++++
> >  1 file changed, 54 insertions(+)
> >
> > diff --git a/arch/arm/boot/dts/mt2701.dtsi b/arch/arm/boot/dts/mt2701.dtsi
> > index eb4c6fd..87be52c 100644
> > --- a/arch/arm/boot/dts/mt2701.dtsi
> > +++ b/arch/arm/boot/dts/mt2701.dtsi
> > @@ -17,6 +17,7 @@
> >  #include <dt-bindings/interrupt-controller/irq.h>
> >  #include <dt-bindings/interrupt-controller/arm-gic.h>
> >  #include <dt-bindings/reset/mt2701-resets.h>
> > +#include <dt-bindings/memory/mt2701-larb-port.h>
> >  #include "skeleton64.dtsi"
> >  #include "mt2701-pinfunc.h"
> >
> > @@ -161,6 +162,16 @@
> >  		clock-names = "system-clk", "rtc-clk";
> >  	};
> >
> > +	smi_common: smi at 1000c000 {
> > +		compatible = "mediatek,mt2701-smi-common";
> > +		reg = <0 0x1000c000 0 0x1000>;
> > +		clocks = <&infracfg CLK_INFRA_SMI>,
> > +			 <&mmsys CLK_MM_SMI_COMMON>,
> > +			 <&infracfg CLK_INFRA_SMI>;
> > +		clock-names = "apb", "smi", "async";
> > +		power-domains = <&scpsys MT2701_POWER_DOMAIN_DISP>;
> > +	};
> > +
> >  	sysirq: interrupt-controller at 10200100 {
> >  		compatible = "mediatek,mt2701-sysirq",
> >  			     "mediatek,mt6577-sysirq";
> > @@ -170,6 +181,16 @@
> >  		reg = <0 0x10200100 0 0x1c>;
> >  	};
> >
> > +	iommu: mmsys_iommu at 10205000 {
> > +		compatible = "mediatek,mt2701-m4u";
> > +		reg = <0 0x10205000 0 0x1000>;
> > +		interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_LOW>;
> > +		clocks = <&infracfg CLK_INFRA_M4U>;
> > +		clock-names = "bclk";
> > +		mediatek,larbs = <&larb0 &larb1 &larb2>;
> > +		#iommu-cells = <1>;
> > +	};
> > +
> >  	apmixedsys: syscon at 10209000 {
> >  		compatible = "mediatek,mt2701-apmixedsys", "syscon";
> >  		reg = <0 0x10209000 0 0x1000>;
> > @@ -272,18 +293,51 @@
> >  		#clock-cells = <1>;
> >  	};
> >
> > +	larb0: larb at 14010000 {
> > +		compatible = "mediatek,mt2701-smi-larb";
> > +		reg = <0 0x14010000 0 0x1000>;
> > +		mediatek,smi = <&smi_common>;
> > +		mediatek,larbidx = <0>;
> 
> Did I miss something? 'mediatek,larbidx' does not sound familiar to me.
> 

Hi, Mathias,
	It's my mistake, we found a bug need this to fix in smi driver,
but I mix those patches together and make it un-clear.

	I will send new patch serial to add the 'mediatek,larbidx' later since
you have applied the last one.

thanks very much.

> Regards,
> Matthias
> 
> > +		clocks = <&mmsys CLK_MM_SMI_LARB0>,
> > +			 <&mmsys CLK_MM_SMI_LARB0>;
> > +		clock-names = "apb", "smi";
> > +		power-domains = <&scpsys MT2701_POWER_DOMAIN_DISP>;
> > +	};
> > +
> >  	imgsys: syscon at 15000000 {
> >  		compatible = "mediatek,mt2701-imgsys", "syscon";
> >  		reg = <0 0x15000000 0 0x1000>;
> >  		#clock-cells = <1>;
> >  	};
> >
> > +	larb2: larb at 15001000 {
> > +		compatible = "mediatek,mt2701-smi-larb";
> > +		reg = <0 0x15001000 0 0x1000>;
> > +		mediatek,smi = <&smi_common>;
> > +		mediatek,larbidx = <2>;
> > +		clocks = <&imgsys CLK_IMG_SMI_COMM>,
> > +			 <&imgsys CLK_IMG_SMI_COMM>;
> > +		clock-names = "apb", "smi";
> > +		power-domains = <&scpsys MT2701_POWER_DOMAIN_ISP>;
> > +	};
> > +
> >  	vdecsys: syscon at 16000000 {
> >  		compatible = "mediatek,mt2701-vdecsys", "syscon";
> >  		reg = <0 0x16000000 0 0x1000>;
> >  		#clock-cells = <1>;
> >  	};
> >
> > +	larb1: larb at 16010000 {
> > +		compatible = "mediatek,mt2701-smi-larb";
> > +		reg = <0 0x16010000 0 0x1000>;
> > +		mediatek,smi = <&smi_common>;
> > +		mediatek,larbidx = <1>;
> > +		clocks = <&vdecsys CLK_VDEC_CKGEN>,
> > +			 <&vdecsys CLK_VDEC_LARB>;
> > +		clock-names = "apb", "smi";
> > +		power-domains = <&scpsys MT2701_POWER_DOMAIN_VDEC>;
> > +	};
> > +
> >  	hifsys: syscon at 1a000000 {
> >  		compatible = "mediatek,mt2701-hifsys", "syscon";
> >  		reg = <0 0x1a000000 0 0x1000>;
> >

Re: [PATCH v2 6/6] arm: dts: mt2701: Add thermal device node.

[Dawei Chien]

On Fri, 2017-01-13 at 16:27 +0100, Matthias Brugger wrote:
> 
> On 13/01/17 09:42, Erin Lo wrote:
> > From: Dawei Chien <dawei.chien@mediatek.com>
> >
> > Add thermal controller device nodes for MT2701.
> >
> > Signed-off-by: Dawei Chien <dawei.chien@mediatek.com>
> > Signed-off-by: Erin Lo <erin.lo@mediatek.com>
> > ---
> >  arch/arm/boot/dts/mt2701.dtsi | 43 +++++++++++++++++++++++++++++++++++++++++++
> >  1 file changed, 43 insertions(+)
> >
> > diff --git a/arch/arm/boot/dts/mt2701.dtsi b/arch/arm/boot/dts/mt2701.dtsi
> > index 3847f70..c43d5f8 100644
> > --- a/arch/arm/boot/dts/mt2701.dtsi
> > +++ b/arch/arm/boot/dts/mt2701.dtsi
> > @@ -89,6 +89,36 @@
> >  		clock-output-names = "rtc32k";
> >  	};
> >
> > +	thermal-zones {
> > +		cpu_thermal: cpu_thermal {
> > +			polling-delay-passive = <1000>; /* milliseconds */
> > +			polling-delay = <1000>; /* milliseconds */
> > +
> > +			thermal-sensors = <&thermal 0>;
> > +			sustainable-power = <1000>;
> > +
> > +			trips {
> > +				threshold: trip-point@0 {
> > +					temperature = <68000>;
> > +					hysteresis = <2000>;
> > +					type = "passive";
> > +				};
> > +
> > +				target: trip-point@1 {
> > +					temperature = <85000>;
> > +					hysteresis = <2000>;
> > +					type = "passive";
> > +				};
> > +
> > +				cpu_crit: cpu_crit@0 {
> > +					temperature = <115000>;
> > +					hysteresis = <2000>;
> > +					type = "critical";
> > +				};
> > +			};
> > +		};
> > +	};
> > +
> >  	timer {
> >  		compatible = "arm,armv7-timer";
> >  		interrupt-parent = <&gic>;
> > @@ -270,6 +300,19 @@
> >  		status = "disabled";
> >  	};
> >
> > +	thermal: thermal@1100b000 {
> > +		#thermal-sensor-cells = <0>;
> > +		compatible = "mediatek,mt2701-thermal";
> > +		reg = <0 0x1100b000 0 0x1000>;
> > +		interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_LOW>;
> > +		clocks = <&pericfg CLK_PERI_THERM>, <&pericfg CLK_PERI_AUXADC>;
> > +		clock-names = "therm", "auxadc";
> > +		resets = <&pericfg 0x10>;
> 
> should be MT2701_PERI_AUXADC_SW_RST, right?
> 
Thank you for your reminding, I didn't realize mt2701-resets.h upstream
already, I would update on next version, thank you.

resets = <&pericfg MT2701_PERI_AUXADC_SW_RST>;

> > +		reset-names = "therm";
> > +		mediatek,auxadc = <&auxadc>;
> > +		mediatek,apmixedsys = <&apmixedsys>;
> > +	};
> > +
> >  	nandc: nfi@1100d000 {
> >  		compatible = "mediatek,mt2701-nfc";
> >  		reg = <0 0x1100d000 0 0x1000>;
> >

Re: [PATCH v2 6/6] arm: dts: mt2701: Add thermal device node.

[Dawei Chien]

On Fri, 2017-01-13 at 16:27 +0100, Matthias Brugger wrote:
> 
> On 13/01/17 09:42, Erin Lo wrote:
> > From: Dawei Chien <dawei.chien@mediatek.com>
> >
> > Add thermal controller device nodes for MT2701.
> >
> > Signed-off-by: Dawei Chien <dawei.chien@mediatek.com>
> > Signed-off-by: Erin Lo <erin.lo@mediatek.com>
> > ---
> >  arch/arm/boot/dts/mt2701.dtsi | 43 +++++++++++++++++++++++++++++++++++++++++++
> >  1 file changed, 43 insertions(+)
> >
> > diff --git a/arch/arm/boot/dts/mt2701.dtsi b/arch/arm/boot/dts/mt2701.dtsi
> > index 3847f70..c43d5f8 100644
> > --- a/arch/arm/boot/dts/mt2701.dtsi
> > +++ b/arch/arm/boot/dts/mt2701.dtsi
> > @@ -89,6 +89,36 @@
> >  		clock-output-names = "rtc32k";
> >  	};
> >
> > +	thermal-zones {
> > +		cpu_thermal: cpu_thermal {
> > +			polling-delay-passive = <1000>; /* milliseconds */
> > +			polling-delay = <1000>; /* milliseconds */
> > +
> > +			thermal-sensors = <&thermal 0>;
> > +			sustainable-power = <1000>;
> > +
> > +			trips {
> > +				threshold: trip-point@0 {
> > +					temperature = <68000>;
> > +					hysteresis = <2000>;
> > +					type = "passive";
> > +				};
> > +
> > +				target: trip-point@1 {
> > +					temperature = <85000>;
> > +					hysteresis = <2000>;
> > +					type = "passive";
> > +				};
> > +
> > +				cpu_crit: cpu_crit@0 {
> > +					temperature = <115000>;
> > +					hysteresis = <2000>;
> > +					type = "critical";
> > +				};
> > +			};
> > +		};
> > +	};
> > +
> >  	timer {
> >  		compatible = "arm,armv7-timer";
> >  		interrupt-parent = <&gic>;
> > @@ -270,6 +300,19 @@
> >  		status = "disabled";
> >  	};
> >
> > +	thermal: thermal@1100b000 {
> > +		#thermal-sensor-cells = <0>;
> > +		compatible = "mediatek,mt2701-thermal";
> > +		reg = <0 0x1100b000 0 0x1000>;
> > +		interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_LOW>;
> > +		clocks = <&pericfg CLK_PERI_THERM>, <&pericfg CLK_PERI_AUXADC>;
> > +		clock-names = "therm", "auxadc";
> > +		resets = <&pericfg 0x10>;
> 
> should be MT2701_PERI_AUXADC_SW_RST, right?
> 
Thank you for your reminding, I didn't realize mt2701-resets.h upstream
already, I would update on next version, thank you.

resets = <&pericfg MT2701_PERI_AUXADC_SW_RST>;

> > +		reset-names = "therm";
> > +		mediatek,auxadc = <&auxadc>;
> > +		mediatek,apmixedsys = <&apmixedsys>;
> > +	};
> > +
> >  	nandc: nfi@1100d000 {
> >  		compatible = "mediatek,mt2701-nfc";
> >  		reg = <0 0x1100d000 0 0x1000>;
> >

[PATCH v2 6/6] arm: dts: mt2701: Add thermal device node.

[Dawei Chien]

On Fri, 2017-01-13 at 16:27 +0100, Matthias Brugger wrote:
> 
> On 13/01/17 09:42, Erin Lo wrote:
> > From: Dawei Chien <dawei.chien@mediatek.com>
> >
> > Add thermal controller device nodes for MT2701.
> >
> > Signed-off-by: Dawei Chien <dawei.chien@mediatek.com>
> > Signed-off-by: Erin Lo <erin.lo@mediatek.com>
> > ---
> >  arch/arm/boot/dts/mt2701.dtsi | 43 +++++++++++++++++++++++++++++++++++++++++++
> >  1 file changed, 43 insertions(+)
> >
> > diff --git a/arch/arm/boot/dts/mt2701.dtsi b/arch/arm/boot/dts/mt2701.dtsi
> > index 3847f70..c43d5f8 100644
> > --- a/arch/arm/boot/dts/mt2701.dtsi
> > +++ b/arch/arm/boot/dts/mt2701.dtsi
> > @@ -89,6 +89,36 @@
> >  		clock-output-names = "rtc32k";
> >  	};
> >
> > +	thermal-zones {
> > +		cpu_thermal: cpu_thermal {
> > +			polling-delay-passive = <1000>; /* milliseconds */
> > +			polling-delay = <1000>; /* milliseconds */
> > +
> > +			thermal-sensors = <&thermal 0>;
> > +			sustainable-power = <1000>;
> > +
> > +			trips {
> > +				threshold: trip-point at 0 {
> > +					temperature = <68000>;
> > +					hysteresis = <2000>;
> > +					type = "passive";
> > +				};
> > +
> > +				target: trip-point at 1 {
> > +					temperature = <85000>;
> > +					hysteresis = <2000>;
> > +					type = "passive";
> > +				};
> > +
> > +				cpu_crit: cpu_crit at 0 {
> > +					temperature = <115000>;
> > +					hysteresis = <2000>;
> > +					type = "critical";
> > +				};
> > +			};
> > +		};
> > +	};
> > +
> >  	timer {
> >  		compatible = "arm,armv7-timer";
> >  		interrupt-parent = <&gic>;
> > @@ -270,6 +300,19 @@
> >  		status = "disabled";
> >  	};
> >
> > +	thermal: thermal at 1100b000 {
> > +		#thermal-sensor-cells = <0>;
> > +		compatible = "mediatek,mt2701-thermal";
> > +		reg = <0 0x1100b000 0 0x1000>;
> > +		interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_LOW>;
> > +		clocks = <&pericfg CLK_PERI_THERM>, <&pericfg CLK_PERI_AUXADC>;
> > +		clock-names = "therm", "auxadc";
> > +		resets = <&pericfg 0x10>;
> 
> should be MT2701_PERI_AUXADC_SW_RST, right?
> 
Thank you for your reminding, I didn't realize mt2701-resets.h upstream
already, I would update on next version, thank you.

resets = <&pericfg MT2701_PERI_AUXADC_SW_RST>;

> > +		reset-names = "therm";
> > +		mediatek,auxadc = <&auxadc>;
> > +		mediatek,apmixedsys = <&apmixedsys>;
> > +	};
> > +
> >  	nandc: nfi at 1100d000 {
> >  		compatible = "mediatek,mt2701-nfc";
> >  		reg = <0 0x1100d000 0 0x1000>;
> >

Re: [PATCH v2 6/6] arm: dts: mt2701: Add thermal device node.

[Dawei Chien]

On Mon, 2017-01-16 at 11:44 +0800, Dawei Chien wrote:
> On Fri, 2017-01-13 at 16:27 +0100, Matthias Brugger wrote:
> > 
> > On 13/01/17 09:42, Erin Lo wrote:
> > > From: Dawei Chien <dawei.chien@mediatek.com>
> > >
> > > Add thermal controller device nodes for MT2701.
> > >
> > > Signed-off-by: Dawei Chien <dawei.chien@mediatek.com>
> > > Signed-off-by: Erin Lo <erin.lo@mediatek.com>
> > > ---
> > >  arch/arm/boot/dts/mt2701.dtsi | 43 +++++++++++++++++++++++++++++++++++++++++++
> > >  1 file changed, 43 insertions(+)
> > >
> > > diff --git a/arch/arm/boot/dts/mt2701.dtsi b/arch/arm/boot/dts/mt2701.dtsi
> > > index 3847f70..c43d5f8 100644
> > > --- a/arch/arm/boot/dts/mt2701.dtsi
> > > +++ b/arch/arm/boot/dts/mt2701.dtsi
> > > @@ -89,6 +89,36 @@
> > >  		clock-output-names = "rtc32k";
> > >  	};
> > >
> > > +	thermal-zones {
> > > +		cpu_thermal: cpu_thermal {
> > > +			polling-delay-passive = <1000>; /* milliseconds */
> > > +			polling-delay = <1000>; /* milliseconds */
> > > +
> > > +			thermal-sensors = <&thermal 0>;
> > > +			sustainable-power = <1000>;
> > > +
> > > +			trips {
> > > +				threshold: trip-point@0 {
> > > +					temperature = <68000>;
> > > +					hysteresis = <2000>;
> > > +					type = "passive";
> > > +				};
> > > +
> > > +				target: trip-point@1 {
> > > +					temperature = <85000>;
> > > +					hysteresis = <2000>;
> > > +					type = "passive";
> > > +				};
> > > +
> > > +				cpu_crit: cpu_crit@0 {
> > > +					temperature = <115000>;
> > > +					hysteresis = <2000>;
> > > +					type = "critical";
> > > +				};
> > > +			};
> > > +		};
> > > +	};
> > > +
> > >  	timer {
> > >  		compatible = "arm,armv7-timer";
> > >  		interrupt-parent = <&gic>;
> > > @@ -270,6 +300,19 @@
> > >  		status = "disabled";
> > >  	};
> > >
> > > +	thermal: thermal@1100b000 {
> > > +		#thermal-sensor-cells = <0>;
> > > +		compatible = "mediatek,mt2701-thermal";
> > > +		reg = <0 0x1100b000 0 0x1000>;
> > > +		interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_LOW>;
> > > +		clocks = <&pericfg CLK_PERI_THERM>, <&pericfg CLK_PERI_AUXADC>;
> > > +		clock-names = "therm", "auxadc";
> > > +		resets = <&pericfg 0x10>;
> > 
> > should be MT2701_PERI_AUXADC_SW_RST, right?
> > 
> Thank you for your reminding, I didn't realize mt2701-resets.h upstream
> already, I would update on next version, thank you.
> 
> resets = <&pericfg MT2701_PERI_AUXADC_SW_RST>;

Actually, Should be MT2701_PERI_THERM_SW_RST.

resets = <&pericfg MT2701_PERI_THERM_SW_RST>;

> > > +		reset-names = "therm";
> > > +		mediatek,auxadc = <&auxadc>;
> > > +		mediatek,apmixedsys = <&apmixedsys>;
> > > +	};
> > > +
> > >  	nandc: nfi@1100d000 {
> > >  		compatible = "mediatek,mt2701-nfc";
> > >  		reg = <0 0x1100d000 0 0x1000>;
> > >
> 

Re: [PATCH v2 6/6] arm: dts: mt2701: Add thermal device node.

[Dawei Chien]

On Mon, 2017-01-16 at 11:44 +0800, Dawei Chien wrote:
> On Fri, 2017-01-13 at 16:27 +0100, Matthias Brugger wrote:
> > 
> > On 13/01/17 09:42, Erin Lo wrote:
> > > From: Dawei Chien <dawei.chien-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org>
> > >
> > > Add thermal controller device nodes for MT2701.
> > >
> > > Signed-off-by: Dawei Chien <dawei.chien-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org>
> > > Signed-off-by: Erin Lo <erin.lo-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org>
> > > ---
> > >  arch/arm/boot/dts/mt2701.dtsi | 43 +++++++++++++++++++++++++++++++++++++++++++
> > >  1 file changed, 43 insertions(+)
> > >
> > > diff --git a/arch/arm/boot/dts/mt2701.dtsi b/arch/arm/boot/dts/mt2701.dtsi
> > > index 3847f70..c43d5f8 100644
> > > --- a/arch/arm/boot/dts/mt2701.dtsi
> > > +++ b/arch/arm/boot/dts/mt2701.dtsi
> > > @@ -89,6 +89,36 @@
> > >  		clock-output-names = "rtc32k";
> > >  	};
> > >
> > > +	thermal-zones {
> > > +		cpu_thermal: cpu_thermal {
> > > +			polling-delay-passive = <1000>; /* milliseconds */
> > > +			polling-delay = <1000>; /* milliseconds */
> > > +
> > > +			thermal-sensors = <&thermal 0>;
> > > +			sustainable-power = <1000>;
> > > +
> > > +			trips {
> > > +				threshold: trip-point@0 {
> > > +					temperature = <68000>;
> > > +					hysteresis = <2000>;
> > > +					type = "passive";
> > > +				};
> > > +
> > > +				target: trip-point@1 {
> > > +					temperature = <85000>;
> > > +					hysteresis = <2000>;
> > > +					type = "passive";
> > > +				};
> > > +
> > > +				cpu_crit: cpu_crit@0 {
> > > +					temperature = <115000>;
> > > +					hysteresis = <2000>;
> > > +					type = "critical";
> > > +				};
> > > +			};
> > > +		};
> > > +	};
> > > +
> > >  	timer {
> > >  		compatible = "arm,armv7-timer";
> > >  		interrupt-parent = <&gic>;
> > > @@ -270,6 +300,19 @@
> > >  		status = "disabled";
> > >  	};
> > >
> > > +	thermal: thermal@1100b000 {
> > > +		#thermal-sensor-cells = <0>;
> > > +		compatible = "mediatek,mt2701-thermal";
> > > +		reg = <0 0x1100b000 0 0x1000>;
> > > +		interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_LOW>;
> > > +		clocks = <&pericfg CLK_PERI_THERM>, <&pericfg CLK_PERI_AUXADC>;
> > > +		clock-names = "therm", "auxadc";
> > > +		resets = <&pericfg 0x10>;
> > 
> > should be MT2701_PERI_AUXADC_SW_RST, right?
> > 
> Thank you for your reminding, I didn't realize mt2701-resets.h upstream
> already, I would update on next version, thank you.
> 
> resets = <&pericfg MT2701_PERI_AUXADC_SW_RST>;

Actually, Should be MT2701_PERI_THERM_SW_RST.

resets = <&pericfg MT2701_PERI_THERM_SW_RST>;

> > > +		reset-names = "therm";
> > > +		mediatek,auxadc = <&auxadc>;
> > > +		mediatek,apmixedsys = <&apmixedsys>;
> > > +	};
> > > +
> > >  	nandc: nfi@1100d000 {
> > >  		compatible = "mediatek,mt2701-nfc";
> > >  		reg = <0 0x1100d000 0 0x1000>;
> > >
> 


--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
More majordomo info at  http://vger.kernel.org/majordomo-info.html

[PATCH v2 6/6] arm: dts: mt2701: Add thermal device node.

[Dawei Chien]

On Mon, 2017-01-16 at 11:44 +0800, Dawei Chien wrote:
> On Fri, 2017-01-13 at 16:27 +0100, Matthias Brugger wrote:
> > 
> > On 13/01/17 09:42, Erin Lo wrote:
> > > From: Dawei Chien <dawei.chien@mediatek.com>
> > >
> > > Add thermal controller device nodes for MT2701.
> > >
> > > Signed-off-by: Dawei Chien <dawei.chien@mediatek.com>
> > > Signed-off-by: Erin Lo <erin.lo@mediatek.com>
> > > ---
> > >  arch/arm/boot/dts/mt2701.dtsi | 43 +++++++++++++++++++++++++++++++++++++++++++
> > >  1 file changed, 43 insertions(+)
> > >
> > > diff --git a/arch/arm/boot/dts/mt2701.dtsi b/arch/arm/boot/dts/mt2701.dtsi
> > > index 3847f70..c43d5f8 100644
> > > --- a/arch/arm/boot/dts/mt2701.dtsi
> > > +++ b/arch/arm/boot/dts/mt2701.dtsi
> > > @@ -89,6 +89,36 @@
> > >  		clock-output-names = "rtc32k";
> > >  	};
> > >
> > > +	thermal-zones {
> > > +		cpu_thermal: cpu_thermal {
> > > +			polling-delay-passive = <1000>; /* milliseconds */
> > > +			polling-delay = <1000>; /* milliseconds */
> > > +
> > > +			thermal-sensors = <&thermal 0>;
> > > +			sustainable-power = <1000>;
> > > +
> > > +			trips {
> > > +				threshold: trip-point at 0 {
> > > +					temperature = <68000>;
> > > +					hysteresis = <2000>;
> > > +					type = "passive";
> > > +				};
> > > +
> > > +				target: trip-point at 1 {
> > > +					temperature = <85000>;
> > > +					hysteresis = <2000>;
> > > +					type = "passive";
> > > +				};
> > > +
> > > +				cpu_crit: cpu_crit at 0 {
> > > +					temperature = <115000>;
> > > +					hysteresis = <2000>;
> > > +					type = "critical";
> > > +				};
> > > +			};
> > > +		};
> > > +	};
> > > +
> > >  	timer {
> > >  		compatible = "arm,armv7-timer";
> > >  		interrupt-parent = <&gic>;
> > > @@ -270,6 +300,19 @@
> > >  		status = "disabled";
> > >  	};
> > >
> > > +	thermal: thermal at 1100b000 {
> > > +		#thermal-sensor-cells = <0>;
> > > +		compatible = "mediatek,mt2701-thermal";
> > > +		reg = <0 0x1100b000 0 0x1000>;
> > > +		interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_LOW>;
> > > +		clocks = <&pericfg CLK_PERI_THERM>, <&pericfg CLK_PERI_AUXADC>;
> > > +		clock-names = "therm", "auxadc";
> > > +		resets = <&pericfg 0x10>;
> > 
> > should be MT2701_PERI_AUXADC_SW_RST, right?
> > 
> Thank you for your reminding, I didn't realize mt2701-resets.h upstream
> already, I would update on next version, thank you.
> 
> resets = <&pericfg MT2701_PERI_AUXADC_SW_RST>;

Actually, Should be MT2701_PERI_THERM_SW_RST.

resets = <&pericfg MT2701_PERI_THERM_SW_RST>;

> > > +		reset-names = "therm";
> > > +		mediatek,auxadc = <&auxadc>;
> > > +		mediatek,apmixedsys = <&apmixedsys>;
> > > +	};
> > > +
> > >  	nandc: nfi at 1100d000 {
> > >  		compatible = "mediatek,mt2701-nfc";
> > >  		reg = <0 0x1100d000 0 0x1000>;
> > >
>