From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751844AbdARGCI (ORCPT ); Wed, 18 Jan 2017 01:02:08 -0500 Received: from mailgw01.mediatek.com ([210.61.82.183]:24970 "EHLO mailgw01.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1751358AbdARGAq (ORCPT ); Wed, 18 Jan 2017 01:00:46 -0500 From: Chunfeng Yun To: Kishon Vijay Abraham I CC: Matthias Brugger , Felipe Balbi , Rob Herring , Mark Rutland , Ian Campbell , Chunfeng Yun , , , , , Subject: [RESEND PATCH 6/6] dt-bindings: phy-mt65xx-usb: add support for mt2712 platform Date: Wed, 18 Jan 2017 14:00:14 +0800 Message-ID: <1484719214-11989-6-git-send-email-chunfeng.yun@mediatek.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1484719214-11989-1-git-send-email-chunfeng.yun@mediatek.com> References: <1484719214-11989-1-git-send-email-chunfeng.yun@mediatek.com> MIME-Version: 1.0 Content-Type: text/plain X-MTK: N Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org add a new compatible string for "mt2712", and a new reference clock for SuperSpeed analog phy; Signed-off-by: Chunfeng Yun --- .../devicetree/bindings/phy/phy-mt65xx-usb.txt | 81 +++++++++++++++++--- 1 file changed, 70 insertions(+), 11 deletions(-) diff --git a/Documentation/devicetree/bindings/phy/phy-mt65xx-usb.txt b/Documentation/devicetree/bindings/phy/phy-mt65xx-usb.txt index 33a2b1e..8f91136 100644 --- a/Documentation/devicetree/bindings/phy/phy-mt65xx-usb.txt +++ b/Documentation/devicetree/bindings/phy/phy-mt65xx-usb.txt @@ -6,19 +6,25 @@ This binding describes a usb3.0 phy for mt65xx platforms of Medaitek SoC. Required properties (controller (parent) node): - compatible : should be one of "mediatek,mt2701-u3phy" + "mediatek,mt2712-u3phy" "mediatek,mt8173-u3phy" - - reg : offset and length of register for phy, exclude port's - register. - clocks : a list of phandle + clock-specifier pairs, one for each entry in clock-names - clock-names : must contain - "u3phya_ref": for reference clock of usb3.0 analog phy. + "u2ref_clk": 48M reference clock of HighSpeed analog phy. + "u3ref_clk": 26M reference clock of SuperSpeed analog phy, + sometimes is 24M, 25M or 27M, depended on platform. Required nodes : a sub-node is required for each port the controller provides. Address range information including the usual 'reg' property is used inside these nodes to describe the controller's topology. +Optional properties (controller (parent) node): + - reg : offset and length of register shared by multiple ports, + exclude port's private register. It is needed on mt2701 + and mt8173, but not on mt2712. + Required properties (port (child) node): - reg : address and length of the register set for the port. - #phy-cells : should be 1 (See second example) @@ -31,21 +37,27 @@ Example: u3phy: usb-phy@11290000 { compatible = "mediatek,mt8173-u3phy"; reg = <0 0x11290000 0 0x800>; - clocks = <&apmixedsys CLK_APMIXED_REF2USB_TX>; - clock-names = "u3phya_ref"; + clocks = <&apmixedsys CLK_APMIXED_REF2USB_TX>, <&clk26m>; + clock-names = "u2ref_clk", "u3ref_clk"; #address-cells = <2>; #size-cells = <2>; ranges; status = "okay"; - phy_port0: port@11290800 { - reg = <0 0x11290800 0 0x800>; + u2port0: port@11290800 { + reg = <0 0x11290800 0 0x100>; + #phy-cells = <1>; + status = "okay"; + }; + + u3port0: port@11290900 { + reg = <0 0x11290800 0 0x700>; #phy-cells = <1>; status = "okay"; }; - phy_port1: port@11291000 { - reg = <0 0x11291000 0 0x800>; + u2port1: port@11291000 { + reg = <0 0x11291000 0 0x100>; #phy-cells = <1>; status = "okay"; }; @@ -64,7 +76,54 @@ Example: usb30: usb@11270000 { ... - phys = <&phy_port0 PHY_TYPE_USB3>; - phy-names = "usb3-0"; + phys = <&u2port0 PHY_TYPE_USB2>, <&u3port0 PHY_TYPE_USB3>; + phy-names = "usb2-0", "usb3-0"; ... }; + + +Layout differences of banks between mt8173/mt2701 and mt2712 +------------------------------------------------------------- +mt8173 and mt2701: +port offset bank +shared 0x0000 SPLLC + 0x0100 FMREG +u2 port0 0x0800 U2PHY_COM +u3 port0 0x0900 U3PHYD + 0x0a00 U3PHYD_BANK2 + 0x0b00 U3PHYA + 0x0c00 U3PHYA_DA +u2 port1 0x1000 U2PHY_COM +u3 port1 0x1100 U3PHYD + 0x1200 U3PHYD_BANK2 + 0x1300 U3PHYA + 0x1400 U3PHYA_DA +u2 port2 0x1800 U2PHY_COM + ... + +mt2712: +port offset bank +u2 port0 0x0000 MISC + 0x0100 FMREG + 0x0300 U2PHY_COM +u3 port0 0x0700 SPLLC + 0x0800 CHIP + 0x0900 U3PHYD + 0x0a00 U3PHYD_BANK2 + 0x0b00 U3PHYA + 0x0c00 U3PHYA_DA +u2 port1 0x1000 MISC + 0x1100 FMREG + 0x1300 U2PHY_COM +u3 port1 0x1700 SPLLC + 0x1800 CHIP + 0x1900 U3PHYD + 0x1a00 U3PHYD_BANK2 + 0x1b00 U3PHYA + 0x1c00 U3PHYA_DA +u2 port2 0x2000 MISC + ... + + SPLLC shared by u3 ports and FMREG shared by u2 ports on +mt8173/mt2701 are put back into each port; a new bank MISC for +u2 ports and CHIP for u3 ports are added on mt2712. -- 1.7.9.5 From mboxrd@z Thu Jan 1 00:00:00 1970 From: Chunfeng Yun Subject: [RESEND PATCH 6/6] dt-bindings: phy-mt65xx-usb: add support for mt2712 platform Date: Wed, 18 Jan 2017 14:00:14 +0800 Message-ID: <1484719214-11989-6-git-send-email-chunfeng.yun@mediatek.com> References: <1484719214-11989-1-git-send-email-chunfeng.yun@mediatek.com> Mime-Version: 1.0 Content-Type: text/plain Return-path: In-Reply-To: <1484719214-11989-1-git-send-email-chunfeng.yun-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org> Sender: devicetree-owner-u79uwXL29TY76Z2rM5mHXA@public.gmane.org To: Kishon Vijay Abraham I Cc: Matthias Brugger , Felipe Balbi , Rob Herring , Mark Rutland , Ian Campbell , Chunfeng Yun , linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org, linux-usb-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-mediatek-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org, devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org List-Id: devicetree@vger.kernel.org add a new compatible string for "mt2712", and a new reference clock for SuperSpeed analog phy; Signed-off-by: Chunfeng Yun --- .../devicetree/bindings/phy/phy-mt65xx-usb.txt | 81 +++++++++++++++++--- 1 file changed, 70 insertions(+), 11 deletions(-) diff --git a/Documentation/devicetree/bindings/phy/phy-mt65xx-usb.txt b/Documentation/devicetree/bindings/phy/phy-mt65xx-usb.txt index 33a2b1e..8f91136 100644 --- a/Documentation/devicetree/bindings/phy/phy-mt65xx-usb.txt +++ b/Documentation/devicetree/bindings/phy/phy-mt65xx-usb.txt @@ -6,19 +6,25 @@ This binding describes a usb3.0 phy for mt65xx platforms of Medaitek SoC. Required properties (controller (parent) node): - compatible : should be one of "mediatek,mt2701-u3phy" + "mediatek,mt2712-u3phy" "mediatek,mt8173-u3phy" - - reg : offset and length of register for phy, exclude port's - register. - clocks : a list of phandle + clock-specifier pairs, one for each entry in clock-names - clock-names : must contain - "u3phya_ref": for reference clock of usb3.0 analog phy. + "u2ref_clk": 48M reference clock of HighSpeed analog phy. + "u3ref_clk": 26M reference clock of SuperSpeed analog phy, + sometimes is 24M, 25M or 27M, depended on platform. Required nodes : a sub-node is required for each port the controller provides. Address range information including the usual 'reg' property is used inside these nodes to describe the controller's topology. +Optional properties (controller (parent) node): + - reg : offset and length of register shared by multiple ports, + exclude port's private register. It is needed on mt2701 + and mt8173, but not on mt2712. + Required properties (port (child) node): - reg : address and length of the register set for the port. - #phy-cells : should be 1 (See second example) @@ -31,21 +37,27 @@ Example: u3phy: usb-phy@11290000 { compatible = "mediatek,mt8173-u3phy"; reg = <0 0x11290000 0 0x800>; - clocks = <&apmixedsys CLK_APMIXED_REF2USB_TX>; - clock-names = "u3phya_ref"; + clocks = <&apmixedsys CLK_APMIXED_REF2USB_TX>, <&clk26m>; + clock-names = "u2ref_clk", "u3ref_clk"; #address-cells = <2>; #size-cells = <2>; ranges; status = "okay"; - phy_port0: port@11290800 { - reg = <0 0x11290800 0 0x800>; + u2port0: port@11290800 { + reg = <0 0x11290800 0 0x100>; + #phy-cells = <1>; + status = "okay"; + }; + + u3port0: port@11290900 { + reg = <0 0x11290800 0 0x700>; #phy-cells = <1>; status = "okay"; }; - phy_port1: port@11291000 { - reg = <0 0x11291000 0 0x800>; + u2port1: port@11291000 { + reg = <0 0x11291000 0 0x100>; #phy-cells = <1>; status = "okay"; }; @@ -64,7 +76,54 @@ Example: usb30: usb@11270000 { ... - phys = <&phy_port0 PHY_TYPE_USB3>; - phy-names = "usb3-0"; + phys = <&u2port0 PHY_TYPE_USB2>, <&u3port0 PHY_TYPE_USB3>; + phy-names = "usb2-0", "usb3-0"; ... }; + + +Layout differences of banks between mt8173/mt2701 and mt2712 +------------------------------------------------------------- +mt8173 and mt2701: +port offset bank +shared 0x0000 SPLLC + 0x0100 FMREG +u2 port0 0x0800 U2PHY_COM +u3 port0 0x0900 U3PHYD + 0x0a00 U3PHYD_BANK2 + 0x0b00 U3PHYA + 0x0c00 U3PHYA_DA +u2 port1 0x1000 U2PHY_COM +u3 port1 0x1100 U3PHYD + 0x1200 U3PHYD_BANK2 + 0x1300 U3PHYA + 0x1400 U3PHYA_DA +u2 port2 0x1800 U2PHY_COM + ... + +mt2712: +port offset bank +u2 port0 0x0000 MISC + 0x0100 FMREG + 0x0300 U2PHY_COM +u3 port0 0x0700 SPLLC + 0x0800 CHIP + 0x0900 U3PHYD + 0x0a00 U3PHYD_BANK2 + 0x0b00 U3PHYA + 0x0c00 U3PHYA_DA +u2 port1 0x1000 MISC + 0x1100 FMREG + 0x1300 U2PHY_COM +u3 port1 0x1700 SPLLC + 0x1800 CHIP + 0x1900 U3PHYD + 0x1a00 U3PHYD_BANK2 + 0x1b00 U3PHYA + 0x1c00 U3PHYA_DA +u2 port2 0x2000 MISC + ... + + SPLLC shared by u3 ports and FMREG shared by u2 ports on +mt8173/mt2701 are put back into each port; a new bank MISC for +u2 ports and CHIP for u3 ports are added on mt2712. -- 1.7.9.5 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org More majordomo info at http://vger.kernel.org/majordomo-info.html From mboxrd@z Thu Jan 1 00:00:00 1970 From: chunfeng.yun@mediatek.com (Chunfeng Yun) Date: Wed, 18 Jan 2017 14:00:14 +0800 Subject: [RESEND PATCH 6/6] dt-bindings: phy-mt65xx-usb: add support for mt2712 platform In-Reply-To: <1484719214-11989-1-git-send-email-chunfeng.yun@mediatek.com> References: <1484719214-11989-1-git-send-email-chunfeng.yun@mediatek.com> Message-ID: <1484719214-11989-6-git-send-email-chunfeng.yun@mediatek.com> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org add a new compatible string for "mt2712", and a new reference clock for SuperSpeed analog phy; Signed-off-by: Chunfeng Yun --- .../devicetree/bindings/phy/phy-mt65xx-usb.txt | 81 +++++++++++++++++--- 1 file changed, 70 insertions(+), 11 deletions(-) diff --git a/Documentation/devicetree/bindings/phy/phy-mt65xx-usb.txt b/Documentation/devicetree/bindings/phy/phy-mt65xx-usb.txt index 33a2b1e..8f91136 100644 --- a/Documentation/devicetree/bindings/phy/phy-mt65xx-usb.txt +++ b/Documentation/devicetree/bindings/phy/phy-mt65xx-usb.txt @@ -6,19 +6,25 @@ This binding describes a usb3.0 phy for mt65xx platforms of Medaitek SoC. Required properties (controller (parent) node): - compatible : should be one of "mediatek,mt2701-u3phy" + "mediatek,mt2712-u3phy" "mediatek,mt8173-u3phy" - - reg : offset and length of register for phy, exclude port's - register. - clocks : a list of phandle + clock-specifier pairs, one for each entry in clock-names - clock-names : must contain - "u3phya_ref": for reference clock of usb3.0 analog phy. + "u2ref_clk": 48M reference clock of HighSpeed analog phy. + "u3ref_clk": 26M reference clock of SuperSpeed analog phy, + sometimes is 24M, 25M or 27M, depended on platform. Required nodes : a sub-node is required for each port the controller provides. Address range information including the usual 'reg' property is used inside these nodes to describe the controller's topology. +Optional properties (controller (parent) node): + - reg : offset and length of register shared by multiple ports, + exclude port's private register. It is needed on mt2701 + and mt8173, but not on mt2712. + Required properties (port (child) node): - reg : address and length of the register set for the port. - #phy-cells : should be 1 (See second example) @@ -31,21 +37,27 @@ Example: u3phy: usb-phy at 11290000 { compatible = "mediatek,mt8173-u3phy"; reg = <0 0x11290000 0 0x800>; - clocks = <&apmixedsys CLK_APMIXED_REF2USB_TX>; - clock-names = "u3phya_ref"; + clocks = <&apmixedsys CLK_APMIXED_REF2USB_TX>, <&clk26m>; + clock-names = "u2ref_clk", "u3ref_clk"; #address-cells = <2>; #size-cells = <2>; ranges; status = "okay"; - phy_port0: port at 11290800 { - reg = <0 0x11290800 0 0x800>; + u2port0: port at 11290800 { + reg = <0 0x11290800 0 0x100>; + #phy-cells = <1>; + status = "okay"; + }; + + u3port0: port at 11290900 { + reg = <0 0x11290800 0 0x700>; #phy-cells = <1>; status = "okay"; }; - phy_port1: port at 11291000 { - reg = <0 0x11291000 0 0x800>; + u2port1: port at 11291000 { + reg = <0 0x11291000 0 0x100>; #phy-cells = <1>; status = "okay"; }; @@ -64,7 +76,54 @@ Example: usb30: usb at 11270000 { ... - phys = <&phy_port0 PHY_TYPE_USB3>; - phy-names = "usb3-0"; + phys = <&u2port0 PHY_TYPE_USB2>, <&u3port0 PHY_TYPE_USB3>; + phy-names = "usb2-0", "usb3-0"; ... }; + + +Layout differences of banks between mt8173/mt2701 and mt2712 +------------------------------------------------------------- +mt8173 and mt2701: +port offset bank +shared 0x0000 SPLLC + 0x0100 FMREG +u2 port0 0x0800 U2PHY_COM +u3 port0 0x0900 U3PHYD + 0x0a00 U3PHYD_BANK2 + 0x0b00 U3PHYA + 0x0c00 U3PHYA_DA +u2 port1 0x1000 U2PHY_COM +u3 port1 0x1100 U3PHYD + 0x1200 U3PHYD_BANK2 + 0x1300 U3PHYA + 0x1400 U3PHYA_DA +u2 port2 0x1800 U2PHY_COM + ... + +mt2712: +port offset bank +u2 port0 0x0000 MISC + 0x0100 FMREG + 0x0300 U2PHY_COM +u3 port0 0x0700 SPLLC + 0x0800 CHIP + 0x0900 U3PHYD + 0x0a00 U3PHYD_BANK2 + 0x0b00 U3PHYA + 0x0c00 U3PHYA_DA +u2 port1 0x1000 MISC + 0x1100 FMREG + 0x1300 U2PHY_COM +u3 port1 0x1700 SPLLC + 0x1800 CHIP + 0x1900 U3PHYD + 0x1a00 U3PHYD_BANK2 + 0x1b00 U3PHYA + 0x1c00 U3PHYA_DA +u2 port2 0x2000 MISC + ... + + SPLLC shared by u3 ports and FMREG shared by u2 ports on +mt8173/mt2701 are put back into each port; a new bank MISC for +u2 ports and CHIP for u3 ports are added on mt2712. -- 1.7.9.5