* [linux-fslc][PATCH 0/2] i.MX7: Fix LPSR specific iomux pins
@ 2017-01-23 14:36 Vanessa Maegima
2017-01-23 14:36 ` [linux-fslc][PATCH 1/2] ARM: dts: imx7: Add "LPSR" to LPSR iomux pin names Vanessa Maegima
2017-01-23 14:36 ` [linux-fslc][PATCH 2/2] ARM: dts: imx7s-warp: Add watchdog pinmux Vanessa Maegima
0 siblings, 2 replies; 3+ messages in thread
From: Vanessa Maegima @ 2017-01-23 14:36 UTC (permalink / raw)
To: meta-freescale; +Cc: Vanessa Maegima
Add "LPSR" to the pin names which belong to the LPSR controller. Based
on Sascha Hauer's patch set (https://www.spinics.net/lists/arm-kernel/msg555844.html).
This patch set works for 4.1-2.0.x-imx and 4.1-1.0.x-imx branches.
Vanessa Maegima (2):
ARM: dts: imx7: Add "LPSR" to LPSR iomux pin names
ARM: dts: imx7s-warp: Add watchdog pinmux
arch/arm/boot/dts/imx7d-12x12-ddr3-arm2.dts | 14 ++--
arch/arm/boot/dts/imx7d-12x12-lpddr3-arm2.dts | 8 +-
arch/arm/boot/dts/imx7d-19x19-lpddr2-arm2.dts | 6 +-
arch/arm/boot/dts/imx7d-pinfunc-lpsr.h | 110 +++++++++++++-------------
arch/arm/boot/dts/imx7d-sdb.dts | 12 +--
arch/arm/boot/dts/imx7s-warp.dts | 8 ++
6 files changed, 83 insertions(+), 75 deletions(-)
--
2.7.4
^ permalink raw reply [flat|nested] 3+ messages in thread
* [linux-fslc][PATCH 1/2] ARM: dts: imx7: Add "LPSR" to LPSR iomux pin names
2017-01-23 14:36 [linux-fslc][PATCH 0/2] i.MX7: Fix LPSR specific iomux pins Vanessa Maegima
@ 2017-01-23 14:36 ` Vanessa Maegima
2017-01-23 14:36 ` [linux-fslc][PATCH 2/2] ARM: dts: imx7s-warp: Add watchdog pinmux Vanessa Maegima
1 sibling, 0 replies; 3+ messages in thread
From: Vanessa Maegima @ 2017-01-23 14:36 UTC (permalink / raw)
To: meta-freescale; +Cc: Sascha Hauer, Vanessa Maegima
From: Sascha Hauer <s.hauer@pengutronix.de>
The i.MX7 has two iomux controllers, the iomuxc and the iomuxc_lpsr.
In a board dts we have to make sure that both controllers are supplied
with the correct pins. It's way too easy to do this wrong since only
a look into the reference manual can reveal which pins belong to which
controller. To make this clearer, add "LPSR" to the pin names which
belong to the LPSR controller.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: Vanessa Maegima <vanessa.maegima@nxp.com>
---
arch/arm/boot/dts/imx7d-12x12-ddr3-arm2.dts | 14 ++--
arch/arm/boot/dts/imx7d-12x12-lpddr3-arm2.dts | 8 +-
arch/arm/boot/dts/imx7d-19x19-lpddr2-arm2.dts | 6 +-
arch/arm/boot/dts/imx7d-pinfunc-lpsr.h | 110 +++++++++++++-------------
arch/arm/boot/dts/imx7d-sdb.dts | 12 +--
5 files changed, 75 insertions(+), 75 deletions(-)
diff --git a/arch/arm/boot/dts/imx7d-12x12-ddr3-arm2.dts b/arch/arm/boot/dts/imx7d-12x12-ddr3-arm2.dts
index 8626f3b..5d17ab0 100644
--- a/arch/arm/boot/dts/imx7d-12x12-ddr3-arm2.dts
+++ b/arch/arm/boot/dts/imx7d-12x12-ddr3-arm2.dts
@@ -436,23 +436,23 @@
imx7d-12x12-ddr3-arm2 {
pinctrl_hog_2: hoggrp-2 {
fsl,pins = <
- MX7D_PAD_GPIO1_IO02__GPIO1_IO2 0x59 /* flexcan stby1 */
- MX7D_PAD_GPIO1_IO03__GPIO1_IO3 0x59 /* flexcan stby2 */
- MX7D_PAD_GPIO1_IO01__ANATOP_24M_OUT 0x80000000
+ MX7D_PAD_LPSR_GPIO1_IO02__GPIO1_IO2 0x59 /* flexcan stby1 */
+ MX7D_PAD_LPSR_GPIO1_IO03__GPIO1_IO3 0x59 /* flexcan stby2 */
+ MX7D_PAD_LPSR_GPIO1_IO01__ANATOP_24M_OUT 0x80000000
>;
};
pinctrl_i2c1_1: i2c1grp-1 {
fsl,pins = <
- MX7D_PAD_GPIO1_IO04__I2C1_SCL 0x4000007f
- MX7D_PAD_GPIO1_IO05__I2C1_SDA 0x4000007f
+ MX7D_PAD_LPSR_GPIO1_IO04__I2C1_SCL 0x4000007f
+ MX7D_PAD_LPSR_GPIO1_IO05__I2C1_SDA 0x4000007f
>;
};
pinctrl_i2c2_1: i2c2grp-1 {
fsl,pins = <
- MX7D_PAD_GPIO1_IO06__I2C2_SCL 0x4000007f
- MX7D_PAD_GPIO1_IO07__I2C2_SDA 0x4000007f
+ MX7D_PAD_LPSR_GPIO1_IO06__I2C2_SCL 0x4000007f
+ MX7D_PAD_LPSR_GPIO1_IO07__I2C2_SDA 0x4000007f
>;
};
};
diff --git a/arch/arm/boot/dts/imx7d-12x12-lpddr3-arm2.dts b/arch/arm/boot/dts/imx7d-12x12-lpddr3-arm2.dts
index eb4af7d..350ebe0 100644
--- a/arch/arm/boot/dts/imx7d-12x12-lpddr3-arm2.dts
+++ b/arch/arm/boot/dts/imx7d-12x12-lpddr3-arm2.dts
@@ -840,7 +840,7 @@
imx7d-12x12-lpddr3-arm2 {
pinctrl_pwm1: pwm1grp {
fsl,pins = <
- MX7D_PAD_GPIO1_IO01__PWM1_OUT 0x30
+ MX7D_PAD_LPSR_GPIO1_IO01__PWM1_OUT 0x30
>;
};
};
@@ -848,19 +848,19 @@
imx7d-sdb {
pinctrl_usbotg1_vbus: usbotg1vbusgrp {
fsl,pins = <
- MX7D_PAD_GPIO1_IO05__GPIO1_IO5 0x14
+ MX7D_PAD_LPSR_GPIO1_IO05__GPIO1_IO5 0x14
>;
};
pinctrl_usbotg2_vbus: usbotg2vbusgrp {
fsl,pins = <
- MX7D_PAD_GPIO1_IO07__GPIO1_IO7 0x14
+ MX7D_PAD_LPSR_GPIO1_IO07__GPIO1_IO7 0x14
>;
};
pinctrl_wdog: wdoggrp {
fsl,pins = <
- MX7D_PAD_GPIO1_IO00__WDOD1_WDOG_B 0x74
+ MX7D_PAD_LPSR_GPIO1_IO00__WDOD1_WDOG_B 0x74
>;
};
};
diff --git a/arch/arm/boot/dts/imx7d-19x19-lpddr2-arm2.dts b/arch/arm/boot/dts/imx7d-19x19-lpddr2-arm2.dts
index 2af374c6..9234b16 100644
--- a/arch/arm/boot/dts/imx7d-19x19-lpddr2-arm2.dts
+++ b/arch/arm/boot/dts/imx7d-19x19-lpddr2-arm2.dts
@@ -380,9 +380,9 @@
imx7d-19x19-lpddr3-arm2 {
pinctrl_hog_2: hoggrp-2 {
fsl,pins = <
- MX7D_PAD_GPIO1_IO03__GPIO1_IO3 0x14
- MX7D_PAD_GPIO1_IO05__GPIO1_IO5 0x14
- MX7D_PAD_GPIO1_IO07__GPIO1_IO7 0x14
+ MX7D_PAD_LPSR_GPIO1_IO03__GPIO1_IO3 0x14
+ MX7D_PAD_LPSR_GPIO1_IO05__GPIO1_IO5 0x14
+ MX7D_PAD_LPSR_GPIO1_IO07__GPIO1_IO7 0x14
>;
};
};
diff --git a/arch/arm/boot/dts/imx7d-pinfunc-lpsr.h b/arch/arm/boot/dts/imx7d-pinfunc-lpsr.h
index 378694e..cd318a9 100644
--- a/arch/arm/boot/dts/imx7d-pinfunc-lpsr.h
+++ b/arch/arm/boot/dts/imx7d-pinfunc-lpsr.h
@@ -17,60 +17,60 @@
* NOTE: imx7d-lpsr pin groups should be put under &iomuxc_lpsr node when used
*/
-#define MX7D_PAD_GPIO1_IO00__GPIO1_IO0 0x0000 0x0030 0x0000 0x0 0x0
-#define MX7D_PAD_GPIO1_IO00__PWM4_OUT 0x0000 0x0030 0x0000 0x1 0x0
-#define MX7D_PAD_GPIO1_IO00__WDOD1_WDOG_ANY 0x0000 0x0030 0x0000 0x2 0x0
-#define MX7D_PAD_GPIO1_IO00__WDOD1_WDOG_B 0x0000 0x0030 0x0000 0x3 0x0
-#define MX7D_PAD_GPIO1_IO00__WDOD1_WDOG__RST_B_DEB 0x0000 0x0030 0x0000 0x4 0x0
-#define MX7D_PAD_GPIO1_IO01__GPIO1_IO1 0x0004 0x0034 0x0000 0x0 0x0
-#define MX7D_PAD_GPIO1_IO01__PWM1_OUT 0x0004 0x0034 0x0000 0x1 0x0
-#define MX7D_PAD_GPIO1_IO01__CCM_ENET_REF_CLK3 0x0004 0x0034 0x0000 0x2 0x0
-#define MX7D_PAD_GPIO1_IO01__SAI1_MCLK 0x0004 0x0034 0x0000 0x3 0x0
-#define MX7D_PAD_GPIO1_IO01__ANATOP_24M_OUT 0x0004 0x0034 0x0000 0x4 0x0
-#define MX7D_PAD_GPIO1_IO01__OBSERVE0_OUT 0x0004 0x0034 0x0000 0x6 0x0
-#define MX7D_PAD_GPIO1_IO02__GPIO1_IO2 0x0008 0x0038 0x0000 0x0 0x0
-#define MX7D_PAD_GPIO1_IO02__PWM2_OUT 0x0008 0x0038 0x0000 0x1 0x0
-#define MX7D_PAD_GPIO1_IO02__CCM_ENET_REF_CLK1 0x0008 0x0038 0x0564 0x2 0x3
-#define MX7D_PAD_GPIO1_IO02__SAI2_MCLK 0x0008 0x0038 0x0000 0x3 0x0
-#define MX7D_PAD_GPIO1_IO02__CCM_CLKO1 0x0008 0x0038 0x0000 0x5 0x0
-#define MX7D_PAD_GPIO1_IO02__OBSERVE1_OUT 0x0008 0x0038 0x0000 0x6 0x0
-#define MX7D_PAD_GPIO1_IO02__USB_OTG1_ID 0x0008 0x0038 0x0734 0x7 0x3
-#define MX7D_PAD_GPIO1_IO03__GPIO1_IO3 0x000C 0x003C 0x0000 0x0 0x0
-#define MX7D_PAD_GPIO1_IO03__PWM3_OUT 0x000C 0x003C 0x0000 0x1 0x0
-#define MX7D_PAD_GPIO1_IO03__CCM_ENET_REF_CLK2 0x000C 0x003C 0x0570 0x2 0x3
-#define MX7D_PAD_GPIO1_IO03__SAI3_MCLK 0x000C 0x003C 0x0000 0x3 0x0
-#define MX7D_PAD_GPIO1_IO03__CCM_CLKO2 0x000C 0x003C 0x0000 0x5 0x0
-#define MX7D_PAD_GPIO1_IO03__OBSERVE2_OUT 0x000C 0x003C 0x0000 0x6 0x0
-#define MX7D_PAD_GPIO1_IO03__USB_OTG2_ID 0x000C 0x003C 0x0730 0x7 0x3
-#define MX7D_PAD_GPIO1_IO04__GPIO1_IO4 0x0010 0x0040 0x0000 0x0 0x0
-#define MX7D_PAD_GPIO1_IO04__USB_OTG1_OC 0x0010 0x0040 0x072C 0x1 0x1
-#define MX7D_PAD_GPIO1_IO04__FLEXTIMER1_CH4 0x0010 0x0040 0x0594 0x2 0x1
-#define MX7D_PAD_GPIO1_IO04__UART5_DCE_CTS 0x0010 0x0040 0x0000 0x3 0x0
-#define MX7D_PAD_GPIO1_IO04__UART5_DTE_RTS 0x0010 0x0040 0x0710 0x3 0x4
-#define MX7D_PAD_GPIO1_IO04__I2C1_SCL 0x0010 0x0040 0x05D4 0x4 0x2
-#define MX7D_PAD_GPIO1_IO04__OBSERVE3_OUT 0x0010 0x0040 0x0000 0x6 0x0
-#define MX7D_PAD_GPIO1_IO05__GPIO1_IO5 0x0014 0x0044 0x0000 0x0 0x0
-#define MX7D_PAD_GPIO1_IO05__USB_OTG1_PWR 0x0014 0x0044 0x0000 0x1 0x0
-#define MX7D_PAD_GPIO1_IO05__FLEXTIMER1_CH5 0x0014 0x0044 0x0598 0x2 0x1
-#define MX7D_PAD_GPIO1_IO05__UART5_DCE_RTS 0x0014 0x0044 0x0710 0x3 0x5
-#define MX7D_PAD_GPIO1_IO05__UART5_DTE_CTS 0x0014 0x0044 0x0000 0x3 0x0
-#define MX7D_PAD_GPIO1_IO05__I2C1_SDA 0x0014 0x0044 0x05D8 0x4 0x2
-#define MX7D_PAD_GPIO1_IO05__OBSERVE4_OUT 0x0014 0x0044 0x0000 0x6 0x0
-#define MX7D_PAD_GPIO1_IO06__GPIO1_IO6 0x0018 0x0048 0x0000 0x0 0x0
-#define MX7D_PAD_GPIO1_IO06__USB_OTG2_OC 0x0018 0x0048 0x0728 0x1 0x1
-#define MX7D_PAD_GPIO1_IO06__FLEXTIMER1_CH6 0x0018 0x0048 0x059C 0x2 0x1
-#define MX7D_PAD_GPIO1_IO06__UART5_DCE_RX 0x0018 0x0048 0x0714 0x3 0x4
-#define MX7D_PAD_GPIO1_IO06__UART5_DTE_TX 0x0018 0x0048 0x0000 0x3 0x0
-#define MX7D_PAD_GPIO1_IO06__I2C2_SCL 0x0018 0x0048 0x05DC 0x4 0x2
-#define MX7D_PAD_GPIO1_IO06__CCM_WAIT 0x0018 0x0048 0x0000 0x5 0x0
-#define MX7D_PAD_GPIO1_IO06__KPP_ROW4 0x0018 0x0048 0x0624 0x6 0x1
-#define MX7D_PAD_GPIO1_IO07__GPIO1_IO7 0x001C 0x004C 0x0000 0x0 0x0
-#define MX7D_PAD_GPIO1_IO07__USB_OTG2_PWR 0x001C 0x004C 0x0000 0x1 0x0
-#define MX7D_PAD_GPIO1_IO07__FLEXTIMER1_CH7 0x001C 0x004C 0x05A0 0x2 0x1
-#define MX7D_PAD_GPIO1_IO07__UART5_DCE_TX 0x001C 0x004C 0x0000 0x3 0x0
-#define MX7D_PAD_GPIO1_IO07__UART5_DTE_RX 0x001C 0x004C 0x0714 0x3 0x5
-#define MX7D_PAD_GPIO1_IO07__I2C2_SDA 0x001C 0x004C 0x05E0 0x4 0x2
-#define MX7D_PAD_GPIO1_IO07__CCM_STOP 0x001C 0x004C 0x0000 0x5 0x0
-#define MX7D_PAD_GPIO1_IO07__KPP_COL4 0x001C 0x004C 0x0604 0x6 0x1
+#define MX7D_PAD_LPSR_GPIO1_IO00__GPIO1_IO0 0x0000 0x0030 0x0000 0x0 0x0
+#define MX7D_PAD_LPSR_GPIO1_IO00__PWM4_OUT 0x0000 0x0030 0x0000 0x1 0x0
+#define MX7D_PAD_LPSR_GPIO1_IO00__WDOD1_WDOG_ANY 0x0000 0x0030 0x0000 0x2 0x0
+#define MX7D_PAD_LPSR_GPIO1_IO00__WDOD1_WDOG_B 0x0000 0x0030 0x0000 0x3 0x0
+#define MX7D_PAD_LPSR_GPIO1_IO00__WDOD1_WDOG__RST_B_DEB 0x0000 0x0030 0x0000 0x4 0x0
+#define MX7D_PAD_LPSR_GPIO1_IO01__GPIO1_IO1 0x0004 0x0034 0x0000 0x0 0x0
+#define MX7D_PAD_LPSR_GPIO1_IO01__PWM1_OUT 0x0004 0x0034 0x0000 0x1 0x0
+#define MX7D_PAD_LPSR_GPIO1_IO01__CCM_ENET_REF_CLK3 0x0004 0x0034 0x0000 0x2 0x0
+#define MX7D_PAD_LPSR_GPIO1_IO01__SAI1_MCLK 0x0004 0x0034 0x0000 0x3 0x0
+#define MX7D_PAD_LPSR_GPIO1_IO01__ANATOP_24M_OUT 0x0004 0x0034 0x0000 0x4 0x0
+#define MX7D_PAD_LPSR_GPIO1_IO01__OBSERVE0_OUT 0x0004 0x0034 0x0000 0x6 0x0
+#define MX7D_PAD_LPSR_GPIO1_IO02__GPIO1_IO2 0x0008 0x0038 0x0000 0x0 0x0
+#define MX7D_PAD_LPSR_GPIO1_IO02__PWM2_OUT 0x0008 0x0038 0x0000 0x1 0x0
+#define MX7D_PAD_LPSR_GPIO1_IO02__CCM_ENET_REF_CLK1 0x0008 0x0038 0x0564 0x2 0x3
+#define MX7D_PAD_LPSR_GPIO1_IO02__SAI2_MCLK 0x0008 0x0038 0x0000 0x3 0x0
+#define MX7D_PAD_LPSR_GPIO1_IO02__CCM_CLKO1 0x0008 0x0038 0x0000 0x5 0x0
+#define MX7D_PAD_LPSR_GPIO1_IO02__OBSERVE1_OUT 0x0008 0x0038 0x0000 0x6 0x0
+#define MX7D_PAD_LPSR_GPIO1_IO02__USB_OTG1_ID 0x0008 0x0038 0x0734 0x7 0x3
+#define MX7D_PAD_LPSR_GPIO1_IO03__GPIO1_IO3 0x000C 0x003C 0x0000 0x0 0x0
+#define MX7D_PAD_LPSR_GPIO1_IO03__PWM3_OUT 0x000C 0x003C 0x0000 0x1 0x0
+#define MX7D_PAD_LPSR_GPIO1_IO03__CCM_ENET_REF_CLK2 0x000C 0x003C 0x0570 0x2 0x3
+#define MX7D_PAD_LPSR_GPIO1_IO03__SAI3_MCLK 0x000C 0x003C 0x0000 0x3 0x0
+#define MX7D_PAD_LPSR_GPIO1_IO03__CCM_CLKO2 0x000C 0x003C 0x0000 0x5 0x0
+#define MX7D_PAD_LPSR_GPIO1_IO03__OBSERVE2_OUT 0x000C 0x003C 0x0000 0x6 0x0
+#define MX7D_PAD_LPSR_GPIO1_IO03__USB_OTG2_ID 0x000C 0x003C 0x0730 0x7 0x3
+#define MX7D_PAD_LPSR_GPIO1_IO04__GPIO1_IO4 0x0010 0x0040 0x0000 0x0 0x0
+#define MX7D_PAD_LPSR_GPIO1_IO04__USB_OTG1_OC 0x0010 0x0040 0x072C 0x1 0x1
+#define MX7D_PAD_LPSR_GPIO1_IO04__FLEXTIMER1_CH4 0x0010 0x0040 0x0594 0x2 0x1
+#define MX7D_PAD_LPSR_GPIO1_IO04__UART5_DCE_CTS 0x0010 0x0040 0x0000 0x3 0x0
+#define MX7D_PAD_LPSR_GPIO1_IO04__UART5_DTE_RTS 0x0010 0x0040 0x0710 0x3 0x4
+#define MX7D_PAD_LPSR_GPIO1_IO04__I2C1_SCL 0x0010 0x0040 0x05D4 0x4 0x2
+#define MX7D_PAD_LPSR_GPIO1_IO04__OBSERVE3_OUT 0x0010 0x0040 0x0000 0x6 0x0
+#define MX7D_PAD_LPSR_GPIO1_IO05__GPIO1_IO5 0x0014 0x0044 0x0000 0x0 0x0
+#define MX7D_PAD_LPSR_GPIO1_IO05__USB_OTG1_PWR 0x0014 0x0044 0x0000 0x1 0x0
+#define MX7D_PAD_LPSR_GPIO1_IO05__FLEXTIMER1_CH5 0x0014 0x0044 0x0598 0x2 0x1
+#define MX7D_PAD_LPSR_GPIO1_IO05__UART5_DCE_RTS 0x0014 0x0044 0x0710 0x3 0x5
+#define MX7D_PAD_LPSR_GPIO1_IO05__UART5_DTE_CTS 0x0014 0x0044 0x0000 0x3 0x0
+#define MX7D_PAD_LPSR_GPIO1_IO05__I2C1_SDA 0x0014 0x0044 0x05D8 0x4 0x2
+#define MX7D_PAD_LPSR_GPIO1_IO05__OBSERVE4_OUT 0x0014 0x0044 0x0000 0x6 0x0
+#define MX7D_PAD_LPSR_GPIO1_IO06__GPIO1_IO6 0x0018 0x0048 0x0000 0x0 0x0
+#define MX7D_PAD_LPSR_GPIO1_IO06__USB_OTG2_OC 0x0018 0x0048 0x0728 0x1 0x1
+#define MX7D_PAD_LPSR_GPIO1_IO06__FLEXTIMER1_CH6 0x0018 0x0048 0x059C 0x2 0x1
+#define MX7D_PAD_LPSR_GPIO1_IO06__UART5_DCE_RX 0x0018 0x0048 0x0714 0x3 0x4
+#define MX7D_PAD_LPSR_GPIO1_IO06__UART5_DTE_TX 0x0018 0x0048 0x0000 0x3 0x0
+#define MX7D_PAD_LPSR_GPIO1_IO06__I2C2_SCL 0x0018 0x0048 0x05DC 0x4 0x2
+#define MX7D_PAD_LPSR_GPIO1_IO06__CCM_WAIT 0x0018 0x0048 0x0000 0x5 0x0
+#define MX7D_PAD_LPSR_GPIO1_IO06__KPP_ROW4 0x0018 0x0048 0x0624 0x6 0x1
+#define MX7D_PAD_LPSR_GPIO1_IO07__GPIO1_IO7 0x001C 0x004C 0x0000 0x0 0x0
+#define MX7D_PAD_LPSR_GPIO1_IO07__USB_OTG2_PWR 0x001C 0x004C 0x0000 0x1 0x0
+#define MX7D_PAD_LPSR_GPIO1_IO07__FLEXTIMER1_CH7 0x001C 0x004C 0x05A0 0x2 0x1
+#define MX7D_PAD_LPSR_GPIO1_IO07__UART5_DCE_TX 0x001C 0x004C 0x0000 0x3 0x0
+#define MX7D_PAD_LPSR_GPIO1_IO07__UART5_DTE_RX 0x001C 0x004C 0x0714 0x3 0x5
+#define MX7D_PAD_LPSR_GPIO1_IO07__I2C2_SDA 0x001C 0x004C 0x05E0 0x4 0x2
+#define MX7D_PAD_LPSR_GPIO1_IO07__CCM_STOP 0x001C 0x004C 0x0000 0x5 0x0
+#define MX7D_PAD_LPSR_GPIO1_IO07__KPP_COL4 0x001C 0x004C 0x0604 0x6 0x1
#endif /* __DTS_IMX7D_PINFUNC_LPSR_H */
diff --git a/arch/arm/boot/dts/imx7d-sdb.dts b/arch/arm/boot/dts/imx7d-sdb.dts
index 09089bb..177dea2 100644
--- a/arch/arm/boot/dts/imx7d-sdb.dts
+++ b/arch/arm/boot/dts/imx7d-sdb.dts
@@ -1052,37 +1052,37 @@
imx7d-sdb {
pinctrl_hog_2: hoggrp-2 {
fsl,pins = <
- MX7D_PAD_GPIO1_IO05__GPIO1_IO5 0x14
+ MX7D_PAD_LPSR_GPIO1_IO05__GPIO1_IO5 0x14
>;
};
pinctrl_pwm1: pwm1grp {
fsl,pins = <
- MX7D_PAD_GPIO1_IO01__PWM1_OUT 0x30
+ MX7D_PAD_LPSR_GPIO1_IO01__PWM1_OUT 0x30
>;
};
pinctrl_usbotg2_pwr_2: usbotg2-2 {
fsl,pins = <
- MX7D_PAD_GPIO1_IO07__GPIO1_IO7 0x14
+ MX7D_PAD_LPSR_GPIO1_IO07__GPIO1_IO7 0x14
>;
};
pinctrl_wdog: wdoggrp {
fsl,pins = <
- MX7D_PAD_GPIO1_IO00__WDOD1_WDOG_B 0x74
+ MX7D_PAD_LPSR_GPIO1_IO00__WDOD1_WDOG_B 0x74
>;
};
pinctrl_enet2_epdc0_en: enet2_epdc0_grp {
fsl,pins = <
- MX7D_PAD_GPIO1_IO04__GPIO1_IO4 0x59
+ MX7D_PAD_LPSR_GPIO1_IO04__GPIO1_IO4 0x59
>;
};
pinctrl_sai3_mclk: sai3grp_mclk {
fsl,pins = <
- MX7D_PAD_GPIO1_IO03__SAI3_MCLK 0x1f
+ MX7D_PAD_LPSR_GPIO1_IO03__SAI3_MCLK 0x1f
>;
};
};
--
2.7.4
^ permalink raw reply related [flat|nested] 3+ messages in thread
* [linux-fslc][PATCH 2/2] ARM: dts: imx7s-warp: Add watchdog pinmux
2017-01-23 14:36 [linux-fslc][PATCH 0/2] i.MX7: Fix LPSR specific iomux pins Vanessa Maegima
2017-01-23 14:36 ` [linux-fslc][PATCH 1/2] ARM: dts: imx7: Add "LPSR" to LPSR iomux pin names Vanessa Maegima
@ 2017-01-23 14:36 ` Vanessa Maegima
1 sibling, 0 replies; 3+ messages in thread
From: Vanessa Maegima @ 2017-01-23 14:36 UTC (permalink / raw)
To: meta-freescale; +Cc: Vanessa Maegima
Add watchdog to the imx7s-warp's device tree.
Signed-off-by: Vanessa Maegima <vanessa.maegima@nxp.com>
---
arch/arm/boot/dts/imx7s-warp.dts | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/arch/arm/boot/dts/imx7s-warp.dts b/arch/arm/boot/dts/imx7s-warp.dts
index 2c8f79a..4a1ff1e 100644
--- a/arch/arm/boot/dts/imx7s-warp.dts
+++ b/arch/arm/boot/dts/imx7s-warp.dts
@@ -449,3 +449,11 @@
};
};
};
+
+&iomuxc_lpsr {
+ pinctrl_wdog: wdoggrp {
+ fsl,pins = <
+ MX7D_PAD_LPSR_GPIO1_IO00__WDOD1_WDOG_B 0x74
+ >;
+ };
+};
--
2.7.4
^ permalink raw reply related [flat|nested] 3+ messages in thread
end of thread, other threads:[~2017-01-23 16:09 UTC | newest]
Thread overview: 3+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2017-01-23 14:36 [linux-fslc][PATCH 0/2] i.MX7: Fix LPSR specific iomux pins Vanessa Maegima
2017-01-23 14:36 ` [linux-fslc][PATCH 1/2] ARM: dts: imx7: Add "LPSR" to LPSR iomux pin names Vanessa Maegima
2017-01-23 14:36 ` [linux-fslc][PATCH 2/2] ARM: dts: imx7s-warp: Add watchdog pinmux Vanessa Maegima
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