From mboxrd@z Thu Jan 1 00:00:00 1970 From: David Woodhouse Subject: Re: Xen Security Advisory 154 (CVE-2016-2270) - x86: inconsistent cachability flags on guest mappings Date: Wed, 25 Jan 2017 14:34:30 +0000 Message-ID: <1485354870.4727.117.camel@infradead.org> References: <1485353329.4727.111.camel@infradead.org> <5888C2810200007800133CDC@prv-mh.provo.novell.com> Mime-Version: 1.0 Content-Type: multipart/mixed; boundary="===============0166307475137329343==" Return-path: In-Reply-To: <5888C2810200007800133CDC@prv-mh.provo.novell.com> List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xen.org Sender: "Xen-devel" To: Jan Beulich Cc: Andrew Cooper , "H. Peter Anvin" , xen-devel@lists.xen.org List-Id: xen-devel@lists.xenproject.org --===============0166307475137329343== Content-Type: multipart/signed; micalg="sha-256"; protocol="application/x-pkcs7-signature"; boundary="=-nUa45W64tHnKhbmK21zr" --=-nUa45W64tHnKhbmK21zr Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable On Wed, 2017-01-25 at 07:21 -0700, Jan Beulich wrote: > Note the difference between "contains" and "overlaps". Oh, that makes more sense; thanks. > > And then there's a 'if (direct_mmio) return UC;' further down which > > looks like it'd do the right thing for the use case I'm actually > > testing. I may see if I can construct a straw man patch, but I'm kind > > of unfamiliar with this code so it should be taken with a large pinch > > of salt... > > If there wasn't INVALID_MFN to be taken care of, the !mfn_valid() > check could simply move down, and be combined with the > direct_mmio one. I'll see what I can come up with. > > WC vs. UC. But it would be good to have a definitive answer from Intel > > and AMD about whether it's safe. > > Well, in the context of this XSA we've asked both of them, and iirc > we've got a vague reply from Intel and none from AMD. In fact we > did defer the XSA for quite a bit waiting for any useful feedback. > To AMD's advantage I'd like to add though that iirc they're a little > more clear in their PM about the specific question of UC and WC > you raise: They group the various cacheabilities into two groups > (cacheable and uncacheable) and require there to only not be > any mixture between groups. Iirc Intel's somewhat vague reply > allowed us to conclude we're likely safe that way on their side too. That's useful information; thanks. Coupled with the empirical testing and the fact that we're already "violating" the recommendation of the Intel SDM by allowing a mixture of memory types on RAM pages, I think that's probably sufficient to conclude that it's OK to permit this. --=-nUa45W64tHnKhbmK21zr Content-Type: application/x-pkcs7-signature; name="smime.p7s" Content-Disposition: attachment; filename="smime.p7s" Content-Transfer-Encoding: base64 MIAGCSqGSIb3DQEHAqCAMIACAQExDzANBglghkgBZQMEAgEFADCABgkqhkiG9w0BBwEAAKCCDzUw ggSvMIIDl6ADAgECAhEA4CPLFRKDU4mtYW56VGdrITANBgkqhkiG9w0BAQsFADBvMQswCQYDVQQG EwJTRTEUMBIGA1UEChMLQWRkVHJ1c3QgQUIxJjAkBgNVBAsTHUFkZFRydXN0IEV4dGVybmFsIFRU UCBOZXR3b3JrMSIwIAYDVQQDExlBZGRUcnVzdCBFeHRlcm5hbCBDQSBSb290MB4XDTE0MTIyMjAw MDAwMFoXDTIwMDUzMDEwNDgzOFowgZsxCzAJBgNVBAYTAkdCMRswGQYDVQQIExJHcmVhdGVyIE1h bmNoZXN0ZXIxEDAOBgNVBAcTB1NhbGZvcmQxGjAYBgNVBAoTEUNPTU9ETyBDQSBMaW1pdGVkMUEw PwYDVQQDEzhDT01PRE8gU0hBLTI1NiBDbGllbnQgQXV0aGVudGljYXRpb24gYW5kIFNlY3VyZSBF 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