From: Madhav Chauhan <madhav.chauhan@intel.com>
To: intel-gfx@lists.freedesktop.org
Cc: ander.conselvan.de.oliveira@intel.com, jani.nikula@intel.com
Subject: [GLK MIPI DSI V4 0/8] GLK MIPI DSI VIDEO MODE PATCHES
Date: Tue, 7 Feb 2017 18:13:04 +0530 [thread overview]
Message-ID: <1486471392-1803-1-git-send-email-madhav.chauhan@intel.com> (raw)
The patches in this list enable MIPI DSI video mode
support for GLK platform. Tesed locally.
v2: Renamed bitfields macros as per review comments(Jani)
v3: Code alignment/abstraction as per arch (Jani review comments)
v4: Fix DSI disable sequence, pll divider checks. Review comments(Jani)
Deepak M (7):
drm/i915/glk: Program dphy param reg for GLK
drm/i915/glk: Program new MIPI DSI PHY registers for GLK
drm/i915/glk: Add MIPIIO Enable/disable sequence
drm/i915: Set the Z inversion overlap field
drm/i915/glk: Add DSI PLL divider range for glk
drm/i915i/glk: Program MIPI_CLOCK_CTRL only for BXT
drm/i915/glk: Program txesc clock divider for GLK
Madhav Chauhan (1):
drm/i915/glk: Validate only DSI PORT A PLL divider
drivers/gpu/drm/i915/i915_reg.h | 17 +++
drivers/gpu/drm/i915/intel_dsi.c | 230 +++++++++++++++++++++++++++--
drivers/gpu/drm/i915/intel_dsi_panel_vbt.c | 45 ++++--
drivers/gpu/drm/i915/intel_dsi_pll.c | 125 +++++++++++++---
4 files changed, 364 insertions(+), 53 deletions(-)
--
1.9.1
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next reply other threads:[~2017-02-07 12:47 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-02-07 12:43 Madhav Chauhan [this message]
2017-02-07 12:43 ` [GLK MIPI DSI V4 1/8] drm/i915/glk: Program dphy param reg for GLK Madhav Chauhan
2017-02-08 14:53 ` Jani Nikula
2017-02-08 17:27 ` Chauhan, Madhav
2017-02-07 12:43 ` [GLK MIPI DSI V4 2/8] drm/i915/glk: Program new MIPI DSI PHY registers " Madhav Chauhan
2017-02-07 12:43 ` [GLK MIPI DSI V4 3/8] drm/i915/glk: Add MIPIIO Enable/disable sequence Madhav Chauhan
2017-02-08 14:58 ` Jani Nikula
2017-02-08 17:51 ` Chauhan, Madhav
2017-02-07 12:43 ` [GLK MIPI DSI V4 4/8] drm/i915: Set the Z inversion overlap field Madhav Chauhan
2017-02-07 12:43 ` [GLK MIPI DSI V4 5/8] drm/i915/glk: Add DSI PLL divider range for glk Madhav Chauhan
2017-02-10 14:24 ` Ander Conselvan De Oliveira
2017-02-13 11:14 ` Chauhan, Madhav
2017-02-07 12:43 ` [GLK MIPI DSI V4 6/8] drm/i915i/glk: Program MIPI_CLOCK_CTRL only for BXT Madhav Chauhan
2017-02-07 12:43 ` [GLK MIPI DSI V4 7/8] drm/i915/glk: Program txesc clock divider for GLK Madhav Chauhan
2017-02-07 12:43 ` [GLK MIPI DSI V4 8/8] drm/i915/glk: Validate only DSI PORT A PLL divider Madhav Chauhan
2017-02-07 13:24 ` ✗ Fi.CI.BAT: failure for GLK MIPI DSI VIDEO MODE PATCHES (rev4) Patchwork
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