From mboxrd@z Thu Jan 1 00:00:00 1970 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 08 Feb 2017 03:00:23 +0100 (CET) Received: from SMTPBG181.QQ.COM ([119.147.193.88]:33539 "EHLO smtpbg181.qq.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S23992221AbdBHB6zqsaN2 (ORCPT ); Wed, 8 Feb 2017 02:58:55 +0100 X-QQ-mid: bizesmtp3t1486519089tc30aou0v Received: from software.domain.org (unknown [222.92.8.142]) by esmtp4.qq.com (ESMTP) with id ; Wed, 08 Feb 2017 09:58:09 +0800 (CST) X-QQ-SSF: 01100000002000F0FH61B00A0000000 X-QQ-FEAT: r8geFCKg7nYSOg6J9CtTD53ghSFIQ1gZuRe8mbYtrAlH3N/WYwFDs0Fdo6ZEp LHielUVpWQiVFqEKW2CTF0plAi/86Nr9fxn0O+unsPrfKx2i0d84fwwayVl/Ak5z2d4CGmv T27vmCf1R/cikqH+t2bllOL7O4HGdR17QW5D1pkL9rLAdYznzbh+7yJ91KUfWrTDOUn0LNQ /YUcScZNuuFpztcjht5lq6hZFuhP7E9KTEOsVjo90sPeseDk7vdoWpdQcw6ZyVYmF35XqjE rdMdsv0TnJiI19OCH60VULPeU7imda8N3Esg== X-QQ-GoodBg: 0 From: Binbin Zhou To: Ralf Baechle Cc: John Crispin , "Steven J . Hill" , linux-mips@linux-mips.org, Fuxin Zhang , Zhangjin Wu , Kelvin Cheung , Yang Ling , Binbin Zhou , HuaCai Chen Subject: [PATCH v5 1/8] MIPS: Loongson: Merge PRID macro for Loongson-1A/1B/1C Date: Wed, 8 Feb 2017 09:57:42 +0800 Message-Id: <1486519069-9364-2-git-send-email-zhoubb@lemote.com> X-Mailer: git-send-email 2.7.0 In-Reply-To: <1486519069-9364-1-git-send-email-zhoubb@lemote.com> References: <1486519069-9364-1-git-send-email-zhoubb@lemote.com> X-QQ-SENDSIZE: 520 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 56721 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: zhoubb@lemote.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips The Loongson-1 series CPUs(1A/1B/1C) share the same PRID macro. Signed-off-by: Binbin Zhou Signed-off-by: HuaCai Chen --- arch/mips/include/asm/cpu.h | 3 +-- arch/mips/kernel/cpu-probe.c | 4 +++- arch/mips/loongson32/common/setup.c | 2 +- 3 files changed, 5 insertions(+), 4 deletions(-) diff --git a/arch/mips/include/asm/cpu.h b/arch/mips/include/asm/cpu.h index 9a83724..76c0b56c3 100644 --- a/arch/mips/include/asm/cpu.h +++ b/arch/mips/include/asm/cpu.h @@ -239,8 +239,7 @@ #define PRID_REV_VR4181A 0x0070 /* Same as VR4122 */ #define PRID_REV_VR4130 0x0080 #define PRID_REV_34K_V1_0_2 0x0022 -#define PRID_REV_LOONGSON1B 0x0020 -#define PRID_REV_LOONGSON1C 0x0020 /* Same as Loongson-1B */ +#define PRID_REV_LOONGSON1ABC 0x0020 #define PRID_REV_LOONGSON2E 0x0002 #define PRID_REV_LOONGSON2F 0x0003 #define PRID_REV_LOONGSON3A_R1 0x0005 diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c index 07718bb..657d65d 100644 --- a/arch/mips/kernel/cpu-probe.c +++ b/arch/mips/kernel/cpu-probe.c @@ -1502,8 +1502,10 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu) c->cputype = CPU_LOONGSON1; switch (c->processor_id & PRID_REV_MASK) { - case PRID_REV_LOONGSON1B: + case PRID_REV_LOONGSON1ABC: +#ifdef CONFIG_CPU_LOONGSON1B __cpu_name[cpu] = "Loongson 1B"; +#endif break; } diff --git a/arch/mips/loongson32/common/setup.c b/arch/mips/loongson32/common/setup.c index 1640744..c8e8b3e 100644 --- a/arch/mips/loongson32/common/setup.c +++ b/arch/mips/loongson32/common/setup.c @@ -21,7 +21,7 @@ const char *get_system_type(void) unsigned int processor_id = (¤t_cpu_data)->processor_id; switch (processor_id & PRID_REV_MASK) { - case PRID_REV_LOONGSON1B: + case PRID_REV_LOONGSON1ABC: #if defined(CONFIG_LOONGSON1_LS1B) return "LOONGSON LS1B"; #elif defined(CONFIG_LOONGSON1_LS1C) -- 2.9.3