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From: Yi Sun <yi.y.sun@linux.intel.com>
To: xen-devel@lists.xenproject.org
Cc: kevin.tian@intel.com, wei.liu2@citrix.com,
	andrew.cooper3@citrix.com, dario.faggioli@citrix.com,
	he.chen@linux.intel.com, ian.jackson@eu.citrix.com,
	Yi Sun <yi.y.sun@linux.intel.com>,
	mengxu@cis.upenn.edu, jbeulich@suse.com,
	chao.p.peng@linux.intel.com
Subject: [PATCH v6 24/24] docs: add L2 CAT description in docs.
Date: Wed,  8 Feb 2017 16:16:16 +0800	[thread overview]
Message-ID: <1486541776-8406-25-git-send-email-yi.y.sun@linux.intel.com> (raw)
In-Reply-To: <1486541776-8406-1-git-send-email-yi.y.sun@linux.intel.com>

This patch adds L2 CAT description in related documents.

Signed-off-by: He Chen <he.chen@linux.intel.com>
Signed-off-by: Yi Sun <yi.y.sun@linux.intel.com>
Acked-by: Wei Liu <wei.liu2@citrix.com>
---
 docs/man/xl.pod.1.in      | 25 ++++++++++++++++++++++---
 docs/misc/xl-psr.markdown | 10 ++++++++--
 2 files changed, 30 insertions(+), 5 deletions(-)

diff --git a/docs/man/xl.pod.1.in b/docs/man/xl.pod.1.in
index 7caed08..5e7676e 100644
--- a/docs/man/xl.pod.1.in
+++ b/docs/man/xl.pod.1.in
@@ -1711,6 +1711,9 @@ occupancy monitoring share the same set of underlying monitoring service. Once
 a domain is attached to the monitoring service, monitoring data can be shown
 for any of these monitoring types.
 
+There is no cache monitoring and memory bandwidth monitoring on L2 cache so
+far.
+
 =over 4
 
 =item B<psr-cmt-attach> [I<domain-id>]
@@ -1735,7 +1738,7 @@ monitor types are:
 
 Intel Broadwell and later server platforms offer capabilities to configure and
 make use of the Cache Allocation Technology (CAT) mechanisms, which enable more
-cache resources (i.e. L3 cache) to be made available for high priority
+cache resources (i.e. L3/L2 cache) to be made available for high priority
 applications. In the Xen implementation, CAT is used to control cache allocation
 on VM basis. To enforce cache on a specific domain, just set capacity bitmasks
 (CBM) for the domain.
@@ -1745,7 +1748,7 @@ Intel Broadwell and later server platforms also offer Code/Data Prioritization
 applications. CDP is used on a per VM basis in the Xen implementation. To
 specify code or data CBM for the domain, CDP feature must be enabled and CBM
 type options need to be specified when setting CBM, and the type options (code
-and data) are mutually exclusive.
+and data) are mutually exclusive. There is no CDP support on L2 so far.
 
 =over 4
 
@@ -1762,6 +1765,11 @@ B<OPTIONS>
 
 Specify the socket to process, otherwise all sockets are processed.
 
+=item B<-l LEVEL>, B<--level=LEVEL>
+
+Specify the cache level to process, otherwise the last level cache (L3) is
+processed.
+
 =item B<-c>, B<--code>
 
 Set code CBM when CDP is enabled.
@@ -1772,10 +1780,21 @@ Set data CBM when CDP is enabled.
 
 =back
 
-=item B<psr-cat-show> [I<domain-id>]
+=item B<psr-cat-show> [I<OPTIONS>] [I<domain-id>]
 
 Show CAT settings for a certain domain or all domains.
 
+B<OPTIONS>
+
+=over 4
+
+=item B<-l LEVEL>, B<--level=LEVEL>
+
+Specify the cache level to process, otherwise the last level cache (L3) is
+processed.
+
+=back
+
 =back
 
 =head1 IGNORED FOR COMPATIBILITY WITH XM
diff --git a/docs/misc/xl-psr.markdown b/docs/misc/xl-psr.markdown
index c3c1e8e..bd2b6bd 100644
--- a/docs/misc/xl-psr.markdown
+++ b/docs/misc/xl-psr.markdown
@@ -70,7 +70,7 @@ total-mem-bandwidth instead of cache-occupancy). E.g. after a `xl psr-cmt-attach
 
 Cache Allocation Technology (CAT) is a new feature available on Intel
 Broadwell and later server platforms that allows an OS or Hypervisor/VMM to
-partition cache allocation (i.e. L3 cache) based on application priority or
+partition cache allocation (i.e. L3/L2 cache) based on application priority or
 Class of Service (COS). Each COS is configured using capacity bitmasks (CBM)
 which represent cache capacity and indicate the degree of overlap and
 isolation between classes. System cache resource is divided into numbers of
@@ -119,13 +119,19 @@ A cbm is valid only when:
 In a multi-socket system, the same cbm will be set on each socket by default.
 Per socket cbm can be specified with the `--socket SOCKET` option.
 
+In different systems, the different cache level is supported, e.g. L3 cache or
+L2 cache. Per cache level cbm can be specified with the `--level LEVEL` option.
+
 Setting the CBM may not be successful if insufficient COS is available. In
 such case unused COS(es) may be freed by setting CBM of all related domains to
 its default value(all-ones).
 
 Per domain CBM settings can be shown by:
 
-`xl psr-cat-show`
+`xl psr-cat-show [OPTIONS] <domid>`
+
+In different systems, the different cache level is supported, e.g. L3 cache or
+L2 cache. Per cache level cbm can be specified with the `--level LEVEL` option.
 
 ## Code and Data Prioritization (CDP)
 
-- 
1.9.1


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      parent reply	other threads:[~2017-02-08  8:20 UTC|newest]

Thread overview: 37+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2017-02-08  8:15 [PATCH v6 00/24] Enable L2 Cache Allocation Technology & Refactor psr.c Yi Sun
2017-02-08  8:15 ` [PATCH v6 01/24] docs: create Cache Allocation Technology (CAT) and Code and Data Prioritization (CDP) feature document Yi Sun
2017-02-08 15:56   ` Konrad Rzeszutek Wilk
2017-02-09  6:38     ` Yi Sun
2017-02-08  8:15 ` [PATCH v6 02/24] x86: refactor psr: remove L3 CAT/CDP codes Yi Sun
2017-02-08  8:15 ` [PATCH v6 03/24] x86: refactor psr: implement main data structures Yi Sun
2017-02-08 16:02   ` Konrad Rzeszutek Wilk
2017-02-09 11:05   ` Wei Liu
2017-02-08  8:15 ` [PATCH v6 04/24] x86: refactor psr: implement CPU init and free flow Yi Sun
2017-02-08 16:34   ` Konrad Rzeszutek Wilk
2017-02-08 19:03     ` Konrad Rzeszutek Wilk
2017-02-09 11:10       ` Yi Sun
2017-02-09 11:00     ` Yi Sun
2017-02-08  8:15 ` [PATCH v6 05/24] x86: refactor psr: implement Domain init/free and schedule flows Yi Sun
2017-02-08 16:43   ` Konrad Rzeszutek Wilk
2017-02-08  8:15 ` [PATCH v6 06/24] x86: refactor psr: implement get hw info flow Yi Sun
2017-02-10 21:34   ` Konrad Rzeszutek Wilk
2017-02-08  8:15 ` [PATCH v6 07/24] x86: refactor psr: implement get value flow Yi Sun
2017-02-09 11:05   ` Wei Liu
2017-02-10 21:38   ` Konrad Rzeszutek Wilk
2017-02-08  8:16 ` [PATCH v6 08/24] x86: refactor psr: set value: implement framework Yi Sun
2017-02-08  8:16 ` [PATCH v6 09/24] x86: refactor psr: set value: assemble features value array Yi Sun
2017-02-08  8:16 ` [PATCH v6 10/24] x86: refactor psr: set value: implement cos finding flow Yi Sun
2017-02-08  8:16 ` [PATCH v6 11/24] x86: refactor psr: set value: implement cos id picking flow Yi Sun
2017-02-08  8:16 ` [PATCH v6 12/24] x86: refactor psr: set value: implement write msr flow Yi Sun
2017-02-08  8:16 ` [PATCH v6 13/24] x86: refactor psr: implement CPU init and free flow for CDP Yi Sun
2017-02-08  8:16 ` [PATCH v6 14/24] x86: refactor psr: implement get hw info " Yi Sun
2017-02-08  8:16 ` [PATCH v6 15/24] x86: refactor psr: implement get value " Yi Sun
2017-02-08  8:16 ` [PATCH v6 16/24] x86: refactor psr: implement set value callback functions " Yi Sun
2017-02-08  8:16 ` [PATCH v6 17/24] x86: L2 CAT: implement CPU init and free flow Yi Sun
2017-02-08  8:16 ` [PATCH v6 18/24] x86: L2 CAT: implement get hw info flow Yi Sun
2017-02-08  8:16 ` [PATCH v6 19/24] x86: L2 CAT: implement get value flow Yi Sun
2017-02-08  8:16 ` [PATCH v6 20/24] x86: L2 CAT: implement set " Yi Sun
2017-02-08  8:16 ` [PATCH v6 21/24] tools: L2 CAT: support get HW info for L2 CAT Yi Sun
2017-02-08  8:16 ` [PATCH v6 22/24] tools: L2 CAT: support show cbm " Yi Sun
2017-02-08  8:16 ` [PATCH v6 23/24] tools: L2 CAT: support set " Yi Sun
2017-02-08  8:16 ` Yi Sun [this message]

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