[Qemu-devel] [PATCH v3 4/8] target-mips: Provide function to test if a CPU supports an ISA

[Qemu-devel] [PATCH v3 4/8] target-mips: Provide function to test if a CPU supports an ISA

[Yongbok Kim]

From: Paul Burton <paul.burton@imgtec.com>

Provide a new cpu_supports_isa function which allows callers to
determine whether a CPU supports one of the ISA_ flags, by testing
whether the associated struct mips_def_t sets the ISA flags in its
insn_flags field.

An example use of this is to allow boards which generate bootloader code
to determine the properties of the CPU that will be used, for example
whether the CPU is 64 bit or which architecture revision it implements.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Reviewed-by: Leon Alrae <leon.alrae@imgtec.com>
Signed-off-by: Yongbok Kim <yongbok.kim@imgtec.com>
---
 target/mips/cpu.h       |  1 +
 target/mips/translate.c | 10 ++++++++++
 2 files changed, 11 insertions(+)

diff --git a/target/mips/cpu.h b/target/mips/cpu.h
index e1c78f5..4a4747a 100644
--- a/target/mips/cpu.h
+++ b/target/mips/cpu.h
@@ -815,6 +815,7 @@ int cpu_mips_signal_handler(int host_signum, void *pinfo, void *puc);
 
 #define cpu_init(cpu_model) CPU(cpu_mips_init(cpu_model))
 bool cpu_supports_cps_smp(const char *cpu_model);
+bool cpu_supports_isa(const char *cpu_model, unsigned int isa);
 void cpu_set_exception_base(int vp_index, target_ulong address);
 
 /* TODO QOM'ify CPU reset and remove */
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 7f8ecf4..8b4a072 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -20233,6 +20233,16 @@ bool cpu_supports_cps_smp(const char *cpu_model)
     return (def->CP0_Config3 & (1 << CP0C3_CMGCR)) != 0;
 }
 
+bool cpu_supports_isa(const char *cpu_model, unsigned int isa)
+{
+    const mips_def_t *def = cpu_mips_find_by_name(cpu_model);
+    if (!def) {
+        return false;
+    }
+
+    return (def->insn_flags & isa) != 0;
+}
+
 void cpu_set_exception_base(int vp_index, target_ulong address)
 {
     MIPSCPU *vp = MIPS_CPU(qemu_get_cpu(vp_index));
-- 
2.7.4

Re: [Qemu-devel] [PATCH v3 4/8] target-mips: Provide function to test if a CPU supports an ISA

[Philippe Mathieu-Daudé]

On 02/08/2017 01:33 PM, Yongbok Kim wrote:
> From: Paul Burton <paul.burton@imgtec.com>
>
> Provide a new cpu_supports_isa function which allows callers to
> determine whether a CPU supports one of the ISA_ flags, by testing
> whether the associated struct mips_def_t sets the ISA flags in its
> insn_flags field.
>
> An example use of this is to allow boards which generate bootloader code
> to determine the properties of the CPU that will be used, for example
> whether the CPU is 64 bit or which architecture revision it implements.
>
> Signed-off-by: Paul Burton <paul.burton@imgtec.com>
> Reviewed-by: Leon Alrae <leon.alrae@imgtec.com>
> Signed-off-by: Yongbok Kim <yongbok.kim@imgtec.com>
> ---
>  target/mips/cpu.h       |  1 +
>  target/mips/translate.c | 10 ++++++++++
>  2 files changed, 11 insertions(+)
>
> diff --git a/target/mips/cpu.h b/target/mips/cpu.h
> index e1c78f5..4a4747a 100644
> --- a/target/mips/cpu.h
> +++ b/target/mips/cpu.h
> @@ -815,6 +815,7 @@ int cpu_mips_signal_handler(int host_signum, void *pinfo, void *puc);
>
>  #define cpu_init(cpu_model) CPU(cpu_mips_init(cpu_model))
>  bool cpu_supports_cps_smp(const char *cpu_model);
> +bool cpu_supports_isa(const char *cpu_model, unsigned int isa);
>  void cpu_set_exception_base(int vp_index, target_ulong address);
>
>  /* TODO QOM'ify CPU reset and remove */
> diff --git a/target/mips/translate.c b/target/mips/translate.c
> index 7f8ecf4..8b4a072 100644
> --- a/target/mips/translate.c
> +++ b/target/mips/translate.c
> @@ -20233,6 +20233,16 @@ bool cpu_supports_cps_smp(const char *cpu_model)
>      return (def->CP0_Config3 & (1 << CP0C3_CMGCR)) != 0;
>  }
>
> +bool cpu_supports_isa(const char *cpu_model, unsigned int isa)
> +{
> +    const mips_def_t *def = cpu_mips_find_by_name(cpu_model);
> +    if (!def) {
> +        return false;
> +    }
> +
> +    return (def->insn_flags & isa) != 0;
> +}
> +
>  void cpu_set_exception_base(int vp_index, target_ulong address)
>  {
>      MIPSCPU *vp = MIPS_CPU(qemu_get_cpu(vp_index));
>

Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>