[U-Boot] [PATCH 07/10] mvebu: a37xx: Add init for ESPRESSBin Topaz switch

[kostap at marvell.com <kostap@marvell.com>]

From: Konstantin Porotchkin <kostap@marvell.com>

Implement the board-specific network init function for
ESPRESSOBin community board, setting the on-board Topaz
switch port to forward mode and allow network connection
through any of the available Etherenet ports.

Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
Cc: Stefan Roese <sr@denx.de>
Cc: Igal Liberman <igall@marvell.com>
---
 board/Marvell/mvebu_db-88f3720/board.c | 49 ++++++++++++++++++++++++++++++++++
 1 file changed, 49 insertions(+)

diff --git a/board/Marvell/mvebu_db-88f3720/board.c b/board/Marvell/mvebu_db-88f3720/board.c
index 3337f3f..45098ce 100644
--- a/board/Marvell/mvebu_db-88f3720/board.c
+++ b/board/Marvell/mvebu_db-88f3720/board.c
@@ -6,6 +6,7 @@
 
 #include <common.h>
 #include <i2c.h>
+#include <phy.h>
 #include <asm/io.h>
 #include <asm/arch/cpu.h>
 #include <asm/arch/soc.h>
@@ -156,3 +157,51 @@ int board_xhci_enable(void)
 
 	return 0;
 }
+
+static int mii_multi_chip_mode_write(struct mii_dev *bus, int dev_smi_addr,
+				     int smi_addr, int reg, u16 value)
+{
+	u16 data = 0;
+
+	if (bus->write(bus, dev_smi_addr, 0, 1, value) != 0) {
+		printf("Error writing to the PHY addr=%02x reg=%02x\n",
+		       smi_addr, reg);
+		return -EFAULT;
+	}
+
+	data = (1 << 15) | (1 << 12) | (1 << 10) | (smi_addr << 5) | reg;
+	if (bus->write(bus, dev_smi_addr, 0, 0, data) != 0) {
+		printf("Error writing to the PHY addr=%02x reg=%02x\n",
+		       smi_addr, reg);
+		return -EFAULT;
+	}
+
+	return 0;
+}
+
+
+int board_network_enable(struct mii_dev *bus)
+{
+	if (!of_machine_is_compatible("marvell,armada-3720-espressobin"))
+		return 0;
+
+	/*
+	 * FIXME: remove this code once Topaz driver gets available
+	 * A3720 Community Board Only
+	 * Configure Topaz switch (88E6341)
+	 * Set port 0,1,2,3 to forwarding Mode
+	 */
+	mii_multi_chip_mode_write(bus, 1, 16, 4, 0x7f);
+	mii_multi_chip_mode_write(bus, 1, 17, 4, 0x7f);
+	mii_multi_chip_mode_write(bus, 1, 18, 4, 0x7f);
+	mii_multi_chip_mode_write(bus, 1, 19, 4, 0x7f);
+	/* RGMII Delay on Port 0*/
+	mii_multi_chip_mode_write(bus, 1, 16, 1, 0xe002);
+	/* Power up PHY 1, 2, 3 */
+	mii_multi_chip_mode_write(bus, 1, 28, 25, 0x1140);
+	mii_multi_chip_mode_write(bus, 1, 28, 24, 0x9620);
+	mii_multi_chip_mode_write(bus, 1, 28, 24, 0x9640);
+	mii_multi_chip_mode_write(bus, 1, 28, 24, 0x9660);
+
+	return 0;
+}
-- 
2.7.4