From: Madhav Chauhan <madhav.chauhan@intel.com>
To: intel-gfx@lists.freedesktop.org
Cc: ander.conselvan.de.oliveira@intel.com, jani.nikula@intel.com,
Deepak M <m.deepak@intel.com>
Subject: [GLK MIPI DSI V6 2/7] drm/i915/glk: Program new MIPI DSI PHY registers for GLK
Date: Fri, 17 Feb 2017 18:13:30 +0530 [thread overview]
Message-ID: <1487335415-14766-3-git-send-email-madhav.chauhan@intel.com> (raw)
In-Reply-To: <1487335415-14766-1-git-send-email-madhav.chauhan@intel.com>
From: Deepak M <m.deepak@intel.com>
Program the clk lane and tlpx time count registers
to configure DSI PHY.
v2: Addressed Jani's Review comments(renamed bit field macros)
v3: Program clk lane timing reg same as dphy param reg.
v4: Removed "line over 80 character" warning
Signed-off-by: Deepak M <m.deepak@intel.com>
Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 8 ++++++++
drivers/gpu/drm/i915/intel_dsi.c | 8 ++++++++
2 files changed, 16 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 141a5c1..c09f665 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -8636,6 +8636,14 @@ enum {
#define LP_BYTECLK_SHIFT 0
#define LP_BYTECLK_MASK (0xffff << 0)
+#define _MIPIA_TLPX_TIME_COUNT (dev_priv->mipi_mmio_base + 0xb0a4)
+#define _MIPIC_TLPX_TIME_COUNT (dev_priv->mipi_mmio_base + 0xb8a4)
+#define MIPI_TLPX_TIME_COUNT(port) _MMIO_MIPI(port, _MIPIA_TLPX_TIME_COUNT, _MIPIC_TLPX_TIME_COUNT)
+
+#define _MIPIA_CLK_LANE_TIMING (dev_priv->mipi_mmio_base + 0xb098)
+#define _MIPIC_CLK_LANE_TIMING (dev_priv->mipi_mmio_base + 0xb898)
+#define MIPI_CLK_LANE_TIMING(port) _MMIO_MIPI(port, _MIPIA_CLK_LANE_TIMING, _MIPIC_CLK_LANE_TIMING)
+
/* bits 31:0 */
#define _MIPIA_LP_GEN_DATA (dev_priv->mipi_mmio_base + 0xb064)
#define _MIPIC_LP_GEN_DATA (dev_priv->mipi_mmio_base + 0xb864)
diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
index c26fe4f..16b8c83 100644
--- a/drivers/gpu/drm/i915/intel_dsi.c
+++ b/drivers/gpu/drm/i915/intel_dsi.c
@@ -1310,6 +1310,14 @@ static void intel_dsi_prepare(struct intel_encoder *intel_encoder,
*/
I915_WRITE(MIPI_LP_BYTECLK(port), intel_dsi->lp_byte_clk);
+ if (IS_GEMINILAKE(dev_priv)) {
+ I915_WRITE(MIPI_TLPX_TIME_COUNT(port),
+ intel_dsi->lp_byte_clk);
+ /* Shadow of DPHY reg */
+ I915_WRITE(MIPI_CLK_LANE_TIMING(port),
+ intel_dsi->dphy_reg);
+ }
+
/* the bw essential for transmitting 16 long packets containing
* 252 bytes meant for dcs write memory command is programmed in
* this register in terms of byte clocks. based on dsi transfer
--
1.9.1
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next prev parent reply other threads:[~2017-02-17 12:48 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-02-17 12:43 [GLK MIPI DSI V6 0/7] GLK MIPI DSI VIDEO MODE PATCHES Madhav Chauhan
2017-02-17 12:43 ` [GLK MIPI DSI V6 1/7] drm/i915/glk: Program dphy param reg for GLK Madhav Chauhan
2017-02-17 12:43 ` Madhav Chauhan [this message]
2017-02-17 12:43 ` [GLK MIPI DSI V6 3/7] drm/i915/glk: Add MIPIIO Enable/disable sequence Madhav Chauhan
2017-02-17 12:43 ` [GLK MIPI DSI V6 4/7] drm/i915/glk: Add DSI PLL divider range for glk Madhav Chauhan
2017-02-17 12:43 ` [GLK MIPI DSI V6 5/7] drm/i915i/glk: Program MIPI_CLOCK_CTRL only for BXT Madhav Chauhan
2017-02-17 12:43 ` [GLK MIPI DSI V6 6/7] drm/i915/glk: Program txesc clock divider for GLK Madhav Chauhan
2017-02-17 12:43 ` [GLK MIPI DSI V6 7/7] drm/i915/glk: Validate only DSI PORT A PLL divider Madhav Chauhan
2017-02-17 14:22 ` ✗ Fi.CI.BAT: failure for GLK MIPI DSI VIDEO MODE PATCHES (rev6) Patchwork
2017-02-28 10:02 ` [GLK MIPI DSI V6 0/7] GLK MIPI DSI VIDEO MODE PATCHES Jani Nikula
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