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* [PATCH v1] clk: rockchip: add pll_wait_lock for pll_enable
@ 2017-02-22  2:59 ` Elaine Zhang
  0 siblings, 0 replies; 4+ messages in thread
From: Elaine Zhang @ 2017-02-22  2:59 UTC (permalink / raw)
  To: heiko, mturquette, sboyd, xf
  Cc: linux-clk, huangtao, xxx, linux-rockchip, linux-kernel,
	linux-arm-kernel, Elaine Zhang

If pll is power down,when power up pll need wait pll lock.
The reference documents section:
	PLL frequency change and lock check

Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
---
 drivers/clk/rockchip/clk-pll.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/clk/rockchip/clk-pll.c b/drivers/clk/rockchip/clk-pll.c
index 6ed605776abd..c4dfd26f37ae 100644
--- a/drivers/clk/rockchip/clk-pll.c
+++ b/drivers/clk/rockchip/clk-pll.c
@@ -268,6 +268,7 @@ static int rockchip_rk3036_pll_enable(struct clk_hw *hw)
 
 	writel(HIWORD_UPDATE(0, RK3036_PLLCON1_PWRDOWN, 0),
 	       pll->reg_base + RK3036_PLLCON(1));
+	rockchip_pll_wait_lock(pll);
 
 	return 0;
 }
@@ -500,6 +501,7 @@ static int rockchip_rk3066_pll_enable(struct clk_hw *hw)
 
 	writel(HIWORD_UPDATE(0, RK3066_PLLCON3_PWRDOWN, 0),
 	       pll->reg_base + RK3066_PLLCON(3));
+	rockchip_pll_wait_lock(pll);
 
 	return 0;
 }
@@ -745,6 +747,7 @@ static int rockchip_rk3399_pll_enable(struct clk_hw *hw)
 
 	writel(HIWORD_UPDATE(0, RK3399_PLLCON3_PWRDOWN, 0),
 	       pll->reg_base + RK3399_PLLCON(3));
+	rockchip_rk3399_pll_wait_lock(pll);
 
 	return 0;
 }
-- 
1.9.1

^ permalink raw reply related	[flat|nested] 4+ messages in thread

* [PATCH v1] clk: rockchip: add pll_wait_lock for pll_enable
@ 2017-02-22  2:59 ` Elaine Zhang
  0 siblings, 0 replies; 4+ messages in thread
From: Elaine Zhang @ 2017-02-22  2:59 UTC (permalink / raw)
  To: linux-arm-kernel

If pll is power down,when power up pll need wait pll lock.
The reference documents section:
	PLL frequency change and lock check

Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
---
 drivers/clk/rockchip/clk-pll.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/clk/rockchip/clk-pll.c b/drivers/clk/rockchip/clk-pll.c
index 6ed605776abd..c4dfd26f37ae 100644
--- a/drivers/clk/rockchip/clk-pll.c
+++ b/drivers/clk/rockchip/clk-pll.c
@@ -268,6 +268,7 @@ static int rockchip_rk3036_pll_enable(struct clk_hw *hw)
 
 	writel(HIWORD_UPDATE(0, RK3036_PLLCON1_PWRDOWN, 0),
 	       pll->reg_base + RK3036_PLLCON(1));
+	rockchip_pll_wait_lock(pll);
 
 	return 0;
 }
@@ -500,6 +501,7 @@ static int rockchip_rk3066_pll_enable(struct clk_hw *hw)
 
 	writel(HIWORD_UPDATE(0, RK3066_PLLCON3_PWRDOWN, 0),
 	       pll->reg_base + RK3066_PLLCON(3));
+	rockchip_pll_wait_lock(pll);
 
 	return 0;
 }
@@ -745,6 +747,7 @@ static int rockchip_rk3399_pll_enable(struct clk_hw *hw)
 
 	writel(HIWORD_UPDATE(0, RK3399_PLLCON3_PWRDOWN, 0),
 	       pll->reg_base + RK3399_PLLCON(3));
+	rockchip_rk3399_pll_wait_lock(pll);
 
 	return 0;
 }
-- 
1.9.1

^ permalink raw reply related	[flat|nested] 4+ messages in thread

* Re: [PATCH v1] clk: rockchip: add pll_wait_lock for pll_enable
  2017-02-22  2:59 ` Elaine Zhang
@ 2017-03-22 18:07   ` Heiko Stuebner
  -1 siblings, 0 replies; 4+ messages in thread
From: Heiko Stuebner @ 2017-03-22 18:07 UTC (permalink / raw)
  To: Elaine Zhang
  Cc: mturquette, sboyd, xf, linux-clk, huangtao, xxx, linux-rockchip,
	linux-kernel, linux-arm-kernel

Am Mittwoch, 22. Februar 2017, 10:59:55 CET schrieb Elaine Zhang:
> If pll is power down,when power up pll need wait pll lock.
> The reference documents section:
> 	PLL frequency change and lock check
> 
> Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>

applied to my clk-branch for 4.12


Thanks
Heiko

^ permalink raw reply	[flat|nested] 4+ messages in thread

* [PATCH v1] clk: rockchip: add pll_wait_lock for pll_enable
@ 2017-03-22 18:07   ` Heiko Stuebner
  0 siblings, 0 replies; 4+ messages in thread
From: Heiko Stuebner @ 2017-03-22 18:07 UTC (permalink / raw)
  To: linux-arm-kernel

Am Mittwoch, 22. Februar 2017, 10:59:55 CET schrieb Elaine Zhang:
> If pll is power down,when power up pll need wait pll lock.
> The reference documents section:
> 	PLL frequency change and lock check
> 
> Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>

applied to my clk-branch for 4.12


Thanks
Heiko

^ permalink raw reply	[flat|nested] 4+ messages in thread

end of thread, other threads:[~2017-03-22 18:08 UTC | newest]

Thread overview: 4+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2017-02-22  2:59 [PATCH v1] clk: rockchip: add pll_wait_lock for pll_enable Elaine Zhang
2017-02-22  2:59 ` Elaine Zhang
2017-03-22 18:07 ` Heiko Stuebner
2017-03-22 18:07   ` Heiko Stuebner

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