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From: Ley Foon Tan <ley.foon.tan@intel.com>
To: u-boot@lists.denx.de
Subject: [U-Boot] [PATCH 12/20] fdt: add compatible strings for Arria 10
Date: Wed, 22 Feb 2017 17:47:30 +0800	[thread overview]
Message-ID: <1487756858-16730-13-git-send-email-ley.foon.tan@intel.com> (raw)
In-Reply-To: <1487756858-16730-1-git-send-email-ley.foon.tan@intel.com>

Add compatible strings for Intel Arria 10 SoCFPGA device.

Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
---
 include/fdtdec.h | 8 ++++++++
 lib/fdtdec.c     | 8 ++++++++
 2 files changed, 16 insertions(+)

diff --git a/include/fdtdec.h b/include/fdtdec.h
index d074478..2134701 100644
--- a/include/fdtdec.h
+++ b/include/fdtdec.h
@@ -155,6 +155,14 @@ enum fdt_compat_id {
 	COMPAT_INTEL_BAYTRAIL_FSP_MDP,	/* Intel FSP memory-down params */
 	COMPAT_INTEL_IVYBRIDGE_FSP,	/* Intel Ivy Bridge FSP */
 	COMPAT_SUNXI_NAND,		/* SUNXI NAND controller */
+	COMPAT_ALTERA_SOCFPGA_CLK,	/* SoCFPGA Clock initialization */
+	COMPAT_ALTERA_SOCFPGA_PINCTRL_SINGLE,	/* SoCFPGA pinctrl-single */
+	COMPAT_ALTERA_SOCFPGA_H2F_BRG,          /* SoCFPGA hps2fpga bridge */
+	COMPAT_ALTERA_SOCFPGA_LWH2F_BRG,        /* SoCFPGA lwhps2fpga bridge */
+	COMPAT_ALTERA_SOCFPGA_F2H_BRG,          /* SoCFPGA fpga2hps bridge */
+	COMPAT_ALTERA_SOCFPGA_F2SDR0,           /* SoCFPGA fpga2SDRAM0 bridge */
+	COMPAT_ALTERA_SOCFPGA_F2SDR1,           /* SoCFPGA fpga2SDRAM1 bridge */
+	COMPAT_ALTERA_SOCFPGA_F2SDR2,           /* SoCFPGA fpga2SDRAM2 bridge */
 
 	COMPAT_COUNT,
 };
diff --git a/lib/fdtdec.c b/lib/fdtdec.c
index 81f47ef..ebe4a9a 100644
--- a/lib/fdtdec.c
+++ b/lib/fdtdec.c
@@ -66,6 +66,14 @@ static const char * const compat_names[COMPAT_COUNT] = {
 	COMPAT(INTEL_BAYTRAIL_FSP_MDP, "intel,baytrail-fsp-mdp"),
 	COMPAT(INTEL_IVYBRIDGE_FSP, "intel,ivybridge-fsp"),
 	COMPAT(COMPAT_SUNXI_NAND, "allwinner,sun4i-a10-nand"),
+	COMPAT(ALTERA_SOCFPGA_CLK, "altr,clk-mgr"),
+	COMPAT(ALTERA_SOCFPGA_PINCTRL_SINGLE, "pinctrl-single"),
+	COMPAT(ALTERA_SOCFPGA_H2F_BRG, "altr,socfpga-hps2fpga-bridge"),
+	COMPAT(ALTERA_SOCFPGA_LWH2F_BRG, "altr,socfpga-lwhps2fpga-bridge"),
+	COMPAT(ALTERA_SOCFPGA_F2H_BRG, "altr,socfpga-fpga2hps-bridge"),
+	COMPAT(ALTERA_SOCFPGA_F2SDR0, "altr,socfpga-fpga2sdram0-bridge"),
+	COMPAT(ALTERA_SOCFPGA_F2SDR1, "altr,socfpga-fpga2sdram1-bridge"),
+	COMPAT(ALTERA_SOCFPGA_F2SDR2, "altr,socfpga-fpga2sdram2-bridge"),
 };
 
 const char *fdtdec_get_compatible(enum fdt_compat_id id)
-- 
1.8.2.3

  parent reply	other threads:[~2017-02-22  9:47 UTC|newest]

Thread overview: 49+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2017-02-22  9:47 [U-Boot] [PATCH 00/20] Add Intel Arria 10 SoC support Ley Foon Tan
2017-02-22  9:47 ` [U-Boot] [PATCH 01/20] arm: socfpga: restructure clock manager driver Ley Foon Tan
2017-02-25 21:18   ` Marek Vasut
2017-02-27  8:36     ` Ley Foon Tan
2017-02-22  9:47 ` [U-Boot] [PATCH 02/20] arm: socfpga: restructure reset " Ley Foon Tan
2017-02-22  9:47 ` [U-Boot] [PATCH 03/20] arm: socfpga: restructure misc driver Ley Foon Tan
2017-02-22  9:47 ` [U-Boot] [PATCH 04/20] arm: socfpga: restructure system manager Ley Foon Tan
2017-02-22  9:47 ` [U-Boot] [PATCH 05/20] arm: socfpga: add A10 defines Ley Foon Tan
2017-02-25 21:20   ` Marek Vasut
     [not found]     ` <1488188711.2424.10.camel@intel.com>
2017-02-27 10:00       ` Marek Vasut
2017-02-22  9:47 ` [U-Boot] [PATCH 06/20] arm: socfpga: add reset driver support for Arria 10 Ley Foon Tan
2017-02-25 21:28   ` Marek Vasut
2017-02-27 10:14     ` Ley Foon Tan
2017-02-27 10:19       ` Marek Vasut
2017-02-28  2:31         ` Ley Foon Tan
2017-02-28  8:27       ` Ley Foon Tan
2017-02-28  8:39         ` Marek Vasut
2017-02-22  9:47 ` [U-Boot] [PATCH 07/20] arm: socfpga: add clock driver " Ley Foon Tan
2017-02-25 21:35   ` Marek Vasut
2017-03-06  7:10     ` Ley Foon Tan
2017-03-07  3:48       ` Marek Vasut
2017-02-22  9:47 ` [U-Boot] [PATCH 08/20] arm: socfpga: add system manager " Ley Foon Tan
2017-02-25 21:36   ` Marek Vasut
2017-03-06  7:39     ` Ley Foon Tan
2017-03-07  3:49       ` Marek Vasut
2017-03-07  9:07         ` Ley Foon Tan
2017-02-22  9:47 ` [U-Boot] [PATCH 09/20] arm: socfpga: add sdram header file " Ley Foon Tan
2017-02-22  9:47 ` [U-Boot] [PATCH 10/20] arm: socfpga: add misc support " Ley Foon Tan
2017-02-25 21:40   ` Marek Vasut
2017-03-06  8:00     ` Ley Foon Tan
2017-03-07  3:50       ` Marek Vasut
2017-02-22  9:47 ` [U-Boot] [PATCH 11/20] arm: socfpga: add pinmux " Ley Foon Tan
2017-02-25 21:41   ` Marek Vasut
2017-03-06  8:08     ` Ley Foon Tan
2017-02-22  9:47 ` Ley Foon Tan [this message]
2017-02-22  9:47 ` [U-Boot] [PATCH 13/20] arm: dts: add dts and dtsi " Ley Foon Tan
2017-02-22  9:47 ` [U-Boot] [PATCH 14/20] arm: socfpga: add SPL support " Ley Foon Tan
2017-02-25 21:43   ` Marek Vasut
2017-02-27  5:36     ` Chee, Tien Fong
2017-03-07  2:51     ` Ley Foon Tan
2017-02-22  9:47 ` [U-Boot] [PATCH 15/20] drivers: Makefile: include fpga build in SPL Ley Foon Tan
2017-02-25 21:44   ` Marek Vasut
2017-02-27 16:06     ` Michal Simek
2017-03-07  2:52       ` Ley Foon Tan
2017-02-22  9:47 ` [U-Boot] [PATCH 16/20] drivers: fpga: add compile switch for Gen5 only registers Ley Foon Tan
2017-02-22  9:47 ` [U-Boot] [PATCH 17/20] arm: socfpga: convert Altera ddr driver to use Kconfig Ley Foon Tan
2017-02-22  9:47 ` [U-Boot] [PATCH 18/20] arm: socfpga: add config and defconfig for Arria 10 Ley Foon Tan
2017-02-22  9:47 ` [U-Boot] [PATCH 19/20] arm: socfpga: add board files for the Arria10 Ley Foon Tan
2017-02-22  9:47 ` [U-Boot] [PATCH 20/20] arm: socfpga: enable build for Arria 10 Ley Foon Tan

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