From: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com>
To: qemu-ppc@nongnu.org, david@gibson.dropbear.id.au, rth@twiddle.net
Cc: qemu-devel@nongnu.org, bharata@linux.vnet.ibm.com,
nikunj@linux.vnet.ibm.com
Subject: [Qemu-devel] [PATCH v6 7/8] target/ppc: add ov32 flag in divide operations
Date: Mon, 27 Feb 2017 10:28:00 +0530 [thread overview]
Message-ID: <1488171481-21699-8-git-send-email-nikunj@linux.vnet.ibm.com> (raw)
In-Reply-To: <1488171481-21699-1-git-send-email-nikunj@linux.vnet.ibm.com>
Add helper_div_compute_ov() in the int_helper for updating the overflow
flags.
For Divide Word:
SO, OV, and OV32 bits reflects overflow of the 32-bit result
For Divide DoubleWord:
SO, OV, and OV32 bits reflects overflow of the 64-bit result
Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com>
Reviewed-by: Richard Henderson <rth@twiddle.net>
---
target/ppc/translate.c | 10 ++++++++--
1 file changed, 8 insertions(+), 2 deletions(-)
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index ccf3bff..982e66f 100644
--- a/target/ppc/translate.c
+++ b/target/ppc/translate.c
@@ -1021,6 +1021,9 @@ static inline void gen_op_arith_divw(DisasContext *ctx, TCGv ret, TCGv arg1,
}
if (compute_ov) {
tcg_gen_extu_i32_tl(cpu_ov, t2);
+ if (is_isa300(ctx)) {
+ tcg_gen_extu_i32_tl(cpu_ov32, t2);
+ }
tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov);
}
tcg_temp_free_i32(t0);
@@ -1092,6 +1095,9 @@ static inline void gen_op_arith_divd(DisasContext *ctx, TCGv ret, TCGv arg1,
}
if (compute_ov) {
tcg_gen_mov_tl(cpu_ov, t2);
+ if (is_isa300(ctx)) {
+ tcg_gen_mov_tl(cpu_ov32, t2);
+ }
tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov);
}
tcg_temp_free_i64(t0);
@@ -1110,10 +1116,10 @@ static void glue(gen_, name)(DisasContext *ctx)
cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
sign, compute_ov); \
}
-/* divwu divwu. divwuo divwuo. */
+/* divdu divdu. divduo divduo. */
GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0);
GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1);
-/* divw divw. divwo divwo. */
+/* divd divd. divdo divdo. */
GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0);
GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1);
--
2.7.4
next prev parent reply other threads:[~2017-02-27 4:58 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-02-27 4:57 [Qemu-devel] [PATCH v6 0/8] POWER9 TCG enablements - part15 Nikunj A Dadhania
2017-02-27 4:57 ` [Qemu-devel] [PATCH v6 1/8] target/ppc: support for 32-bit carry and overflow Nikunj A Dadhania
2017-02-27 4:57 ` [Qemu-devel] [PATCH v6 2/8] target/ppc: update ca32 in arithmetic add Nikunj A Dadhania
2017-02-27 4:57 ` [Qemu-devel] [PATCH v6 3/8] target/ppc: update ca32 in arithmetic substract Nikunj A Dadhania
2017-02-27 4:57 ` [Qemu-devel] [PATCH v6 4/8] target/ppc: update overflow flags for add/sub Nikunj A Dadhania
2017-02-27 4:57 ` [Qemu-devel] [PATCH v6 5/8] target/ppc: use tcg ops for neg instruction Nikunj A Dadhania
2017-02-27 4:57 ` [Qemu-devel] [PATCH v6 6/8] target/ppc: add ov32 flag for multiply low insns Nikunj A Dadhania
2017-02-27 4:58 ` Nikunj A Dadhania [this message]
2017-02-27 4:58 ` [Qemu-devel] [PATCH v6 8/8] target/ppc: add mcrxrx instruction Nikunj A Dadhania
2017-02-27 23:21 ` [Qemu-devel] [PATCH v6 0/8] POWER9 TCG enablements - part15 David Gibson
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