From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752239AbdCCKSW (ORCPT ); Fri, 3 Mar 2017 05:18:22 -0500 Received: from mailout1.samsung.com ([203.254.224.24]:56181 "EHLO mailout1.samsung.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752044AbdCCKSN (ORCPT ); Fri, 3 Mar 2017 05:18:13 -0500 X-AuditID: b6c32a2d-f793d6d0000012b6-02-58b931acadaf From: Smitha T Murthy To: linux-arm-kernel@lists.infradead.org, linux-media@vger.kernel.org, linux-kernel@vger.kernel.org Cc: kyungmin.park@samsung.com, kamil@wypas.org, jtp.park@samsung.com, a.hajda@samsung.com, mchehab@kernel.org, pankaj.dubey@samsung.com, krzk@kernel.org, m.szyprowski@samsung.com, s.nawrocki@samsung.com, Smitha T Murthy Subject: [Patch v2 04/11] s5p-mfc: Support MFCv10.10 buffer requirements Date: Fri, 03 Mar 2017 14:37:09 +0530 Message-id: <1488532036-13044-5-git-send-email-smitha.t@samsung.com> X-Mailer: git-send-email 1.7.2.3 In-reply-to: <1488532036-13044-1-git-send-email-smitha.t@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFnrGIsWRmVeSWpSXmKPExsWy7bCmuu4aw50RBjeOmlncWneO1eLI2qtM FjNPtLNanD+/gd3ibNMbdotNj6+xWlzeNYfNomfDVlaLtUfuslss2/SHyWLR1i/sFoffABXf 3bON0YHXY9OqTjaPzUvqPfq2rGL0+LxJzuPKkUb2ANYoLpuU1JzMstQifbsEroyuZyuYCuY6 VdyfZt/A2GPWxcjBISFgItG8PrKLkRPIFJO4cG89G4gtJLCUUeLprpouRi4gu51J4t+sA4wQ RSYSmz8uZ4FIzGGUWHh6PTtEx39GicO7wYrYBHQkvr0/DTZJRCBV4tW6tawgDcwCPxglbn27 wQKSEBbwkFh9bTJYEYuAqsSNQ5NZQWxeAReJXcdmQG1TkHh1Yy3YAk4BV4kNy3YwgQySEJjH LnF1/WkmiBdkJTYdYIaod5H4vO8dG4QtLPHq+BZ2CFta4u/SW4wQvc2MEnO3NbNAJCYwSqxs LYWw7SUOXJkDFmcW4JPo/f0Eaj6vREebEESJh8Sph9OgdjlKnDu3gRESEjMYJbZsvsc2gVFm ASPDKkax1ILi3PTUYtMCI73ixNzi0rx0veT83E2M4NjX0t3B+GWB9yFGAQ5GJR7eCumdEUKs iWXFlbmHGCU4mJVEeNP27ogQ4k1JrKxKLcqPLyrNSS0+xCjNwaIkzhtlMDFCSCA9sSQ1OzW1 ILUIJsvEwSnVwOhyZpPG3gdd24wd7HJsnGbuDnGccSHlHNd9bu9sm1XMQYs8u6Y58fi9/nLq 2baPUQaspQov/09yXt24OGmZYXT2IW324x177jm/mPr4S8v2o8p1Om77Exc+tC6PenRvot4f O83m/fI+KblxB8PXtP5/47lCJWnVGnuP3TGfJr9z+L3vGnfhLn8lluKMREMt5qLiRADhtB/m +QIAAA== X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFupikeLIzCtJLcpLzFFi42I5/e+xoO4aw50RBhOealjcWneO1eLI2qtM FjNPtLNanD+/gd3ibNMbdotNj6+xWlzeNYfNomfDVlaLtUfuslss2/SHyWLR1i/sFoffABXf 3bON0YHXY9OqTjaPzUvqPfq2rGL0+LxJzuPKkUb2ANYoN5uM1MSU1CKF1Lzk/JTMvHRbpdAQ N10LJYW8xNxUW6UIXd+QICWFssScUiDPyAANODgHuAcr6dsluGV0PVvBVDDXqeL+NPsGxh6z LkZODgkBE4nNH5ezQNhiEhfurWfrYuTiEBKYxShxen4vlNPIJLH94GtGkCo2AR2Jb+9Ps4HY IgKpEmu3nmcFKWIW+MEo0XTgJTtIQljAQ2L1tclgRSwCqhI3Dk1mBbF5BVwkdh2bwQixTkHi 1Y21YPWcAq4SG5btYAKxhYBqZj14xDaBkXcBI8MqRonUguSC4qT0XKO81HK94sTc4tK8dL3k /NxNjOB4eCa9g/HwLvdDjAIcjEo8vBdsdkQIsSaWFVfmHmKU4GBWEuFN2wsU4k1JrKxKLcqP LyrNSS0+xGgKdNhEZinR5HxgrOaVxBuamJuYGxtYmFtamhgpifM2zn4WLiSQnliSmp2aWpBa BNPHxMEp1cCoL9y7J59Ldmc319be055zlqjtjqtzO9LGEp79bdGPXsm3Ra4lbKkBr1eVaaxx bDleuS/UzcdNhnkvs7Xp3egJtn1aZppzgq/ccy8MlqoMmvxUj3nfs9P3Gu6KtRgcmu5wZfaL N5H3H/iz3PonnvG16pSav0nx1JvlmnxG0X07CutOvPvu91KJpTgj0VCLuag4EQCrnWAGnQIA AA== X-MTR: 20000000000000000@CPGS X-CMS-MailID: 20170303090444epcas5p338f4cd2b1746da117f69907ca09e0ea9 X-Msg-Generator: CA X-Sender-IP: 203.254.230.27 X-Local-Sender: =?UTF-8?B?U21pdGhhIFQgTXVydGh5G1NTSVItVHVybiBLZXkgU29sdXRp?= =?UTF-8?B?b25zG+yCvOyEseyghOyekBtMZWFkIEVuZ2luZWVy?= X-Global-Sender: =?UTF-8?B?U21pdGhhIFQgTXVydGh5G1NTSVItVHVybiBLZXkgU29sdXRp?= =?UTF-8?B?b25zG1NhbXN1bmcgRWxlY3Ryb25pY3MbTGVhZCBFbmdpbmVlcg==?= X-Sender-Code: =?UTF-8?B?QzEwG1NXQUhRG0MxMElEMDdJRDAxMDk5Nw==?= CMS-TYPE: 105P X-HopCount: 7 X-CMS-RootMailID: 20170303090444epcas5p338f4cd2b1746da117f69907ca09e0ea9 X-RootMTR: 20170303090444epcas5p338f4cd2b1746da117f69907ca09e0ea9 References: <1488532036-13044-1-git-send-email-smitha.t@samsung.com> Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Aligning the luma_dpb_size, chroma_dpb_size, mv_size and me_buffer_size for MFCv10.10. Signed-off-by: Smitha T Murthy --- drivers/media/platform/s5p-mfc/regs-mfc-v10.h | 19 +++++ drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c | 99 ++++++++++++++++++----- drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.h | 2 + 3 files changed, 99 insertions(+), 21 deletions(-) diff --git a/drivers/media/platform/s5p-mfc/regs-mfc-v10.h b/drivers/media/platform/s5p-mfc/regs-mfc-v10.h index bd671a5..dafcf9d 100644 --- a/drivers/media/platform/s5p-mfc/regs-mfc-v10.h +++ b/drivers/media/platform/s5p-mfc/regs-mfc-v10.h @@ -32,5 +32,24 @@ #define MFC_VERSION_V10 0xA0 #define MFC_NUM_PORTS_V10 1 +/* MFCv10 codec defines*/ +#define S5P_FIMV_CODEC_HEVC_ENC 26 + +/* Encoder buffer size for MFC v10.0 */ +#define ENC_V100_BASE_SIZE(x, y) \ + (((x + 3) * (y + 3) * 8) \ + + ((y * 64) + 1280) * DIV_ROUND_UP(x, 8)) + +#define ENC_V100_H264_ME_SIZE(x, y) \ + (ENC_V100_BASE_SIZE(x, y) \ + + (DIV_ROUND_UP(x * y, 64) * 32)) + +#define ENC_V100_MPEG4_ME_SIZE(x, y) \ + (ENC_V100_BASE_SIZE(x, y) \ + + (DIV_ROUND_UP(x * y, 128) * 16)) + +#define ENC_V100_VP8_ME_SIZE(x, y) \ + ENC_V100_BASE_SIZE(x, y) + #endif /*_REGS_MFC_V10_H*/ diff --git a/drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c b/drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c index 5f0da0b..d4c75eb 100644 --- a/drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c +++ b/drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c @@ -45,6 +45,8 @@ #define IS_MFCV6_V2(dev) (!IS_MFCV7_PLUS(dev) && dev->fw_ver == MFC_FW_V2) +#define calc_param(value, align) (DIV_ROUND_UP(value, align) * align) + /* Allocate temporary buffers for decoding */ static int s5p_mfc_alloc_dec_temp_buffers_v6(struct s5p_mfc_ctx *ctx) { @@ -64,6 +66,7 @@ static int s5p_mfc_alloc_codec_buffers_v6(struct s5p_mfc_ctx *ctx) { struct s5p_mfc_dev *dev = ctx->dev; unsigned int mb_width, mb_height; + unsigned int lcu_width = 0, lcu_height = 0; int ret; mb_width = MB_WIDTH(ctx->img_width); @@ -74,7 +77,9 @@ static int s5p_mfc_alloc_codec_buffers_v6(struct s5p_mfc_ctx *ctx) ctx->luma_size, ctx->chroma_size, ctx->mv_size); mfc_debug(2, "Totals bufs: %d\n", ctx->total_dpb_count); } else if (ctx->type == MFCINST_ENCODER) { - if (IS_MFCV8_PLUS(dev)) + if (IS_MFCV10(dev)) { + ctx->tmv_buffer_size = 0; + } else if (IS_MFCV8_PLUS(dev)) ctx->tmv_buffer_size = S5P_FIMV_NUM_TMV_BUFFERS_V6 * ALIGN(S5P_FIMV_TMV_BUFFER_SIZE_V8(mb_width, mb_height), S5P_FIMV_TMV_BUFFER_ALIGN_V6); @@ -82,13 +87,36 @@ static int s5p_mfc_alloc_codec_buffers_v6(struct s5p_mfc_ctx *ctx) ctx->tmv_buffer_size = S5P_FIMV_NUM_TMV_BUFFERS_V6 * ALIGN(S5P_FIMV_TMV_BUFFER_SIZE_V6(mb_width, mb_height), S5P_FIMV_TMV_BUFFER_ALIGN_V6); - - ctx->luma_dpb_size = ALIGN((mb_width * mb_height) * - S5P_FIMV_LUMA_MB_TO_PIXEL_V6, - S5P_FIMV_LUMA_DPB_BUFFER_ALIGN_V6); - ctx->chroma_dpb_size = ALIGN((mb_width * mb_height) * - S5P_FIMV_CHROMA_MB_TO_PIXEL_V6, - S5P_FIMV_CHROMA_DPB_BUFFER_ALIGN_V6); + if (IS_MFCV10(dev)) { + lcu_width = enc_lcu_width(ctx->img_width); + lcu_height = enc_lcu_height(ctx->img_height); + if (ctx->codec_mode != S5P_FIMV_CODEC_HEVC_ENC) { + ctx->luma_dpb_size = + ALIGN(calc_param((mb_width * 16), 64) + * calc_param((mb_height * 16), 32) + + 64, 64); + ctx->chroma_dpb_size = + ALIGN(calc_param((mb_width * 16), 64) + * (mb_height * 8) + + 64, 64); + } else { + ctx->luma_dpb_size = + ALIGN(calc_param((lcu_width * 32), 64) + * calc_param((lcu_height * 32), 32) + + 64, 64); + ctx->chroma_dpb_size = + ALIGN(calc_param((lcu_width * 32), 64) + * (lcu_height * 16) + + 64, 64); + } + } else { + ctx->luma_dpb_size = ALIGN((mb_width * mb_height) * + S5P_FIMV_LUMA_MB_TO_PIXEL_V6, + S5P_FIMV_LUMA_DPB_BUFFER_ALIGN_V6); + ctx->chroma_dpb_size = ALIGN((mb_width * mb_height) * + S5P_FIMV_CHROMA_MB_TO_PIXEL_V6, + S5P_FIMV_CHROMA_DPB_BUFFER_ALIGN_V6); + } if (IS_MFCV8_PLUS(dev)) ctx->me_buffer_size = ALIGN(S5P_FIMV_ME_BUFFER_SIZE_V8( ctx->img_width, ctx->img_height, @@ -197,6 +225,8 @@ static int s5p_mfc_alloc_codec_buffers_v6(struct s5p_mfc_ctx *ctx) case S5P_MFC_CODEC_H264_ENC: if (IS_MFCV10(dev)) { mfc_debug(2, "Use min scratch buffer size\n"); + ctx->me_buffer_size = + ALIGN(ENC_V100_H264_ME_SIZE(mb_width, mb_height), 16); } else if (IS_MFCV8_PLUS(dev)) ctx->scratch_buf_size = S5P_FIMV_SCRATCH_BUF_SIZE_H264_ENC_V8( @@ -219,6 +249,9 @@ static int s5p_mfc_alloc_codec_buffers_v6(struct s5p_mfc_ctx *ctx) case S5P_MFC_CODEC_H263_ENC: if (IS_MFCV10(dev)) { mfc_debug(2, "Use min scratch buffer size\n"); + ctx->me_buffer_size = + ALIGN(ENC_V100_MPEG4_ME_SIZE(mb_width, + mb_height), 16); } else ctx->scratch_buf_size = S5P_FIMV_SCRATCH_BUF_SIZE_MPEG4_ENC_V6( @@ -235,7 +268,10 @@ static int s5p_mfc_alloc_codec_buffers_v6(struct s5p_mfc_ctx *ctx) case S5P_MFC_CODEC_VP8_ENC: if (IS_MFCV10(dev)) { mfc_debug(2, "Use min scratch buffer size\n"); - } else if (IS_MFCV8_PLUS(dev)) + ctx->me_buffer_size = + ALIGN(ENC_V100_VP8_ME_SIZE(mb_width, mb_height), + 16); + } else if (IS_MFCV8_PLUS(dev)) ctx->scratch_buf_size = S5P_FIMV_SCRATCH_BUF_SIZE_VP8_ENC_V8( mb_width, @@ -395,13 +431,15 @@ static void s5p_mfc_dec_calc_dpb_size_v6(struct s5p_mfc_ctx *ctx) if (ctx->codec_mode == S5P_MFC_CODEC_H264_DEC || ctx->codec_mode == S5P_MFC_CODEC_H264_MVC_DEC) { - if (IS_MFCV10(dev)) + if (IS_MFCV10(dev)) { ctx->mv_size = S5P_MFC_DEC_MV_SIZE_V10(ctx->img_width, ctx->img_height); - else + ctx->mv_size = ALIGN(ctx->mv_size, 32); + } else { ctx->mv_size = S5P_MFC_DEC_MV_SIZE_V6(ctx->img_width, ctx->img_height); - ctx->mv_size = ALIGN(ctx->mv_size, 16); + ctx->mv_size = ALIGN(ctx->mv_size, 16); + } } else { ctx->mv_size = 0; } @@ -598,15 +636,34 @@ static int s5p_mfc_set_enc_ref_buffer_v6(struct s5p_mfc_ctx *ctx) mfc_debug(2, "Buf1: %p (%d)\n", (void *)buf_addr1, buf_size1); - for (i = 0; i < ctx->pb_count; i++) { - writel(buf_addr1, mfc_regs->e_luma_dpb + (4 * i)); - buf_addr1 += ctx->luma_dpb_size; - writel(buf_addr1, mfc_regs->e_chroma_dpb + (4 * i)); - buf_addr1 += ctx->chroma_dpb_size; - writel(buf_addr1, mfc_regs->e_me_buffer + (4 * i)); - buf_addr1 += ctx->me_buffer_size; - buf_size1 -= (ctx->luma_dpb_size + ctx->chroma_dpb_size + - ctx->me_buffer_size); + if (IS_MFCV10(dev)) { + /* start address of per buffer is aligned */ + for (i = 0; i < ctx->pb_count; i++) { + writel(buf_addr1, mfc_regs->e_luma_dpb + (4 * i)); + buf_addr1 += ctx->luma_dpb_size; + buf_size1 -= ctx->luma_dpb_size; + } + for (i = 0; i < ctx->pb_count; i++) { + writel(buf_addr1, mfc_regs->e_chroma_dpb + (4 * i)); + buf_addr1 += ctx->chroma_dpb_size; + buf_size1 -= ctx->chroma_dpb_size; + } + for (i = 0; i < ctx->pb_count; i++) { + writel(buf_addr1, mfc_regs->e_me_buffer + (4 * i)); + buf_addr1 += ctx->me_buffer_size; + buf_size1 -= ctx->me_buffer_size; + } + } else { + for (i = 0; i < ctx->pb_count; i++) { + writel(buf_addr1, mfc_regs->e_luma_dpb + (4 * i)); + buf_addr1 += ctx->luma_dpb_size; + writel(buf_addr1, mfc_regs->e_chroma_dpb + (4 * i)); + buf_addr1 += ctx->chroma_dpb_size; + writel(buf_addr1, mfc_regs->e_me_buffer + (4 * i)); + buf_addr1 += ctx->me_buffer_size; + buf_size1 -= (ctx->luma_dpb_size + ctx->chroma_dpb_size + + ctx->me_buffer_size); + } } writel(buf_addr1, mfc_regs->e_scratch_buffer_addr); diff --git a/drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.h b/drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.h index 021b8db..975bbc5 100644 --- a/drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.h +++ b/drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.h @@ -26,6 +26,8 @@ (((MB_HEIGHT(y)+1)/2)*2) * 64 + 128) #define S5P_MFC_DEC_MV_SIZE_V10(x, y) (MB_WIDTH(x) * \ (((MB_HEIGHT(y)+1)/2)*2) * 64 + 512) +#define enc_lcu_width(x_size) DIV_ROUND_UP(x_size, 32) +#define enc_lcu_height(y_size) DIV_ROUND_UP(y_size, 32) /* Definition */ #define ENC_MULTI_SLICE_MB_MAX ((1 << 30) - 1) -- 1.7.2.3 From mboxrd@z Thu Jan 1 00:00:00 1970 From: smitha.t@samsung.com (Smitha T Murthy) Date: Fri, 03 Mar 2017 14:37:09 +0530 Subject: [Patch v2 04/11] s5p-mfc: Support MFCv10.10 buffer requirements In-Reply-To: <1488532036-13044-1-git-send-email-smitha.t@samsung.com> References: <1488532036-13044-1-git-send-email-smitha.t@samsung.com> Message-ID: <1488532036-13044-5-git-send-email-smitha.t@samsung.com> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org Aligning the luma_dpb_size, chroma_dpb_size, mv_size and me_buffer_size for MFCv10.10. Signed-off-by: Smitha T Murthy --- drivers/media/platform/s5p-mfc/regs-mfc-v10.h | 19 +++++ drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c | 99 ++++++++++++++++++----- drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.h | 2 + 3 files changed, 99 insertions(+), 21 deletions(-) diff --git a/drivers/media/platform/s5p-mfc/regs-mfc-v10.h b/drivers/media/platform/s5p-mfc/regs-mfc-v10.h index bd671a5..dafcf9d 100644 --- a/drivers/media/platform/s5p-mfc/regs-mfc-v10.h +++ b/drivers/media/platform/s5p-mfc/regs-mfc-v10.h @@ -32,5 +32,24 @@ #define MFC_VERSION_V10 0xA0 #define MFC_NUM_PORTS_V10 1 +/* MFCv10 codec defines*/ +#define S5P_FIMV_CODEC_HEVC_ENC 26 + +/* Encoder buffer size for MFC v10.0 */ +#define ENC_V100_BASE_SIZE(x, y) \ + (((x + 3) * (y + 3) * 8) \ + + ((y * 64) + 1280) * DIV_ROUND_UP(x, 8)) + +#define ENC_V100_H264_ME_SIZE(x, y) \ + (ENC_V100_BASE_SIZE(x, y) \ + + (DIV_ROUND_UP(x * y, 64) * 32)) + +#define ENC_V100_MPEG4_ME_SIZE(x, y) \ + (ENC_V100_BASE_SIZE(x, y) \ + + (DIV_ROUND_UP(x * y, 128) * 16)) + +#define ENC_V100_VP8_ME_SIZE(x, y) \ + ENC_V100_BASE_SIZE(x, y) + #endif /*_REGS_MFC_V10_H*/ diff --git a/drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c b/drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c index 5f0da0b..d4c75eb 100644 --- a/drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c +++ b/drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c @@ -45,6 +45,8 @@ #define IS_MFCV6_V2(dev) (!IS_MFCV7_PLUS(dev) && dev->fw_ver == MFC_FW_V2) +#define calc_param(value, align) (DIV_ROUND_UP(value, align) * align) + /* Allocate temporary buffers for decoding */ static int s5p_mfc_alloc_dec_temp_buffers_v6(struct s5p_mfc_ctx *ctx) { @@ -64,6 +66,7 @@ static int s5p_mfc_alloc_codec_buffers_v6(struct s5p_mfc_ctx *ctx) { struct s5p_mfc_dev *dev = ctx->dev; unsigned int mb_width, mb_height; + unsigned int lcu_width = 0, lcu_height = 0; int ret; mb_width = MB_WIDTH(ctx->img_width); @@ -74,7 +77,9 @@ static int s5p_mfc_alloc_codec_buffers_v6(struct s5p_mfc_ctx *ctx) ctx->luma_size, ctx->chroma_size, ctx->mv_size); mfc_debug(2, "Totals bufs: %d\n", ctx->total_dpb_count); } else if (ctx->type == MFCINST_ENCODER) { - if (IS_MFCV8_PLUS(dev)) + if (IS_MFCV10(dev)) { + ctx->tmv_buffer_size = 0; + } else if (IS_MFCV8_PLUS(dev)) ctx->tmv_buffer_size = S5P_FIMV_NUM_TMV_BUFFERS_V6 * ALIGN(S5P_FIMV_TMV_BUFFER_SIZE_V8(mb_width, mb_height), S5P_FIMV_TMV_BUFFER_ALIGN_V6); @@ -82,13 +87,36 @@ static int s5p_mfc_alloc_codec_buffers_v6(struct s5p_mfc_ctx *ctx) ctx->tmv_buffer_size = S5P_FIMV_NUM_TMV_BUFFERS_V6 * ALIGN(S5P_FIMV_TMV_BUFFER_SIZE_V6(mb_width, mb_height), S5P_FIMV_TMV_BUFFER_ALIGN_V6); - - ctx->luma_dpb_size = ALIGN((mb_width * mb_height) * - S5P_FIMV_LUMA_MB_TO_PIXEL_V6, - S5P_FIMV_LUMA_DPB_BUFFER_ALIGN_V6); - ctx->chroma_dpb_size = ALIGN((mb_width * mb_height) * - S5P_FIMV_CHROMA_MB_TO_PIXEL_V6, - S5P_FIMV_CHROMA_DPB_BUFFER_ALIGN_V6); + if (IS_MFCV10(dev)) { + lcu_width = enc_lcu_width(ctx->img_width); + lcu_height = enc_lcu_height(ctx->img_height); + if (ctx->codec_mode != S5P_FIMV_CODEC_HEVC_ENC) { + ctx->luma_dpb_size = + ALIGN(calc_param((mb_width * 16), 64) + * calc_param((mb_height * 16), 32) + + 64, 64); + ctx->chroma_dpb_size = + ALIGN(calc_param((mb_width * 16), 64) + * (mb_height * 8) + + 64, 64); + } else { + ctx->luma_dpb_size = + ALIGN(calc_param((lcu_width * 32), 64) + * calc_param((lcu_height * 32), 32) + + 64, 64); + ctx->chroma_dpb_size = + ALIGN(calc_param((lcu_width * 32), 64) + * (lcu_height * 16) + + 64, 64); + } + } else { + ctx->luma_dpb_size = ALIGN((mb_width * mb_height) * + S5P_FIMV_LUMA_MB_TO_PIXEL_V6, + S5P_FIMV_LUMA_DPB_BUFFER_ALIGN_V6); + ctx->chroma_dpb_size = ALIGN((mb_width * mb_height) * + S5P_FIMV_CHROMA_MB_TO_PIXEL_V6, + S5P_FIMV_CHROMA_DPB_BUFFER_ALIGN_V6); + } if (IS_MFCV8_PLUS(dev)) ctx->me_buffer_size = ALIGN(S5P_FIMV_ME_BUFFER_SIZE_V8( ctx->img_width, ctx->img_height, @@ -197,6 +225,8 @@ static int s5p_mfc_alloc_codec_buffers_v6(struct s5p_mfc_ctx *ctx) case S5P_MFC_CODEC_H264_ENC: if (IS_MFCV10(dev)) { mfc_debug(2, "Use min scratch buffer size\n"); + ctx->me_buffer_size = + ALIGN(ENC_V100_H264_ME_SIZE(mb_width, mb_height), 16); } else if (IS_MFCV8_PLUS(dev)) ctx->scratch_buf_size = S5P_FIMV_SCRATCH_BUF_SIZE_H264_ENC_V8( @@ -219,6 +249,9 @@ static int s5p_mfc_alloc_codec_buffers_v6(struct s5p_mfc_ctx *ctx) case S5P_MFC_CODEC_H263_ENC: if (IS_MFCV10(dev)) { mfc_debug(2, "Use min scratch buffer size\n"); + ctx->me_buffer_size = + ALIGN(ENC_V100_MPEG4_ME_SIZE(mb_width, + mb_height), 16); } else ctx->scratch_buf_size = S5P_FIMV_SCRATCH_BUF_SIZE_MPEG4_ENC_V6( @@ -235,7 +268,10 @@ static int s5p_mfc_alloc_codec_buffers_v6(struct s5p_mfc_ctx *ctx) case S5P_MFC_CODEC_VP8_ENC: if (IS_MFCV10(dev)) { mfc_debug(2, "Use min scratch buffer size\n"); - } else if (IS_MFCV8_PLUS(dev)) + ctx->me_buffer_size = + ALIGN(ENC_V100_VP8_ME_SIZE(mb_width, mb_height), + 16); + } else if (IS_MFCV8_PLUS(dev)) ctx->scratch_buf_size = S5P_FIMV_SCRATCH_BUF_SIZE_VP8_ENC_V8( mb_width, @@ -395,13 +431,15 @@ static void s5p_mfc_dec_calc_dpb_size_v6(struct s5p_mfc_ctx *ctx) if (ctx->codec_mode == S5P_MFC_CODEC_H264_DEC || ctx->codec_mode == S5P_MFC_CODEC_H264_MVC_DEC) { - if (IS_MFCV10(dev)) + if (IS_MFCV10(dev)) { ctx->mv_size = S5P_MFC_DEC_MV_SIZE_V10(ctx->img_width, ctx->img_height); - else + ctx->mv_size = ALIGN(ctx->mv_size, 32); + } else { ctx->mv_size = S5P_MFC_DEC_MV_SIZE_V6(ctx->img_width, ctx->img_height); - ctx->mv_size = ALIGN(ctx->mv_size, 16); + ctx->mv_size = ALIGN(ctx->mv_size, 16); + } } else { ctx->mv_size = 0; } @@ -598,15 +636,34 @@ static int s5p_mfc_set_enc_ref_buffer_v6(struct s5p_mfc_ctx *ctx) mfc_debug(2, "Buf1: %p (%d)\n", (void *)buf_addr1, buf_size1); - for (i = 0; i < ctx->pb_count; i++) { - writel(buf_addr1, mfc_regs->e_luma_dpb + (4 * i)); - buf_addr1 += ctx->luma_dpb_size; - writel(buf_addr1, mfc_regs->e_chroma_dpb + (4 * i)); - buf_addr1 += ctx->chroma_dpb_size; - writel(buf_addr1, mfc_regs->e_me_buffer + (4 * i)); - buf_addr1 += ctx->me_buffer_size; - buf_size1 -= (ctx->luma_dpb_size + ctx->chroma_dpb_size + - ctx->me_buffer_size); + if (IS_MFCV10(dev)) { + /* start address of per buffer is aligned */ + for (i = 0; i < ctx->pb_count; i++) { + writel(buf_addr1, mfc_regs->e_luma_dpb + (4 * i)); + buf_addr1 += ctx->luma_dpb_size; + buf_size1 -= ctx->luma_dpb_size; + } + for (i = 0; i < ctx->pb_count; i++) { + writel(buf_addr1, mfc_regs->e_chroma_dpb + (4 * i)); + buf_addr1 += ctx->chroma_dpb_size; + buf_size1 -= ctx->chroma_dpb_size; + } + for (i = 0; i < ctx->pb_count; i++) { + writel(buf_addr1, mfc_regs->e_me_buffer + (4 * i)); + buf_addr1 += ctx->me_buffer_size; + buf_size1 -= ctx->me_buffer_size; + } + } else { + for (i = 0; i < ctx->pb_count; i++) { + writel(buf_addr1, mfc_regs->e_luma_dpb + (4 * i)); + buf_addr1 += ctx->luma_dpb_size; + writel(buf_addr1, mfc_regs->e_chroma_dpb + (4 * i)); + buf_addr1 += ctx->chroma_dpb_size; + writel(buf_addr1, mfc_regs->e_me_buffer + (4 * i)); + buf_addr1 += ctx->me_buffer_size; + buf_size1 -= (ctx->luma_dpb_size + ctx->chroma_dpb_size + + ctx->me_buffer_size); + } } writel(buf_addr1, mfc_regs->e_scratch_buffer_addr); diff --git a/drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.h b/drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.h index 021b8db..975bbc5 100644 --- a/drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.h +++ b/drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.h @@ -26,6 +26,8 @@ (((MB_HEIGHT(y)+1)/2)*2) * 64 + 128) #define S5P_MFC_DEC_MV_SIZE_V10(x, y) (MB_WIDTH(x) * \ (((MB_HEIGHT(y)+1)/2)*2) * 64 + 512) +#define enc_lcu_width(x_size) DIV_ROUND_UP(x_size, 32) +#define enc_lcu_height(y_size) DIV_ROUND_UP(y_size, 32) /* Definition */ #define ENC_MULTI_SLICE_MB_MAX ((1 << 30) - 1) -- 1.7.2.3