From mboxrd@z Thu Jan  1 00:00:00 1970
From: Hemant Agrawal <hemant.agrawal@nxp.com>
Subject: [PATCHv8 21/46] bus/fslmc: define queues for DPAA2
	devices
Date: Fri, 3 Mar 2017 18:16:38 +0530
Message-ID: <1488545223-25739-22-git-send-email-hemant.agrawal@nxp.com>
References: <1487205586-6785-1-git-send-email-hemant.agrawal@nxp.com>
 <1488545223-25739-1-git-send-email-hemant.agrawal@nxp.com>
Mime-Version: 1.0
Content-Type: text/plain
Cc: <thomas.monjalon@6wind.com>, <bruce.richardson@intel.com>,
 <shreyansh.jain@nxp.com>, <john.mcnamara@intel.com>,
 <ferruh.yigit@intel.com>, <jerin.jacob@caviumnetworks.com>
To: <dev@dpdk.org>
Return-path: <dev-bounces@dpdk.org>
Received: from NAM01-BY2-obe.outbound.protection.outlook.com
 (mail-by2nam01on0068.outbound.protection.outlook.com [104.47.34.68])
 by dpdk.org (Postfix) with ESMTP id 46867F966
 for <dev@dpdk.org>; Fri,  3 Mar 2017 08:14:17 +0100 (CET)
In-Reply-To: <1488545223-25739-1-git-send-email-hemant.agrawal@nxp.com>
List-Id: DPDK patches and discussions <dev.dpdk.org>
List-Unsubscribe: <http://dpdk.org/ml/options/dev>,
 <mailto:dev-request@dpdk.org?subject=unsubscribe>
List-Archive: <http://dpdk.org/ml/archives/dev/>
List-Post: <mailto:dev@dpdk.org>
List-Help: <mailto:dev-request@dpdk.org?subject=help>
List-Subscribe: <http://dpdk.org/ml/listinfo/dev>,
 <mailto:dev-request@dpdk.org?subject=subscribe>
Errors-To: dev-bounces@dpdk.org
Sender: "dev" <dev-bounces@dpdk.org>

Before DPAA2 devices can communicate using hardware queues, this patch
adds queue definitions in the FSLMC bus which the DPAA2 devices would
instantitate.

Signed-off-by: Hemant Agrawal <hemant.agrawal@nxp.com>
---
 drivers/bus/fslmc/portal/dpaa2_hw_pvt.h | 20 ++++++++++++++++++++
 1 file changed, 20 insertions(+)

diff --git a/drivers/bus/fslmc/portal/dpaa2_hw_pvt.h b/drivers/bus/fslmc/portal/dpaa2_hw_pvt.h
index ad2847f..42c5517 100644
--- a/drivers/bus/fslmc/portal/dpaa2_hw_pvt.h
+++ b/drivers/bus/fslmc/portal/dpaa2_hw_pvt.h
@@ -37,9 +37,12 @@
 #include <mc/fsl_mc_sys.h>
 #include <fsl_qbman_portal.h>
 
+#define DPAA2_DQRR_RING_SIZE	16
+	/** <Maximum number of slots available in RX ring*/
 
 #define MC_PORTAL_INDEX		0
 #define NUM_DPIO_REGIONS	2
+#define NUM_DQS_PER_QUEUE       2
 
 #define MEMPOOL_F_HW_PKT_POOL 0x8000 /**< mpool flag to check offloaded pool */
 
@@ -79,6 +82,23 @@ struct dpaa2_dpbp_dev {
 	uint32_t dpbp_id; /*HW ID for DPBP object */
 };
 
+struct queue_storage_info_t {
+	struct qbman_result *dq_storage[NUM_DQS_PER_QUEUE];
+};
+
+struct dpaa2_queue {
+	struct rte_mempool *mb_pool; /**< mbuf pool to populate RX ring. */
+	void *dev;
+	int32_t eventfd;	/*!< Event Fd of this queue */
+	uint32_t fqid;		/*!< Unique ID of this queue */
+	uint8_t tc_index;	/*!< traffic class identifier */
+	uint16_t flow_id;	/*!< To be used by DPAA2 frmework */
+	uint64_t rx_pkts;
+	uint64_t tx_pkts;
+	uint64_t err_pkts;
+	struct queue_storage_info_t *q_storage;
+};
+
 /*! Global MCP list */
 extern void *(*rte_mcp_ptr_list);
 
-- 
1.9.1