[PATCH v6 23/23] drm/i915/slpc: Enable SLPC, where supported

[Sagar Arun Kamble <sagar.a.kamble@intel.com>]

From: Tom O'Rourke <Tom.O'Rourke@intel.com>

This patch makes SLPC enabled by default on
platforms with hardware/firmware support.

v1: Removing warning "enable_slpc < 0" as it is
set to -1 with this patch now. This was caught by CI BAT.

v2-v4: Rebase.

v5: Sanitizing SLPC option based on capabilities earlier in
driver load for handling uncore sanitization properly.

Testcase: igt/pm_slpc
Signed-off-by: Tom O'Rourke <Tom.O'Rourke@intel.com>
Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
---
 drivers/gpu/drm/i915/i915_params.c | 4 ++--
 drivers/gpu/drm/i915/intel_uc.c    | 9 +++++++++
 2 files changed, 11 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_params.c b/drivers/gpu/drm/i915/i915_params.c
index 6393a17..e4a22ce 100644
--- a/drivers/gpu/drm/i915/i915_params.c
+++ b/drivers/gpu/drm/i915/i915_params.c
@@ -36,7 +36,7 @@ struct i915_params i915 __read_mostly = {
 	.enable_dc = -1,
 	.enable_fbc = -1,
 	.enable_execlists = -1,
-	.enable_slpc = 0,
+	.enable_slpc = -1,
 	.enable_hangcheck = true,
 	.enable_ppgtt = -1,
 	.enable_psr = -1,
@@ -146,7 +146,7 @@ struct i915_params i915 __read_mostly = {
 module_param_named_unsafe(enable_slpc, i915.enable_slpc, int, 0400);
 MODULE_PARM_DESC(enable_slpc,
 	"Override single-loop-power-controller (slpc) usage. "
-	"(-1=auto, 0=disabled [default], 1=enabled)");
+	"(-1=auto [default], 0=disabled, 1=enabled)");
 
 module_param_named_unsafe(enable_psr, i915.enable_psr, int, 0600);
 MODULE_PARM_DESC(enable_psr, "Enable PSR "
diff --git a/drivers/gpu/drm/i915/intel_uc.c b/drivers/gpu/drm/i915/intel_uc.c
index bbb6635..6ba5b86 100644
--- a/drivers/gpu/drm/i915/intel_uc.c
+++ b/drivers/gpu/drm/i915/intel_uc.c
@@ -74,6 +74,15 @@ void intel_uc_sanitize_options(struct drm_i915_private *dev_priv)
 		if (intel_guc_select_fw(&dev_priv->guc))
 			i915.enable_guc_loading = 0;
 	}
+
+	/*
+	 * SLPC runs in GuC and hence depends on GuC parameters. For platforms
+	 * with GuC, this option will be sanitized further in intel_guc_init.
+	 * Sanitize here for all platforms so that gt_powersave/sanitize
+	 * routines get to know whether SLPC or RPS is going to be operational.
+	 */
+	if (i915.enable_slpc < 0)
+		i915.enable_slpc = HAS_SLPC(dev_priv);
 }
 
 void intel_uc_init_early(struct drm_i915_private *dev_priv)
-- 
1.9.1

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