From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751299AbdCQMpw (ORCPT ); Fri, 17 Mar 2017 08:45:52 -0400 Received: from mailapp01.imgtec.com ([195.59.15.196]:50846 "EHLO mailapp01.imgtec.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751011AbdCQMpu (ORCPT ); Fri, 17 Mar 2017 08:45:50 -0400 From: Rahul Bedarkar To: , CC: Rahul Bedarkar , David Woodhouse , Brian Norris , Boris Brezillon , Marek Vasut , Richard Weinberger , Cyrille Pitchen Subject: [RFC 4/6] mtd: m25p80: implement read_xfer and write_xfer Date: Fri, 17 Mar 2017 18:13:54 +0530 Message-ID: <1489754636-21461-5-git-send-email-rahul.bedarkar@imgtec.com> X-Mailer: git-send-email 2.6.2 In-Reply-To: <1489754636-21461-1-git-send-email-rahul.bedarkar@imgtec.com> References: <1489754636-21461-1-git-send-email-rahul.bedarkar@imgtec.com> MIME-Version: 1.0 Content-Type: text/plain X-Originating-IP: [192.168.91.23] Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Implement read_xfer and write_xfer interfaces provided by SPI-NOR. These will be used in upcoming OTP support in SPI-NOR to read/write OTP area. Signed-off-by: Rahul Bedarkar Cc: David Woodhouse Cc: Brian Norris Cc: Boris Brezillon Cc: Marek Vasut Cc: Richard Weinberger Cc: Cyrille Pitchen --- drivers/mtd/devices/m25p80.c | 79 ++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 79 insertions(+) diff --git a/drivers/mtd/devices/m25p80.c b/drivers/mtd/devices/m25p80.c index 8368249..a3ba907 100644 --- a/drivers/mtd/devices/m25p80.c +++ b/drivers/mtd/devices/m25p80.c @@ -186,6 +186,83 @@ static ssize_t m25p80_read(struct spi_nor *nor, loff_t from, size_t len, return ret; } +static ssize_t m25p80_read_xfer(struct spi_nor *nor, + struct spi_nor_xfer_cfg *cfg, + u8 *buf, size_t len) +{ + struct m25p *flash = nor->priv; + struct spi_device *spi = flash->spi; + struct spi_transfer t[2] = {}; + struct spi_message m; + unsigned int dummy = cfg->dummy_cycles; + ssize_t ret; + + /* convert the dummy cycles to the number of bytes */ + dummy /= 8; + + spi_message_init(&m); + + flash->command[0] = cfg->cmd; + m25p_addr2cmd(cfg->addr, cfg->addr_width, flash->command); + + t[0].tx_buf = flash->command; + t[0].len = m25p_cmdsz(cfg->addr_width) + dummy; + spi_message_add_tail(&t[0], &m); + + t[1].rx_buf = buf; + t[1].rx_nbits = m25p80_rx_nbits(cfg->mode); + t[1].len = len; + spi_message_add_tail(&t[1], &m); + + ret = spi_sync(spi, &m); + if (ret) + return ret; + + ret = m.actual_length - m25p_cmdsz(cfg->addr_width) - dummy; + if (ret < 0) + return -EIO; + return ret; +} + +static ssize_t m25p80_write_xfer(struct spi_nor *nor, + struct spi_nor_xfer_cfg *cfg, + u8 *buf, size_t len) +{ + struct m25p *flash = nor->priv; + struct spi_device *spi = flash->spi; + struct spi_transfer t[2] = {}; + struct spi_message m; + unsigned int dummy = cfg->dummy_cycles; + ssize_t ret; + + /* convert the dummy cycles to the number of bytes */ + dummy /= 8; + + spi_message_init(&m); + + flash->command[0] = cfg->cmd; + m25p_addr2cmd(cfg->addr, cfg->addr_width, flash->command); + + t[0].tx_buf = flash->command; + t[0].len = m25p_cmdsz(cfg->addr_width) + dummy; + spi_message_add_tail(&t[0], &m); + + if (len) { + t[1].tx_buf = buf; + t[1].len = len; + spi_message_add_tail(&t[1], &m); + } + + ret = spi_sync(spi, &m); + if (ret) + return ret; + + ret = m.actual_length - m25p_cmdsz(cfg->addr_width) - dummy; + if (ret < 0) + return -EIO; + return ret; +} + /* * board specific setup should have ensured the SPI clock used here * matches what the READ command supports, at least until this driver @@ -213,6 +290,8 @@ static int m25p_probe(struct spi_device *spi) nor->write = m25p80_write; nor->write_reg = m25p80_write_reg; nor->read_reg = m25p80_read_reg; + nor->read_xfer = m25p80_read_xfer; + nor->write_xfer = m25p80_write_xfer; nor->dev = &spi->dev; spi_nor_set_flash_node(nor, spi->dev.of_node); -- 2.6.2