From mboxrd@z Thu Jan 1 00:00:00 1970 From: Rasesh Mody Subject: [PATCH v2 37/61] net/qede/base: remove clock slowdown option Date: Sat, 18 Mar 2017 00:06:02 -0700 Message-ID: <1489820786-14226-38-git-send-email-rasesh.mody@cavium.com> References: <162b5be7-d8a5-0e89-a32f-b1a992aef2a3@intel.com> Mime-Version: 1.0 Content-Type: text/plain Cc: Rasesh Mody , To: , Return-path: Received: from mx0b-0016ce01.pphosted.com (mx0b-0016ce01.pphosted.com [67.231.156.153]) by dpdk.org (Postfix) with ESMTP id C5E8D69C5 for ; Sat, 18 Mar 2017 08:12:07 +0100 (CET) In-Reply-To: <162b5be7-d8a5-0e89-a32f-b1a992aef2a3@intel.com> List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Remove clock slowdown NVM config option as this is not supported for current chipsets. Signed-off-by: Rasesh Mody --- drivers/net/qede/base/nvm_cfg.h | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/drivers/net/qede/base/nvm_cfg.h b/drivers/net/qede/base/nvm_cfg.h index 4202337..4e58835 100644 --- a/drivers/net/qede/base/nvm_cfg.h +++ b/drivers/net/qede/base/nvm_cfg.h @@ -72,10 +72,12 @@ struct nvm_cfg1_glob { #define NVM_CFG1_GLOB_ENABLE_ATC_OFFSET 30 #define NVM_CFG1_GLOB_ENABLE_ATC_DISABLED 0x0 #define NVM_CFG1_GLOB_ENABLE_ATC_ENABLED 0x1 - #define NVM_CFG1_GLOB_CLOCK_SLOWDOWN_MASK 0x80000000 - #define NVM_CFG1_GLOB_CLOCK_SLOWDOWN_OFFSET 31 - #define NVM_CFG1_GLOB_CLOCK_SLOWDOWN_DISABLED 0x0 - #define NVM_CFG1_GLOB_CLOCK_SLOWDOWN_ENABLED 0x1 + #define NVM_CFG1_GLOB_RESERVED__M_WAS_CLOCK_SLOWDOWN_MASK \ + 0x80000000 + #define NVM_CFG1_GLOB_RESERVED__M_WAS_CLOCK_SLOWDOWN_OFFSET 31 + #define NVM_CFG1_GLOB_RESERVED__M_WAS_CLOCK_SLOWDOWN_DISABLED \ + 0x0 + #define NVM_CFG1_GLOB_RESERVED__M_WAS_CLOCK_SLOWDOWN_ENABLED 0x1 u32 engineering_change[3]; /* 0x4 */ u32 manufacturing_id; /* 0x10 */ u32 serial_number[4]; /* 0x14 */ -- 1.7.10.3