From: Praveen Paneri <praveen.paneri@intel.com>
To: intel-gfx@lists.freedesktop.org
Cc: Praveen Paneri <praveen.paneri@intel.com>,
Paulo Zanoni <paulo.r.zanoni@intel.com>
Subject: [PATCH v4] drm/i915: Fix FBC cfb stride programming for non X-tiled FB
Date: Fri, 24 Mar 2017 17:12:44 +0530 [thread overview]
Message-ID: <1490355764-17230-1-git-send-email-praveen.paneri@intel.com> (raw)
In-Reply-To: <CAD6zSYMKRRoRnW4=exa_nhkBq7SVxbKJKwrP9vd-3NiCe3gkwQ@mail.gmail.com>
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When FBC is enabled for linear, legacy Y-tiled and Yf-tiled
surfaces on gen9, the cfb stride must be programmed by SW as
cfb_stride = ceiling[(at least plane width in pixels)/
(32 * compression limit factor)] * 8
v2: Minor fix for a build error
v3: Fixed subject, register name and platform check (Ville)
v4: Added WA details in comment (Paulo)
Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Praveen Paneri <praveen.paneri@intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 3 +++
drivers/gpu/drm/i915/intel_fbc.c | 9 +++++++++
2 files changed, 12 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 04c8f69..4adf2e6 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -6504,6 +6504,9 @@ enum {
#define GLK_CL1_PWR_DOWN (1 << 11)
#define GLK_CL2_PWR_DOWN (1 << 12)
+#define CHICKEN_MISC_4 _MMIO(0x4208c)
+#define FBC_STRIDE_OVERRIDE (1<<13)
+
#define _CHICKEN_PIPESL_1_A 0x420b0
#define _CHICKEN_PIPESL_1_B 0x420b4
#define HSW_FBCQ_DIS (1 << 22)
diff --git a/drivers/gpu/drm/i915/intel_fbc.c b/drivers/gpu/drm/i915/intel_fbc.c
index ded2add..1183633 100644
--- a/drivers/gpu/drm/i915/intel_fbc.c
+++ b/drivers/gpu/drm/i915/intel_fbc.c
@@ -298,9 +298,18 @@ static bool ilk_fbc_is_active(struct drm_i915_private *dev_priv)
static void gen7_fbc_activate(struct drm_i915_private *dev_priv)
{
struct intel_fbc_reg_params *params = &dev_priv->fbc.params;
+ struct intel_fbc_state_cache *cache = &dev_priv->fbc.state_cache;
u32 dpfc_ctl;
int threshold = dev_priv->fbc.threshold;
+ /* Display WA #0529: skl, kbl, bxt, glk */
+ if (IS_GEN9(dev_priv) &&
+ i915_gem_object_get_tiling(cache->vma->obj) != I915_TILING_X) {
+ int cfb_stride = DIV_ROUND_UP(cache->plane.src_w,
+ (32 * threshold)) * 8;
+ I915_WRITE(CHICKEN_MISC_4, FBC_STRIDE_OVERRIDE | cfb_stride);
+ }
+
dpfc_ctl = 0;
if (IS_IVYBRIDGE(dev_priv))
dpfc_ctl |= IVB_DPFC_CTL_PLANE(params->crtc.plane);
--
1.9.1
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next prev parent reply other threads:[~2017-03-24 11:36 UTC|newest]
Thread overview: 23+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-03-15 6:59 [PATCH] drm/i915: Enable FBC for non X-tiled FBs Praveen Paneri
2017-03-15 7:02 ` ✗ Fi.CI.BAT: failure for " Patchwork
2017-03-15 7:43 ` [PATCH v2] " Praveen Paneri
2017-03-15 8:34 ` ✗ Fi.CI.BAT: failure for drm/i915: Enable FBC for non X-tiled FBs (rev2) Patchwork
2017-03-15 8:48 ` ✓ Fi.CI.BAT: success " Patchwork
2017-03-15 10:23 ` [PATCH] drm/i915: Enable FBC for non X-tiled FBs Ville Syrjälä
2017-03-16 11:37 ` Praveen Paneri
2017-03-16 12:08 ` [PATCH v3] drm/i915: Fix FBC cfb stride programming for non X-tiled FB Praveen Paneri
2017-03-16 19:54 ` Paulo Zanoni
2017-03-17 19:12 ` Praveen Paneri
2017-03-24 11:42 ` Praveen Paneri [this message]
2017-07-14 19:34 ` [PATCH v4] " Paulo Zanoni
2017-07-18 18:57 ` [PATCH v5] " Praveen Paneri
2017-07-25 18:29 ` Paulo Zanoni
2017-08-10 18:30 ` [PATCH v6] " Praveen Paneri
2017-08-26 0:49 ` Paulo Zanoni
2017-08-28 6:50 ` Praveen Paneri
2017-03-16 20:13 ` [PATCH] drm/i915: Enable FBC for non X-tiled FBs Ville Syrjälä
2017-03-16 12:28 ` ✓ Fi.CI.BAT: success for drm/i915: Enable FBC for non X-tiled FBs (rev3) Patchwork
2017-03-18 1:35 ` [PATCH] drm/i915: Enable FBC for non X-tiled FBs kbuild test robot
2017-03-24 12:07 ` ✓ Fi.CI.BAT: success for drm/i915: Enable FBC for non X-tiled FBs (rev4) Patchwork
2017-07-18 19:04 ` ✓ Fi.CI.BAT: success for drm/i915: Enable FBC for non X-tiled FBs (rev5) Patchwork
2017-08-11 8:13 ` ✓ Fi.CI.BAT: success for drm/i915: Enable FBC for non X-tiled FBs (rev6) Patchwork
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