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From: Chunming Zhou <David1.Zhou-5C7GfCeVMHo@public.gmane.org>
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org,
	Christian.Koenig-5C7GfCeVMHo@public.gmane.org,
	Alexander.Deucher-5C7GfCeVMHo@public.gmane.org
Cc: "Christian König" <christian.koenig-5C7GfCeVMHo@public.gmane.org>
Subject: [PATCH 02/15] drm/amdgpu: add the VM pointer to the amdgpu_pte_update_params as well
Date: Mon, 27 Mar 2017 13:53:12 +0800	[thread overview]
Message-ID: <1490594005-14553-3-git-send-email-David1.Zhou@amd.com> (raw)
In-Reply-To: <1490594005-14553-1-git-send-email-David1.Zhou-5C7GfCeVMHo@public.gmane.org>

From: Christian König <christian.koenig@amd.com>

This way we save passing it through the different functions.

Change-Id: Id94564a70d106b0ef36c7f45de2b25ca176db2d2
Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 21 +++++++++++----------
 1 file changed, 11 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
index 66f5b91..1f27300 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
@@ -61,6 +61,8 @@
 struct amdgpu_pte_update_params {
 	/* amdgpu device we do this update for */
 	struct amdgpu_device *adev;
+	/* optional amdgpu_vm we do this update for */
+	struct amdgpu_vm *vm;
 	/* address where to copy page table entries from */
 	uint64_t src;
 	/* indirect buffer to fill with commands */
@@ -729,7 +731,6 @@ int amdgpu_vm_update_page_directory(struct amdgpu_device *adev,
  * Update the page tables in the range @start - @end.
  */
 static void amdgpu_vm_update_ptes(struct amdgpu_pte_update_params *params,
-				  struct amdgpu_vm *vm,
 				  uint64_t start, uint64_t end,
 				  uint64_t dst, uint64_t flags)
 {
@@ -745,7 +746,7 @@ static void amdgpu_vm_update_ptes(struct amdgpu_pte_update_params *params,
 	/* initialize the variables */
 	addr = start;
 	pt_idx = addr >> amdgpu_vm_block_size;
-	pt = vm->page_tables[pt_idx].bo;
+	pt = params->vm->page_tables[pt_idx].bo;
 	if (params->shadow) {
 		if (!pt->shadow)
 			return;
@@ -768,7 +769,7 @@ static void amdgpu_vm_update_ptes(struct amdgpu_pte_update_params *params,
 	/* walk over the address space and update the page tables */
 	while (addr < end) {
 		pt_idx = addr >> amdgpu_vm_block_size;
-		pt = vm->page_tables[pt_idx].bo;
+		pt = params->vm->page_tables[pt_idx].bo;
 		if (params->shadow) {
 			if (!pt->shadow)
 				return;
@@ -819,7 +820,6 @@ static void amdgpu_vm_update_ptes(struct amdgpu_pte_update_params *params,
  * @flags: hw mapping flags
  */
 static void amdgpu_vm_frag_ptes(struct amdgpu_pte_update_params	*params,
-				struct amdgpu_vm *vm,
 				uint64_t start, uint64_t end,
 				uint64_t dst, uint64_t flags)
 {
@@ -853,25 +853,25 @@ static void amdgpu_vm_frag_ptes(struct amdgpu_pte_update_params	*params,
 	if (params->src || !(flags & AMDGPU_PTE_VALID) ||
 	    (frag_start >= frag_end)) {
 
-		amdgpu_vm_update_ptes(params, vm, start, end, dst, flags);
+		amdgpu_vm_update_ptes(params, start, end, dst, flags);
 		return;
 	}
 
 	/* handle the 4K area at the beginning */
 	if (start != frag_start) {
-		amdgpu_vm_update_ptes(params, vm, start, frag_start,
+		amdgpu_vm_update_ptes(params, start, frag_start,
 				      dst, flags);
 		dst += (frag_start - start) * AMDGPU_GPU_PAGE_SIZE;
 	}
 
 	/* handle the area in the middle */
-	amdgpu_vm_update_ptes(params, vm, frag_start, frag_end, dst,
+	amdgpu_vm_update_ptes(params, frag_start, frag_end, dst,
 			      flags | frag_flags);
 
 	/* handle the 4K area at the end */
 	if (frag_end != end) {
 		dst += (frag_end - frag_start) * AMDGPU_GPU_PAGE_SIZE;
-		amdgpu_vm_update_ptes(params, vm, frag_end, end, dst, flags);
+		amdgpu_vm_update_ptes(params, frag_end, end, dst, flags);
 	}
 }
 
@@ -911,6 +911,7 @@ static int amdgpu_vm_bo_update_mapping(struct amdgpu_device *adev,
 
 	memset(&params, 0, sizeof(params));
 	params.adev = adev;
+	params.vm = vm;
 	params.src = src;
 
 	ring = container_of(vm->entity.sched, struct amdgpu_ring, sched);
@@ -992,9 +993,9 @@ static int amdgpu_vm_bo_update_mapping(struct amdgpu_device *adev,
 		goto error_free;
 
 	params.shadow = true;
-	amdgpu_vm_frag_ptes(&params, vm, start, last + 1, addr, flags);
+	amdgpu_vm_frag_ptes(&params, start, last + 1, addr, flags);
 	params.shadow = false;
-	amdgpu_vm_frag_ptes(&params, vm, start, last + 1, addr, flags);
+	amdgpu_vm_frag_ptes(&params, start, last + 1, addr, flags);
 
 	amdgpu_ring_pad_ib(ring, params.ib);
 	WARN_ON(params.ib->length_dw > ndw);
-- 
1.9.1

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  parent reply	other threads:[~2017-03-27  5:53 UTC|newest]

Thread overview: 28+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2017-03-27  5:53 [PATCH 00/15] *** Multiple level VMPT enablement *** Chunming Zhou
     [not found] ` <1490594005-14553-1-git-send-email-David1.Zhou-5C7GfCeVMHo@public.gmane.org>
2017-03-27  5:53   ` [PATCH 01/15] drm/amdgpu: rename page_directory_fence to last_dir_update Chunming Zhou
2017-03-27  5:53   ` Chunming Zhou [this message]
2017-03-27  5:53   ` [PATCH 03/15] drm/amdgpu: add num_level to the VM manager Chunming Zhou
     [not found]     ` <1490594005-14553-4-git-send-email-David1.Zhou-5C7GfCeVMHo@public.gmane.org>
2017-03-27 17:05       ` William Lewis
2017-03-27  5:53   ` [PATCH 04/15] drm/amdgpu: generalize page table level Chunming Zhou
2017-03-27  5:53   ` [PATCH 05/15] drm/amdgpu: handle multi level PD size calculation Chunming Zhou
     [not found]     ` <1490594005-14553-6-git-send-email-David1.Zhou-5C7GfCeVMHo@public.gmane.org>
2017-03-28  2:41       ` Zhang, Jerry (Junwei)
2017-03-27  5:53   ` [PATCH 06/15] drm/amdgpu: handle multi level PD during validation Chunming Zhou
2017-03-27  5:53   ` [PATCH 07/15] drm/amdgpu: handle multi level PD in the LRU Chunming Zhou
2017-03-27  5:53   ` [PATCH 08/15] drm/amdgpu: handle multi level PD updates V2 Chunming Zhou
2017-03-27  5:53   ` [PATCH 09/15] drm/amdgpu: handle multi level PD during PT updates Chunming Zhou
2017-03-27  5:53   ` [PATCH 10/15] drm/amdgpu: add alloc/free for multi level PDs V2 Chunming Zhou
2017-03-27  5:53   ` [PATCH 11/15] drm/amdgpu: abstract block size to one function Chunming Zhou
2017-03-27  5:53   ` [PATCH 12/15] drm/amdgpu: limit block size to one page Chunming Zhou
     [not found]     ` <1490594005-14553-13-git-send-email-David1.Zhou-5C7GfCeVMHo@public.gmane.org>
2017-03-28  3:07       ` Zhang, Jerry (Junwei)
2017-03-27  5:53   ` [PATCH 13/15] drm/amdgpu: adapt vm size for multi vmpt Chunming Zhou
     [not found]     ` <1490594005-14553-14-git-send-email-David1.Zhou-5C7GfCeVMHo@public.gmane.org>
2017-03-28  3:19       ` Zhang, Jerry (Junwei)
     [not found]         ` <58D9D656.7090107-5C7GfCeVMHo@public.gmane.org>
2017-03-28  3:43           ` zhoucm1
2017-03-28  8:38           ` Christian König
2017-03-27  5:53   ` [PATCH 14/15] drm/amdgpu: set page table depth by num_level Chunming Zhou
2017-03-27  5:53   ` [PATCH 15/15] drm/amdgpu: enable four level VMPT for gmc9 Chunming Zhou
2017-03-27  9:37   ` [PATCH 00/15] *** Multiple level VMPT enablement *** Christian König
     [not found]     ` <eef2fbb5-8318-4ec3-c91f-b2cb7f9fee86-5C7GfCeVMHo@public.gmane.org>
2017-03-27 16:05       ` Deucher, Alexander
     [not found]         ` <BN6PR12MB1652FBDB212BC00E7461DB84F7330-/b2+HYfkarQqUD6E6FAiowdYzm3356FpvxpqHgZTriW3zl9H0oFU5g@public.gmane.org>
2017-03-28  3:21           ` Zhang, Jerry (Junwei)
2017-03-28 20:14   ` Multilevel page tables broken for high addresses Felix Kuehling
     [not found]     ` <31bd63c4-5ab6-d6f8-8b7c-3411e45c1c57-5C7GfCeVMHo@public.gmane.org>
2017-03-28 20:25       ` Deucher, Alexander
     [not found]         ` <BN6PR12MB16523E15828BC0C8ED26EF04F7320-/b2+HYfkarQqUD6E6FAiowdYzm3356FpvxpqHgZTriW3zl9H0oFU5g@public.gmane.org>
2017-03-28 20:31           ` Felix Kuehling

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