From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752759AbdC0QCv (ORCPT ); Mon, 27 Mar 2017 12:02:51 -0400 Received: from mga03.intel.com ([134.134.136.65]:56938 "EHLO mga03.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751385AbdC0QCn (ORCPT ); Mon, 27 Mar 2017 12:02:43 -0400 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.36,232,1486454400"; d="scan'208";a="81480668" From: kan.liang@intel.com To: peterz@infradead.org, tglx@linutronix.de, mingo@redhat.com, linux-kernel@vger.kernel.org Cc: acme@kernel.org, eranian@google.com, jolsa@kernel.org, ak@linux.intel.com, Kan Liang Subject: [PATCH V2 0/2] measure SMI cost (kernel) Date: Mon, 27 Mar 2017 08:47:36 -0700 Message-Id: <1490629658-4308-1-git-send-email-kan.liang@intel.com> X-Mailer: git-send-email 2.7.4 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Kan Liang Currently, there is no way to measure the time cost in System management mode (SMM) by perf. Intel perfmon supports FREEZE_WHILE_SMM bit in IA32_DEBUGCTL. Once it sets, the PMU core counters will freeze on SMI handler. But it will not have an effect on free running counters. E.g. APERF counter. The cost of SMI can be measured by (aperf - cycles). A new sysfs entry /sys/device/cpu/freeze_on_smi is introduced to set FREEZE_WHILE_SMM bit in IA32_DEBUGCTL. A new --smi-cost mode in perf stat is implemented to measure the SMI cost by calculating cycles and aperf results. In practice, the percentages of SMI cycles should be more useful than absolute value. So the output will be the percentage of SMI cycles and SMI#. If user wants to get the actual cycles, they can apply --no-metric-only. Here is an example output. Performance counter stats for 'sudo echo ': SMI cycles% SMI# 0.1% 1 0.010858678 seconds time elapsed Changes since V1: - Only include kernel patch - New functions to set msr bit on cpu and cpus. Using the new functions to replace rdmsrl_on_cpu and wrmsrl_on_cpu. That avoids the extra IPIs and atomic issue. - Support hotplug Kan Liang (2): x86/msr: add msr_set/clear_bit_on_cpu/cpus access functions perf/x86: add sysfs entry to freeze counter on SMI arch/x86/events/core.c | 10 ++++++ arch/x86/events/intel/core.c | 48 +++++++++++++++++++++++++ arch/x86/events/perf_event.h | 3 ++ arch/x86/include/asm/msr-index.h | 2 ++ arch/x86/include/asm/msr.h | 29 +++++++++++++++ arch/x86/lib/msr-smp.c | 76 ++++++++++++++++++++++++++++++++++++++++ 6 files changed, 168 insertions(+) -- 2.7.4